CN115567805A - System and method for measuring periodic signal - Google Patents

Abstract

The invention provides a method and a system for measuring periodic signals, comprising the following steps: step S1: transmitting a detected signal with a period of T1 to a PAM4 chip, and inputting a synchronous clock to PLL1, wherein the period of the synchronous clock is nT1; step S2: setting a PLL1 and a PLL2 based on a synchronous clock, and enabling the PLL2 to output a high-precision sampling trigger clock; and step S3: an analog unit built in a PAM4 chip preprocesses a detected signal and then transmits the signal to an ADC (analog to digital converter), and the ADC converts the preprocessed detected signal into a digital signal according to a sampling trigger clock and stores the digital signal in an FIFO (first in first out) memory space; and step S4: the MCU transmits the sampled data in the FIFO memory space to the PC, and the PC calculates the test index of the signal to be tested through digital processing; step S5: reconstructing the sampled data by the PC to recover a signal to be detected; step S6: and displaying the recovered signal to be tested and the calculated test index of the signal to be tested through a display screen.

Description

System and method for measuring periodic signal

Technical Field

The invention relates to the technical field of optical network communication, in particular to a periodic signal measuring system and a periodic signal measuring method, and more particularly to a periodic signal measuring system and a periodic signal measuring method based on a PAM4 network chip.

Background

In the field of research and development and production of optical modules, eye pattern analysis and eye pattern template testing are required, and sampling oscilloscopes are widely used due to the characteristics of high bandwidth, high resolution, low noise and the like. The sampling oscilloscope is mainly designed for measuring periodic signals, is different from a real-time oscilloscope, only samples data once when a trigger signal arrives each time, and samples the signals again by adding a small delay behind the trigger signal when the trigger signal is triggered next time until a complete periodic waveform is sampled. Because the sampling oscilloscope reconstructs signals by repeatedly sampling for many times, even if the frequency of the measured signals is high, the signals can be reconstructed point by a low sampling rate.

The structure of the sampling oscilloscope is shown in figure 1 and comprises two parts, namely a host and a plugging module. The host computer comprises an ADC converter, an FIFO memory, a synchronous generator, a sequential delay generator, a microprocessor system and the like. The plug-in module comprises a sampling head and an amplifier. The sampling head changes the high-speed signal into a short-time direct-current signal, and the ADC of the host computer is digitized after the signal is amplified. And the data of each short-time direct current signal are combined together to form a waveform which can be displayed on a screen, and the waveform information (time, amplitude and the like) is displayed as the information of a real signal through mathematical operation.

The principle and method of the conventional test system are as follows:

1. and respectively connecting the tested signal and the synchronous clock to the oscilloscope, wherein the period of the tested signal is T1, and the period of the synchronous clock is nT1.

2. The sequential delay generator delays the synchronous clock by delta T to the ADC as a sampling trigger clock.

3. The ADC converts the signal under test into a digital signal according to the delayed sampling pulse and stores the digital signal in the FIFO memory space, and the sampling process is shown in fig. 2.

4. The microprocessor system processes the sampling data in the FIFO memory digitally to calculate various indexes of the detected signal, such as eye height, eye width, eye pattern template tolerance, SNR, etc., and reconstructs the sampling data to restore the detected signal and display it on the screen.

The conventional test method has at least the following disadvantages: 1. the volume is large, the weight is heavy, and the carrying and the moving are not easy; 2. the system is complex, and the design, development and production periods are long; 3. the cost is high, and the purchase price of a sampling oscilloscope for measuring 28Gps speed signals is more than 30 ten thousand RMB. Therefore, a new test system and method are needed to solve the above problems.

Patent document CN112462121B (application number: 202011092482. X) discloses an eye pattern filter system and an eye pattern test method, the system including: the device comprises an equalizer, a clock data recovery circuit and an eye pattern oscilloscope; after the input signal is regulated by the equalizer, the input clock data recovery circuit recovers the clock information of the input signal and inputs the clock information and the input signal into the eye pattern oscilloscope; the eye chart oscilloscope comprises an algorithm logic module, a first phase interpolator and a first sampler; and the algorithm logic module controls the first phase interpolator to output a clock to traverse N phases and controls the threshold voltage of the first sampler to traverse M voltage values, so that the error rate of each phase and each voltage value is tested, and the eye diagram of M x N test points is obtained.

Disclosure of Invention

In view of the defects in the prior art, the present invention provides a method and a system for measuring a periodic signal.

The invention provides a periodic signal measuring method, which comprises the following steps:

step S1: transmitting a detected signal with a period of T1 to a PAM4 chip, and inputting a synchronous clock to PLL1, wherein the period of the synchronous clock is nT1;

step S2: setting a PLL1 and a PLL2 based on a synchronous clock, and enabling the PLL2 to output a high-precision sampling trigger clock;

and step S3: an analog unit built in a PAM4 chip preprocesses a detected signal and then transmits the signal to an ADC (analog to digital converter), and the ADC converts the preprocessed detected signal into a digital signal according to a sampling trigger clock and stores the digital signal in an FIFO (first in first out) memory space;

and step S4: the MCU transmits the sampling data in the FIFO memory space to the PC, and the PC calculates the test index of the signal to be tested through digital processing;

step S5: reconstructing the sampled data by the PC to recover a signal to be detected;

step S6: and displaying the recovered signal to be tested and the calculated test index of the signal to be tested through a display screen.

Preferably, the PLL1 employs: the PLL1 selects either the synchronization signal or the crystal as the reference clock.

Preferably, the high-precision sampling trigger clock output by the PLL2 adopts:

T2＝nT1+ΔT

wherein, Δ T and the highest frequency f of the signal to be measured should satisfy the nyquist sampling theorem: delta T is less than or equal to 1/2f.

Preferably, the sampling period is T2, and after m times of sampling, one sampling cycle of the periodic signal is completed, and the relationship between one sampling cycle period T and the measured signal period T1 is T = m (nT 1+ Δ T) = (mn + 1) T1.

Preferably, the test indexes of the signal to be tested include: eye height, eye width, eye template tolerance, and SNR.

Preferably, the step S5 adopts: according to the nyquist theorem, when the sampling frequency is greater than 2 times of the maximum frequency in the signal, the original signal is recovered.

The invention provides a periodic signal measuring system, which comprises:

a module M1: transmitting a detected signal with a period of T1 to a PAM4 chip, and inputting a synchronous clock to PLL1, wherein the period of the synchronous clock is nT1;

a module M2: setting a PLL1 and a PLL2 based on a synchronous clock, and enabling the PLL2 to output a high-precision sampling trigger clock;

a module M3: an analog unit built in a PAM4 chip preprocesses a detected signal and then transmits the signal to an ADC (analog to digital converter), and the ADC converts the preprocessed detected signal into a digital signal according to a sampling trigger clock and stores the digital signal in an FIFO (first in first out) memory space;

a module M4: the MCU transmits the sampling data in the FIFO memory space to the PC, and the PC calculates the test index of the signal to be tested through digital processing;

a module M5: the PC machine reconstructs the sampled data to recover a signal to be detected;

a module M6: and displaying the recovered signal to be tested and the calculated test index of the signal to be tested through a display screen.

Preferably, the PLL1 employs: the PLL1 selects either the synchronization signal or the crystal as the reference clock.

Preferably, the high-precision sampling trigger clock output by the PLL2 adopts:

T2＝nT1+ΔT

wherein, Δ T and the highest frequency f of the signal to be measured should satisfy the nyquist sampling theorem: delta T is less than or equal to 1/2f;

the sampling period is T2, and after m times of sampling, one sampling cycle of the periodic signal is completed, and the relationship between one sampling cycle period T and the measured signal period T1 is T = m (nT 1+ Δ T) = (mn + 1) T1.

Preferably, the test indexes of the signal to be tested include: eye height, eye width, eye template tolerance, and SNR.

Compared with the prior art, the invention has the following beneficial effects:

1. the volume is small, the weight is light, and the carrying and the moving are easy;

2. the invention utilizes the PLL with wide application to control the sampling trigger clock, does not need a special delay generator and simplifies the design;

3. according to the invention, complex and expensive components in the sampling oscilloscope are replaced by functions integrated in the PAM4 network chip, so that the integration level is improved, and the production period and the production cost are reduced;

4. the invention can avoid using expensive test equipment in some specific fields, thus reducing the test cost;

drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic diagram of a sampling oscilloscope.

Fig. 2 is a schematic diagram of a sampling process of the sampling oscilloscope.

FIG. 3 is a schematic diagram of a system for measuring a periodic signal.

Fig. 4 is a schematic diagram of a measurement sampling process of a periodic signal.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the invention.

Example 1

The invention aims to provide a periodic signal measuring system and method based on a PAM4 network chip aiming at the defects in the prior art. The PAM4 network chip is widely used in optical network communication, is a main component of an optical module, and integrates units such as analog signal processing (including AGC (automatic gain control), VGA (variable gain amplifier), weighting, equalization, etc.), ADC (analog-to-digital converter), PLL (phase locked loop), FIFO memory, CDR (clock data recovery), etc. inside the chip. Analog signal processing including filtering, amplification and emphasis processing is carried out on the signal to be detected, the ADC samples the signal to be detected, and mathematical operation is carried out on the sampled data, so that the waveform can be recovered. The CDR functions mainly to track the signal to be measured. The invention is based on PAM4 network chip, makes full use of the analog and digital units integrated in it, and PLL, MCU, PC, etc. to form a periodic signal test system, as shown in FIG. 3.

The invention provides a periodic signal measuring method, which comprises the following steps:

step S1: transmitting a detected signal with a period of T1 to a PAM4 chip, and inputting a synchronous clock to PLL1, wherein the period of the synchronous clock is nT1;

step S2: setting a PLL1 and a PLL2 based on a synchronous clock, and enabling the PLL2 to output a high-precision sampling trigger clock;

and step S3: an analog unit built in a PAM4 chip preprocesses a detected signal and then transmits the signal to an ADC (analog to digital converter), and the ADC converts the preprocessed detected signal into a digital signal according to a sampling trigger clock and stores the digital signal in an FIFO (first in first out) memory space;

and step S4: the MCU transmits the sampling data in the FIFO memory space to the PC, and the PC calculates the preset index of the signal to be detected through digital processing;

step S5: the PC machine reconstructs the sampled data to recover a signal to be detected;

step S6: and displaying the recovered signal to be tested and the calculated test index of the signal to be tested through a display screen.

Specifically, the PLL1 employs: the PLL1 selects the synchronization signal or crystal as the reference clock. PLL1 outputs clock to PLL2 for reference, and PLL2 outputs clock to ADC for sampling trigger.

Specifically, the high-precision sampling trigger clock output by the PLL2 adopts:

T2＝nT1+ΔT

wherein, Δ T and the highest frequency f of the signal to be measured should satisfy the nyquist sampling theorem: delta T is less than or equal to 1/2f.

Specifically, the sampling period is T2, one sampling cycle of the periodic signal is completed after m times of sampling, the relationship between one sampling cycle period T and the measured signal period T1 is T = m (nT 1+ Δ T) = (mn + 1) T1, and the sampling process is as shown in fig. 4.

Specifically, the test indexes of the signal to be tested include: eye height, eye width, eye pattern template tolerance, and SNR.

Specifically, the step S5 employs: according to the nyquist theorem, when the sampling frequency is greater than 2 times of the maximum frequency in the signal, the original signal can be recovered.

The invention provides a periodic signal measuring system, which comprises:

a module M1: transmitting a detected signal with a period of T1 to a PAM4 chip, and inputting a synchronous clock to PLL1, wherein the period of the synchronous clock is nT1;

a module M2: setting a PLL1 and a PLL2 based on a synchronous clock, and enabling the PLL2 to output a high-precision sampling trigger clock;

a module M3: an analog unit built in a PAM4 chip preprocesses a detected signal and then transmits the signal to an ADC (analog to digital converter), and the ADC converts the preprocessed detected signal into a digital signal according to a sampling trigger clock and stores the digital signal in an FIFO (first in first out) memory space;

a module M4: the MCU transmits the sampling data in the FIFO memory space to the PC, and the PC calculates the test index of the signal to be tested through digital processing;

a module M5: the PC machine reconstructs the sampled data to recover a signal to be detected;

a module M6: and displaying the recovered signal to be tested and the calculated test index of the signal to be tested through a display screen.

Specifically, the PLL1 employs: the PLL1 selects either the synchronization signal or the crystal as the reference clock. PLL1 outputs clock to PLL2 for reference, and PLL2 outputs clock to ADC for sampling trigger.

Specifically, the high-precision sampling trigger clock output by the PLL2 adopts:

T2＝nT1+ΔT

wherein, Δ T and the highest frequency f of the signal to be measured should satisfy the nyquist sampling theorem: delta T is less than or equal to 1/2f.

Specifically, the sampling period is T2, one sampling cycle of the periodic signal is completed after m times of sampling, the relationship between one sampling cycle period T and the measured signal period T1 is T = m (nT 1+ Δ T) = (mn + 1) T1, and the sampling process is as shown in fig. 4.

Specifically, the test indexes of the signal to be tested include: eye height, eye width, eye pattern template tolerance, and SNR.

Specifically, the module M5 employs: according to the nyquist theorem, when the sampling frequency is greater than 2 times of the maximum frequency in the signal, the original signal can be restored.

Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (10)

1. A method for measuring a periodic signal, comprising:

step S1: transmitting a detected signal with a period of T1 to a PAM4 chip, and inputting a synchronous clock to PLL1, wherein the period of the synchronous clock is nT1;

step S2: setting a PLL1 and a PLL2 based on a synchronous clock, and enabling the PLL2 to output a high-precision sampling trigger clock;

and step S3: an analog unit built in a PAM4 chip preprocesses a detected signal and then transmits the signal to an ADC (analog to digital converter), and the ADC converts the preprocessed detected signal into a digital signal according to a sampling trigger clock and stores the digital signal in an FIFO (first in first out) memory space;

and step S4: the MCU transmits the sampled data in the FIFO memory space to the PC, and the PC calculates the test index of the signal to be tested through digital processing;

step S5: reconstructing the sampled data by the PC to recover a signal to be detected;

step S6: and displaying the recovered signal to be tested and the calculated test index of the signal to be tested through a display screen.

2. The method for measuring a periodic signal according to claim 1, wherein the PLL1 employs: the PLL1 selects either the synchronization signal or the crystal as the reference clock.

3. The method for measuring a periodic signal according to claim 1, wherein the high-precision sampling trigger clock output by the PLL2 comprises:

T2＝nT1+ΔT

wherein, Δ T and the highest frequency f of the measured signal should satisfy nyquist sampling theorem: delta T is less than or equal to 1/2f.

4. The method according to claim 1, wherein the sampling period is T2, and after m samples, one sampling cycle of the periodic signal is completed, and the relationship between one sampling cycle period T and the measured signal period T1 is T = m (nT 1+ Δ T) = (mn + 1) T1.

5. The method according to claim 1, wherein the test indicators of the signal under test comprise: eye height, eye width, eye template tolerance, and SNR.

6. The method for measuring a periodic signal according to claim 1, wherein the step S5 comprises: according to the nyquist theorem, when the sampling frequency is greater than 2 times of the maximum frequency in the signal, the original signal can be recovered.

7. A system for measuring a periodic signal, comprising:

a module M1: transmitting a detected signal with a period of T1 to a PAM4 chip, and inputting a synchronous clock to PLL1, wherein the period of the synchronous clock is nT1;

a module M2: setting a PLL1 and a PLL2 based on a synchronous clock, and enabling the PLL2 to output a high-precision sampling trigger clock;

a module M3: an analog unit built in a PAM4 chip preprocesses a detected signal and then transmits the signal to an ADC (analog to digital converter), and the ADC converts the preprocessed detected signal into a digital signal according to a sampling trigger clock and stores the digital signal in an FIFO (first in first out) memory space;

a module M4: the MCU transmits the sampled data in the FIFO memory space to the PC, and the PC calculates the test index of the signal to be tested through digital processing;

a module M5: the PC machine reconstructs the sampled data to recover a signal to be detected;

a module M6: and displaying the recovered signal to be tested and the calculated test index of the signal to be tested through a display screen.

8. The periodic signal measurement system according to claim 7, wherein the PLL1 employs: the PLL1 selects the synchronization signal or crystal as the reference clock.

9. The periodic signal measuring system according to claim 7, wherein the high-precision sampling trigger clock output by the PLL2 is:

T2＝nT1+ΔT

wherein, Δ T and the highest frequency f of the signal to be measured should satisfy the nyquist sampling theorem: delta T is less than or equal to 1/2f;

the sampling period is T2, and after m times of sampling, one sampling cycle of the periodic signal is completed, and the relationship between one sampling cycle period T and the measured signal period T1 is T = m (nT 1+ Δ T) = (mn + 1) T1.

10. The system of claim 7, wherein the test indicators of the signal under test comprise: eye height, eye width, eye pattern template tolerance, and SNR.

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