CN115550784A - Safe earphone amplifier based on high-speed sampling technology - Google Patents
Safe earphone amplifier based on high-speed sampling technology Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R1/00—Details of transducers, loudspeakers or microphones
- H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R3/00—Circuits for transducers, loudspeakers or microphones
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
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Abstract
The invention provides a high-speed sampling technology-based safe earphone amplifier, which is provided with two DSP chips, wherein the first DSP chip works at 100kHz and keeps a certain difference frequency with an audio signal, and the ultrahigh frequency DSP chip works by frequency multiplication of the audio signal and corrects the output result of the first DSP chip, thereby ensuring that the noise of equipment can be effectively collected, the control cooperativity can be ensured, and the first DSP chip can have good processing speed during control.
Description
Technical Field
The invention relates to the field of audio amplifiers, in particular to a safe earphone amplifier based on a high-speed sampling technology.
Background
A power amplifier refers to an amplifier that produces maximum power output to drive a load (e.g., a speaker) at a given distortion rate. The power amplifier plays a role of 'organization and coordination' in the whole sound system, and governs to some extent whether the whole system can provide good sound quality output.
For example, application No. CN201910096690.8 discloses a digital power amplifier system, which includes a first component branch and a second component branch, where the first component branch includes: a first switch structure and a first current source in series, the first current source comprising: fourth resistance, first field effect transistor, second field effect transistor and second operational amplifier, the second branch of composition includes: a second switch structure and a second current source in series, the second current source comprising: and when the fifth resistor, the third field effect transistor, the fourth field effect transistor and the third operational amplifier are applied to a digital power amplifier system, the equivalent output impedance of the digital-analog converter is increased, and the power supply rejection ratio of the digital power amplifier system is reduced. The traditional power amplifier adopts analog bias, and has large discreteness and poor bias following performance.
The company has developed a headphone amplifier before, and the signal collected by the DSP is matched with a pre-established power amplifier level bias model in a unit of 5mS, and whether an overload trend exists or not is detected, and whether the power amplifier is about to exceed a bias linear interval or not is detected, so as to determine whether the power amplifier bias is adjusted or not, and a strong overload trend (short circuit) exists, and the power amplifier last stage is closed in time; for the deviation execution exceeding advanced region (A type region), overfitting compensation is carried out to a certain degree, so that the power amplification stage is always in a high-linearity region, fixed deviation execution current is reduced, and power consumption is reduced; the equipment is protected.
At present, however, the sampling rate of the audio format is generally 44.1kHz, 48kHz or 96kHz, since the amplifier generally works in an analog signal mode, the noise of the device itself is not the same as the sampling rate of the audio format, directly adopting the DSP sampling rate which is the same as the audio format will cause the noise generated by the device itself to be effectively collected, and adopting other frequencies will cause the control synchronism to be reduced, and if the DSP is directly adopted for control, the control delay will be higher due to the larger calculation amount.
Disclosure of Invention
In order to solve the above problems, the present invention provides a safe headphone amplifier based on a high-speed sampling technique, comprising: the device comprises an input end, a bias power amplifier module and an output end; the system also comprises an information acquisition module, a frequency multiplication sampling module, an ultrahigh frequency DSP, a current sampling module, an analog-to-digital conversion module, a first digital signal processor/DSP, a digital-to-analog converter, a low-pass filter, a current-voltage converter and a current control voltage module;
the bias power amplifier module is respectively connected with an input end and an output end, wherein the input end is used for inputting signals, amplifying the signals after the signals pass through the bias amplifier, and then outputting the signals through the output end;
the information acquisition module is used for acquiring the data format of the played audio through the input end, including the sampling rate of the audio; and sending the sampling rate to a frequency multiplication sampling module;
the frequency doubling sampling module performs frequency doubling sampling from the output end based on the sampling rate of the audio, and the frequency doubling sampling is multiple k; the frequency multiplication sampling module sends frequency multiplication samples to the ultrahigh frequency DSP; the ultrahigh frequency DSP processes the frequency multiplication sampling to obtain voltage correction data, and the voltage correction data is input into the first DSP;
the current sampling module is connected with the bias power amplifier module and is used for copying proportional current of an output stage of the bias power amplifier module, and then the copied current is converted into a digital signal through the analog-to-digital conversion module and is input into the first DSP;
the signal output by the analog-to-digital converter is input into a power amplifier bias model in a first DSP for calculation, and the first DSP outputs voltage control data by combining voltage correction data;
after the voltage control data are input into the digital-to-analog converter, the voltage control data enter the current-to-voltage converter through the low-pass filter to obtain control current; the control current is input into the current control voltage module to obtain the regulated voltage, and the regulated voltage and the input signal are loaded to the bias amplification module together.
Carrying out model matching on the signal acquired by the DSP and a pre-established power amplifier bias model by taking 5ms as a unit; the sampling rate of the analog-to-digital converter and the digital-to-analog converter is 100kHz.
The sampling rate of the audio acquired by the information acquisition module is the sampling rate of a played audio file or the sampling rate of an audio track of a played video file; the sampling rate is 44.1kHz, 48kHz or 96kHz; the multiple k of frequency multiplication is 2, 4, 8 or 16;
the frequency doubling sampling module collects ultrahigh frequency data and sends the ultrahigh frequency data to the ultrahigh frequency DSP; the ultrahigh frequency DSP performs real-time fast Fourier transform on the input data to obtain a frequency spectrum curve of the ultrahigh frequency data, and calculates the total energy E of the frequency spectrum curve;
the ultrahigh frequency DSP converts the total energy E and the energy threshold E 0 Comparing and calculating V k ＝A〃(E-E 0 ) (ii) a Wherein A is a coefficient of less than 0, V k Correcting the data for the voltage; because the ultrahigh frequency DSP converts signals in real time, E and V k Are all time-varying quantities.
The power amplifier bias model comprises two parts, wherein the first part is an overload identification model and is used for detecting whether an overload trend exists and carrying out corresponding control, and the second part is a compensation model and is used for detecting whether the power amplifier is about to exceed a bias linear interval and applying corresponding control;
the working process of the overload identification model is as follows:
performing time domain-frequency domain transformation on the digital signal input into the first DSP at fixed time intervals, wherein the transformation mode is Fourier transformation or wavelet transformation; the frequency domain signal carries out waveform energy calculation in real time, waveform energy is compared with an energy threshold value, and if the waveform energy exceeds the energy threshold value, the first DSP controls to close the final stage of the power amplifier;
wherein the energy threshold is a curve varying with frequency, i.e. the energy threshold G is a function G (f), wherein f represents the frequency of the signal; the waveform energy solved in real time is also a curve changing along with the frequency, the signal energy of different frequencies is different, and the waveform energy H is a function H (f);
calculating Y (f) = H (f) -G (f), and when any value of Y (f) is less than 0, the first DSP controls to close the power amplification final stage;
the working process of the compensation model is as follows:
performing time domain-frequency domain transformation on the digital signal input into the first DSP at fixed time intervals, wherein the transformation mode is Fourier transformation or wavelet transformation; the first DSP performs feature extraction on the frequency domain signal, and the extracted features comprise the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max The energy value sum M of the characteristic frequency section; wherein the characteristic frequency segment is a preset frequency range;
the first DSP converts the pattern of the frequency domain signal and the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max The energy value sum M of the characteristic frequency section is used as a parameter to be input into the neural network model to obtainVoltage V 0 。
V 0 Is a time-varying quantity, V = V is calculated in the first DSP 0 +V k V is voltage control data;
after the voltage control data are input into the digital-to-analog converter, the voltage control data enter the current-to-voltage converter through the low-pass filter to obtain control current; the control current is input into the current control voltage module to obtain a regulated voltage, and the regulated voltage and the input signal are loaded to the bias amplification module;
when the total energy E of the spectrum curve exceeds E0, V k The voltage is negative, so that the bias voltage of the adjusting voltage is reduced, and the distortion of the bias power amplifier module is further reduced; when the total energy E is less than E 0 When, V k The voltage is positive, so that the voltage bias is increased, and the working effect of the power amplifier module is ensured.
The current sampling module comprises a circuit for current-voltage conversion and low-pass filtering at the same time, and converts a current signal into a voltage signal and performs low-pass filtering at the same time; the purpose of the low-pass filtering is to remove out-of-band interference.
The bias power amplifier module comprises two resistors R3 and R4 which are connected in series, an NPN triode Q6 and a PNP triode Q4; the base electrode of the NPN triode Q6 and the base electrode of the PNP triode Q4 are both connected with the driving output; two resistors connected in series are connected between the emitter of the NPN triode Q6 and the emitter of the PNP triode Q4, and an output is formed between the two resistors connected in series;
the collector of NPN triode Q6 is connected with vcc, and the base of PNP triode Q4 is connected with vee.
The first DSP chip used the Texas Instruments TMS320C6713B series.
The maximum clock frequency of the ultrahigh frequency DSP chip is 300MHz.
The invention has the beneficial effects that:
the invention sets two DSP chips, the first DSP chip works at 100kHz and keeps a certain difference frequency with the audio signal, the ultrahigh frequency DSP chip works with the frequency multiplication of the audio signal and corrects the result output by the first DSP chip, thereby not only ensuring that the noise of the equipment can be effectively collected and the control cooperativity, but also ensuring that the first DSP chip can have good processing speed when in control.
Aiming at the time domain-frequency domain transformation of a signal input in a DSP, waveform energy of a frequency domain is compared with an energy threshold value, and if the waveform energy exceeds the energy threshold value, the DSP controls to close a power amplifier final stage; the pattern of the frequency domain signal and the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max The energy value sum M of the characteristic frequency section is used as input, the corresponding voltage control data is used as output to construct a neural network model, the data processing speed and accuracy are greatly improved, the bias following problem is improved, and meanwhile the circuit is effectively protected.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic diagram of the overall architecture of the present invention;
fig. 2 is a block diagram of a portion of the circuit of the present invention.
Wherein Q represents a triode and R represents a resistor; q4, Q6, R3 and R4 form the output stage of the power amplifier; q1, Q2, Q3, Q5, Q7, Q8, R1, R2, R5, R6 and R8 constitute a proportional current replicator of the power output stage; and finishing current-voltage conversion at R7 and OP-1, and forming a low-pass filter by C1 and R7 to remove out-of-band interference.
Detailed Description
Example 1:
referring to fig. 1, the present invention provides a high-speed sampling technology-based secure headphone amplifier, including: the device comprises an input end, a bias power amplifier module and an output end; the system also comprises an information acquisition module, a frequency doubling sampling module, an ultrahigh frequency DSP, a current sampling module, an analog-to-digital conversion module, a first digital signal processor/DSP, a digital-to-analog converter, a low-pass filter, a current-voltage converter and a current control voltage module;
the bias power amplifier module is respectively connected with an input end and an output end, wherein the input end is used for inputting signals, amplifying the signals after passing through the bias amplifier, and then outputting the signals through the output end;
the information acquisition module is used for acquiring a data format of the played audio through the input end, wherein the data format comprises the sampling rate of the audio; and sending the sampling rate to a frequency multiplication sampling module;
the frequency multiplication sampling module carries out frequency multiplication sampling from the output end based on the sampling rate of the audio frequency, and the frequency multiplication sampling is multiple k; the frequency multiplication sampling module sends frequency multiplication samples to the ultrahigh frequency DSP; the ultrahigh frequency DSP processes the frequency multiplication sampling to obtain voltage correction data, and the voltage correction data is input into the first DSP;
the current sampling module is connected with the bias power amplification module and is used for carrying out proportional current copying on the output stage of the bias power amplification module, and then the copied current is converted into a digital signal through the analog-to-digital conversion module and is input into the first DSP;
the signal output by the analog-to-digital converter is input into a power amplifier bias model in a first DSP for calculation, and the first DSP outputs voltage control data by combining voltage correction data;
after the voltage control data are input into the digital-to-analog converter, the voltage control data enter the current-to-voltage converter through the low-pass filter to obtain control current; the control current is input into the current control voltage module to obtain the regulated voltage, and the regulated voltage and the input signal are loaded to the bias amplification module together.
Carrying out model matching on the signal acquired by the DSP and a pre-established power amplifier bias model by taking 5ms as a unit; the sampling rate of the analog-to-digital converter and the digital-to-analog converter is 100kHz.
The sampling rate of the audio acquired by the information acquisition module is the sampling rate of a played audio file or the sampling rate of an audio track of a played video file; the sampling rate is 44.1kHz, 48kHz or 96kHz; the multiple k of frequency multiplication is 2, 4, 8 or 16;
the frequency doubling sampling module collects ultrahigh frequency data and sends the ultrahigh frequency data to the ultrahigh frequency DSP; the ultrahigh frequency DSP performs real-time fast Fourier transform on the input data to obtain a frequency spectrum curve of the ultrahigh frequency data, and calculates the total energy E of the frequency spectrum curve;
the ultrahigh frequency DSP compares the total energy E with an energy threshold E0 and calculates V k ＝A〃(E-E 0 ) (ii) a Wherein A is a coefficient of less than 0, V k Correcting the data for the voltage; because the ultrahigh frequency DSP converts signals in real time, E and V k Are all time-varying quantities.
The power amplifier bias model comprises two parts, wherein the first part is an overload identification model and is used for detecting whether an overload trend exists and carrying out corresponding control, and the second part is a compensation model and is used for detecting whether the power amplifier is about to exceed a bias linear interval and applying corresponding control;
the working process of the overload identification model is as follows:
performing time domain-frequency domain transformation on the digital signal input into the first DSP at fixed time intervals, wherein the transformation mode is Fourier transformation or wavelet transformation; the frequency domain signal carries out waveform energy calculation in real time, waveform energy is compared with an energy threshold value, and if the waveform energy exceeds the energy threshold value, the first DSP controls the power amplifier final stage to be closed;
wherein the energy threshold is a curve varying with frequency, i.e. the energy threshold G is a function G (f), wherein f represents the frequency of the signal; the waveform energy solved in real time is also a curve changing along with the frequency, the signal energy of different frequencies is different, and the waveform energy H is a function H (f);
calculating Y (f) = H (f) -G (f), and when any value of Y (f) is less than 0, the first DSP controls to close the power amplification final stage;
the working process of the compensation model is as follows:
performing time domain-frequency domain transformation on the digital signal input into the first DSP at fixed time intervals, wherein the transformation mode is Fourier transformation or wavelet transformation; the first DSP performs feature extraction on the frequency domain signal, and the extracted features comprise the strongest frequency F max 、F max Corresponding peak heights Pmax, F max Corresponding full width at half maximum W max The energy value sum M of the characteristic frequency section; wherein the characteristicsThe frequency section is a preset frequency range;
the first DSP converts the pattern of the frequency domain signal and the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max Inputting the energy value sum M of the characteristic frequency section as a parameter into the neural network model to obtain a voltage V 0 。
V 0 Is a time-varying quantity, V = V is calculated in the first DSP 0 +V k V is voltage control data;
after voltage control data are input into the digital-to-analog converter, the voltage control data enter the current-to-voltage converter through the low-pass filter to obtain control current; the control current is input into the current control voltage module to obtain a regulated voltage, and the regulated voltage and the input signal are loaded to the bias amplification module together;
when the total energy E of the spectrum curve exceeds E 0 When, V k The bias voltage of the adjusting voltage is reduced, and the distortion of the bias power amplifier module is further reduced; when the total energy E is less than E 0 When, V k The voltage is positive, so that the voltage bias is increased, and the working effect of the power amplifier module is ensured.
The training method of the neural network model comprises the following steps:
a set of power amplifiers with the same structure as that in actual use are installed in a laboratory and are controlled to work, and the difference is that voltage control data output by a DSP is set as random numbers;
performing time domain-frequency domain transformation on the digital signals input into the DSP at fixed time intervals, wherein the transformation mode is Fourier transformation or wavelet transformation; the DSP performs feature extraction on the frequency domain signal, and the extracted features comprise the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max The energy value sum M of the characteristic frequency section;
monitoring the time period of returning to the linear interval after the power amplifier exceeds the bias linear interval in real time, and extracting data in the time period; extracting a graph comprising a frequency domain signal and the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max The energy value sum M of the characteristic frequency section and corresponding voltage control data;
the pattern of the frequency domain signal and the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max Taking the energy value sum M of the characteristic frequency section as input, and taking corresponding voltage control data as output to construct a neural network model; the type of the neural network model is a convolutional neural network model.
Example 2:
fig. 2 is a circuit structure diagram of the present invention:
the current sampling module comprises a circuit for current-voltage conversion and low-pass filtering at the same time, and the circuit converts a current signal into a voltage signal and performs low-pass filtering at the same time; the purpose of the low-pass filtering is to remove out-of-band interference.
The collector of NPN triode Q6 is connected with vcc, and the base of PNP triode Q4 is connected with vee.
The first DSP chip used the Texas Instruments TMS320C6713B series.
The maximum clock frequency of the ultrahigh frequency DSP chip is 300MHz.
The bias power amplifier module comprises two resistors R3 and R4 which are connected in series, an NPN triode Q6 and a PNP triode Q4; the base electrode of the NPN triode Q6 and the base electrode of the PNP triode Q4 are connected with the driving output; two resistors connected in series are connected between the emitter of the NPN triode Q6 and the emitter of the PNP triode Q4, and an output is formed between the two resistors connected in series;
the collector of the NPN triode Q6 is connected with vcc, and the base of the PNP triode Q4 is connected with vee.
Q1, Q2, Q3, Q5, Q7, Q8, R1, R2, R5, R6 and R8 constitute a proportional current duplicator of the power output stage.
R7, OP-1 and C1 are connected in parallel to form a circuit for current-voltage conversion and low-pass filtering, and the circuit converts a current signal into a voltage signal and performs low-pass filtering; the purpose of the low-pass filtering is to remove out-of-band interference.
Q1, Q2, Q3, Q5 are PNP triode, Q7, Q8 are NPN triode; one ends of R1, R2 and R5 are connected with Vcc, the other end of R1 is connected with an emitting electrode of Q1, the other end of R2 is connected with an emitting electrode of Q2, the other end of R3 is connected with an emitting electrode of Q3 and a base electrode of Q5, the emitting electrode of Q5 is connected with Vcc, and a collector electrode of Q5 is grounded through R6 after being connected with the base electrode of Q3;
the collector and the base of Q1 are connected and then connected to the collector of Q7, the emitter of Q7 is connected with the emitter of Q6, and the base of Q7 is connected with the base of Q8, the collector of Q8 and the collector of Q3; the collector of Q2 is connected with one end of R9 and the negative end of OP-1, and the other end of R9 is connected with the positive end of OP-1. R7, OP-1 and C1 are connected in parallel, and OP-1 is output to a high-speed ADC (analog-to-digital converter).
The foregoing description of the embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same elements or features may also be varied in many respects. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.
Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those skilled in the art. Numerous details are set forth, such as examples of specific parts, devices, and methods, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In certain example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are intended to be inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed and illustrated, unless explicitly indicated as an order of performance. It should also be understood that additional or alternative steps may be employed.
Claims (9)
1. A safe headphone amplifier based on high-speed sampling techniques, comprising: the device comprises an input end, a bias power amplifier module and an output end; the method is characterized in that: the system also comprises an information acquisition module, a frequency doubling sampling module, an ultrahigh frequency DSP, a current sampling module, an analog-to-digital conversion module, a first digital signal processor/DSP, a digital-to-analog converter, a low-pass filter, a current-voltage converter and a current control voltage module;
the bias power amplifier module is respectively connected with an input end and an output end, wherein the input end is used for inputting signals, amplifying the signals after passing through the bias amplifier, and then outputting the signals through the output end;
the information acquisition module is used for acquiring the data format of the played audio through the input end, including the sampling rate of the audio; and sending the sampling rate to a frequency doubling sampling module;
the frequency doubling sampling module performs frequency doubling sampling from the output end based on the sampling rate of the audio, and the frequency doubling sampling is multiple k; the frequency multiplication sampling module sends frequency multiplication samples to the ultrahigh frequency DSP; the ultrahigh frequency DSP processes the frequency multiplication sampling to obtain voltage correction data, and the voltage correction data is input into the first DSP; the working frequency of the first DSP is different from the frequency of the ultrahigh frequency DSP;
the current sampling module is connected with the bias power amplifier module and is used for copying proportional current of an output stage of the bias power amplifier module, and then the copied current is converted into a digital signal through the analog-to-digital conversion module and is input into the first DSP;
the signal output by the analog-to-digital converter is input into a power amplifier bias model in a first DSP for calculation, and the first DSP outputs voltage control data by combining voltage correction data;
after the voltage control data are input into the digital-to-analog converter, the voltage control data enter the current-to-voltage converter through the low-pass filter to obtain control current; the control current is input into the current control voltage module to obtain the regulated voltage, and the regulated voltage and the input signal are loaded to the bias amplification module together.
2. A safe headphone amplifier based on high speed sampling techniques according to claim 1, characterized in that:
carrying out model matching on the signal acquired by the DSP and a pre-established power amplifier bias model by taking 5ms as a unit; the sampling rate of the analog-to-digital converter and the digital-to-analog converter is 100kHz.
3. A high speed sampling technology based secure headphone amplifier as in claim 1, wherein:
the sampling rate of the audio acquired by the information acquisition module is the sampling rate of a played audio file or the sampling rate of an audio track of a played video file; the sampling rate is 44.1kHz, 48kHz or 96kHz; the multiple k of frequency multiplication is 2, 4, 8 or 16;
the frequency doubling sampling module collects ultrahigh frequency data and sends the ultrahigh frequency data to the ultrahigh frequency DSP; the ultrahigh frequency DSP performs real-time fast Fourier transform on the input data to obtain a frequency spectrum curve of the ultrahigh frequency data, and calculates the total energy E of the frequency spectrum curve;
the ultrahigh frequency DSP converts the total energy E and the energy threshold E 0 Comparison was made and Vk = a ″ (E-E) was calculated 0 ) (ii) a Wherein A is a coefficient of less than 0, V k Correcting the data for the voltage; because the ultrahigh frequency DSP converts signals in real time, E and V k Are all time-varying quantities.
4. A safe headphone amplifier based on high speed sampling techniques according to claim 3, characterized in that:
the power amplifier bias model comprises two parts, wherein the first part is an overload identification model and is used for detecting whether an overload trend exists and carrying out corresponding control, and the second part is a compensation model and is used for detecting whether the power amplifier is about to exceed a bias linear interval and applying corresponding control;
the working process of the overload identification model is as follows:
performing time domain-frequency domain transformation on the digital signal input into the first DSP at fixed time intervals, wherein the transformation mode is Fourier transformation or wavelet transformation; the frequency domain signal carries out waveform energy calculation in real time, waveform energy is compared with an energy threshold value, and if the waveform energy exceeds the energy threshold value, the first DSP controls the power amplifier final stage to be closed;
wherein the energy threshold is a curve varying with frequency, i.e. the energy threshold G is a function G (f), wherein f represents the frequency of the signal; the waveform energy solved in real time is also a curve changing along with the frequency, the signal energy of different frequencies is different, and the waveform energy H is a function H (f);
calculating Y (f) = H (f) -G (f), and when any value of Y (f) is less than 0, controlling the first DSP to close the power amplifier final stage;
the working process of the compensation model is as follows:
performing time domain-frequency domain transformation on the digital signal input into the first DSP at fixed time intervals, wherein the transformation mode is Fourier transformation or wavelet transformation; the first DSP performs feature extraction on the frequency domain signal, and the extracted features comprise the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max The energy value sum M of the characteristic frequency section; wherein the characteristic frequency segment is a preset frequency range;
the first DSP converts the pattern of the frequency domain signal and the strongest frequency F max 、F max Corresponding peak height P max 、F max Corresponding full width at half maximum W max And inputting the energy value sum M of the characteristic frequency section as a parameter into the neural network model to obtain a voltage V 0 。
5. A safe headphone amplifier based on high-speed sampling techniques according to claim 4, characterized in that:
v0 is a time-varying quantity, V = V being calculated in the first DSP 0 +V k V is voltage control data;
after the voltage control data are input into the digital-to-analog converter, the voltage control data enter the current-to-voltage converter through the low-pass filter to obtain control current; the control current is input into the current control voltage module to obtain a regulated voltage, and the regulated voltage and the input signal are loaded to the bias amplification module together;
when the total energy E of the spectrum curve exceeds E 0 When, V k The bias voltage of the adjusting voltage is reduced, and the distortion of the bias power amplifier module is further reduced; when the total energy E is less than E 0 When, V k The voltage bias is positive, so that the voltage bias is increased, and the working effect of the power amplifier module is ensured.
6. A safe headphone amplifier based on high speed sampling techniques according to claim 1, characterized in that:
the current sampling module comprises a circuit for current-voltage conversion and low-pass filtering at the same time, and converts a current signal into a voltage signal and performs low-pass filtering at the same time; the purpose of the low-pass filtering is to remove out-of-band interference.
7. A high speed sampling technology based secure headphone amplifier as in claim 1, wherein:
the bias power amplifier module comprises two resistors R3 and R4 which are connected in series, an NPN triode Q6 and a PNP triode Q4; the base electrode of the NPN triode Q6 and the base electrode of the PNP triode Q4 are both connected with the driving output; two resistors connected in series are connected between the emitter of the NPN triode Q6 and the emitter of the PNP triode Q4, and an output is formed between the two resistors connected in series;
the collector of the NPN triode Q6 is connected with vcc, and the base of the PNP triode Q4 is connected with vee.
8. A safe headphone amplifier based on high speed sampling techniques according to claim 1, characterized in that:
the first DSP chip used the Texas Instruments TMS320C6713B series.
9. A high speed sampling technology based secure headphone amplifier as in claim 1, wherein:
the maximum clock frequency of the ultrahigh frequency DSP chip is 300MHz.
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| CN116107383A (en) * | 2023-04-12 | 2023-05-12 | 华南理工大学 | Maximum power point tracking circuit applied to piezoelectric energy collection interface |
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