CN219145560U

CN219145560U - Safe earphone amplifier based on high-speed sampling technology

Info

Publication number: CN219145560U
Application number: CN202222628099.2U
Authority: CN
Inventors: 杨澄
Original assignee: Guangzhou Gordon Audio Technology Co ltd
Current assignee: Guangzhou Gordon Audio Technology Co ltd
Priority date: 2022-10-08
Filing date: 2022-10-08
Publication date: 2023-06-06
Anticipated expiration: 2032-10-08

Abstract

The utility model provides a safe earphone amplifier based on a high-speed sampling technology, which is provided with two DSP chips, wherein a first DSP chip works at 100kHz, maintains a certain difference frequency with an audio signal, and an ultra-high frequency DSP chip works by frequency multiplication of the audio signal to correct the output result of the first DSP, so that the noise of equipment can be effectively collected, the control synergy is ensured, and the good processing speed can be ensured when the first DSP chip is controlled.

Description

Safe earphone amplifier based on high-speed sampling technology

Technical Field

The utility model relates to the field of audio amplifiers, in particular to a safe earphone amplifier based on a high-speed sampling technology.

Background

A power amplifier refers to an amplifier that produces maximum power output to drive a load (e.g., a speaker) at a given distortion rate. The power amplifier plays a role of a pivot for organizing and coordinating in the whole sound system, and the power amplifier dominates whether the whole sound system can provide good tone quality output to a certain extent.

For example, application number CN201910096690.8 discloses a digital power amplifier system, which includes a first component branch and a second component branch, where the first component branch includes: a first switch structure and a first current source in series, the first current source comprising: the fourth resistor, the first field effect transistor, the second field effect transistor and the second operational amplifier, the second component branch circuit includes: a second switch structure and a second current source in series, the second current source comprising: when the fifth resistor, the third field effect transistor, the fourth field effect transistor and the third operational amplifier are applied to a digital power amplification system, the equivalent output impedance of the digital-analog converter is increased, and the power supply rejection ratio of the digital power amplification system is reduced. The traditional power amplifier adopts analog bias, has large discreteness and poor bias following property.

The method comprises the steps that a headset amplifier is developed before a company, according to the fact that signals collected by a DSP are subjected to model matching with a pre-established power amplifier stage paranoid model in a unit of 5mS, whether overload trend exists or not is detected, whether the power amplifier is about to exceed a paranoid linear interval or not is detected, whether the power amplifier paranoid is adjusted or not is determined, a strong overload trend (short circuit) exists, and the final stage of the power amplifier is closed timely; for the deviation from the paranoid preceding zone (class A zone), the deviation is subjected to a certain degree of overfitting compensation, so that the power amplifier stage is always in a high-linearity zone, and meanwhile, the fixed paranoid current and the power consumption are reduced; the device is protected.

However, at present, the sampling rate of the audio format is typically 44.1kHz, 48kHz or 96kHz, because the amplifier generally works in an analog signal mode, the noise of the device itself is not the same as the sampling rate of the audio format, and directly adopting the same DSP sampling rate as the audio format can lead to effective collection of the noise generated by the device itself, while adopting other frequencies can lead to reduced control synchronism, and in addition, if the ultra-high frequency DSP is directly adopted for control, the control delay is higher due to larger calculation amount.

Disclosure of Invention

In order to solve the above-mentioned problems, the present utility model provides a safe earphone amplifier based on a high-speed sampling technology, comprising: the input end, the bias power amplifier module and the output end; the system also comprises an information acquisition module, a frequency multiplication sampling module, an ultrahigh frequency DSP, a current sampling module, an analog-to-digital converter, a first digital signal processor/DSP, a digital-to-analog converter, a low-pass filter, a current-voltage converter and a current control voltage module;

the input end is connected with the input end of the bias power amplifier module, the first output end of the bias power amplifier module is connected with the output end, and the other end of the output end is connected with the second input end of the frequency multiplication sampling module;

the second output end of the bias power amplifier module is connected with the input end of the current sampling module, the output end of the current sampling module is connected with the input end of the analog-to-digital converter, the output end of the analog-to-digital converter is connected with the first input end of the first DSP, the output end of the first DSP is connected with the input end of the digital-to-analog converter, the output end of the digital-to-analog converter is connected with the input end of the low-pass filter, the output end of the low-pass filter is connected with the input end of the current-voltage converter, the output end of the current-voltage converter is connected with the input end of the current control voltage module, and the output end of the current control voltage module is connected with the input end of the bias power amplifier module;

the input end is connected with the input end of the information acquisition module, the output end of the information acquisition module is connected with the first input end of the frequency multiplication sampling module, the output end of the frequency multiplication sampling module is connected with the input end of the ultrahigh frequency DSP, and the output end of the ultrahigh frequency DSP is connected with the second input end of the first DSP;

the current sampling module comprises a circuit for converting current into voltage and simultaneously carrying out low-pass filtering.

Carrying out model matching on signals acquired by the DSP and a pre-established power amplifier bias model by taking 5ms as a unit; the sampling rate of the analog-to-digital converter and the digital-to-analog converter is 100kHz.

The sampling rate of the audio acquired by the information acquisition module is the sampling rate of a played audio file or the sampling rate of an audio track of a played video file; the sampling rate is 44.1kHz, 48kHz or 96kHz; the multiple k of the frequency multiplication is 2, 4, 8 or 16;

the frequency multiplication sampling module acquires ultrahigh frequency data and sends the ultrahigh frequency data to the ultrahigh frequency DSP; the ultra-high frequency DSP performs real-time fast Fourier transform on the input data to obtain a spectrum curve of the ultra-high frequency data, and calculates the total energy E of the spectrum curve;

the ultra-high frequency DSP compares the total energy E with an energy threshold E0 and calculates vk=a' (E-E0); wherein A is a coefficient and is smaller than 0, and Vk is voltage correction data; since the uhf DSP converts signals in real time, E, vk is a time-varying quantity.

The power amplifier bias model comprises two parts, wherein the first part is an overload recognition model for detecting whether overload trend exists and performing corresponding control, and the second part is a compensation model for detecting whether the power amplifier is about to exceed a bias linear interval and applying corresponding control;

the voltage control data is input into a digital-to-analog converter and then enters a current-to-voltage converter through a low-pass filter to obtain control current; the control current is input into the current control voltage module to obtain an adjusting voltage, and the adjusting voltage and an input signal are loaded to the bias amplifying module together;

when the total energy E of the spectrum curve exceeds E0, vk is a negative value, so that the bias voltage of the regulating voltage is reduced, and the distortion of the bias power amplifier module is further reduced; when the total energy E is smaller than E0, vk is a positive value, so that the regulating voltage bias is increased, and the working effect of the power amplifier module is ensured.

The current sampling module comprises a circuit for converting current into voltage and simultaneously carrying out low-pass filtering, and converts a current signal into a voltage signal and simultaneously carries out low-pass filtering; the purpose of the low pass filtering is to remove out-of-band interference.

The bias power amplifier module comprises two resistors R3 and R4 which are connected in series, an NPN triode Q6 and a PNP triode Q4; the base electrode of the NPN triode Q6 and the base electrode of the PNP triode Q4 are connected with a driving output; two resistors connected in series are connected between the emitter of the NPN triode Q6 and the emitter of the PNP triode Q4, and output is arranged between the two resistors connected in series;

the collector of NPN transistor Q6 is connected to vcc and the base of PNP transistor Q4 is connected to vee.

The first DSP chip used the TMS320C6713B series of Texas Instruments company.

The maximum clock frequency of the ultra-high frequency DSP chip is 300MHz.

The beneficial effects of the utility model are as follows:

the utility model sets two DSP chips, the first DSP chip works at 100kHz, maintains a certain difference frequency with the audio signal, the ultra-high frequency DSP chip works by frequency multiplication of the audio signal, and corrects the result output by the first DSP, thereby not only ensuring that the noise of the equipment can be effectively collected and the control synergy, but also ensuring that the first DSP chip can have good processing speed when being controlled.

Aiming at the time domain-frequency domain transformation of signals input in the DSP, the utility model compares the waveform energy of the frequency domain with an energy threshold value, and if the waveform energy exceeds the energy threshold value, the DSP controls the closing of the final stage of the power amplifier; the speed and accuracy of data processing are greatly improved, and the circuit is effectively protected while the bias following performance is improved.

Drawings

In order to more clearly illustrate the embodiments of the utility model or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the utility model, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a schematic diagram of the overall architecture of the present utility model;

fig. 2 is a block diagram of a portion of the circuit of the present utility model.

Wherein Q represents a triode, R represents a resistor, OP represents an operational amplifier, and C represents a capacitor; q4, Q6, R3 and R4 form the output stage of the power amplifier; q1, Q2, Q3, Q5, Q7, Q8, R1, R2, R5, R6 and R8 form a proportional current replicator of the power output stage; and at R7 and OP-1, current-voltage conversion is completed, and C1 and R7 form a low-pass filter to remove out-of-band interference.

Detailed Description

Example 1:

referring to fig. 1, the present utility model provides a high-speed sampling technology-based safety headphone amplifier, comprising: the input end, the bias power amplifier module and the output end; the system also comprises an information acquisition module, a frequency multiplication sampling module, an ultrahigh frequency DSP, a current sampling module, an analog-to-digital converter, a first digital signal processor/DSP, a digital-to-analog converter, a low-pass filter, a current-voltage converter and a current control voltage module;

Specifically, the bias power amplifier module is respectively connected with an input end and an output end, the input end is used for inputting signals, the signals are amplified after passing through the bias amplifier, and then the signals are output through the output end;

the information acquisition module is used for acquiring a data format of the played audio through an input end, wherein the data format comprises the sampling rate of the audio; the sampling rate is sent to a frequency multiplication sampling module;

the frequency multiplication sampling module performs frequency multiplication sampling from an output end based on the sampling rate of the audio frequency, and the frequency multiplication sampling is multiplied by k; the frequency multiplication sampling module sends frequency multiplication samples to the ultrahigh frequency DSP; the ultra-high frequency DSP processes the frequency multiplication samples to obtain voltage correction data, and the voltage correction data is input into the first DSP;

the current sampling module is connected with the bias power amplifier module and is used for carrying out proportional current replication on an output stage of the bias power amplifier module, and then the replicated current is converted into a digital signal through the analog-to-digital conversion module and is input into the first DSP;

the signal output by the analog-to-digital converter is input into a power amplifier bias model in a first DSP for calculation, and the first DSP combines the voltage correction data to output voltage control data;

the voltage control data is input into a digital-to-analog converter and then enters a current-to-voltage converter through a low-pass filter to obtain control current; the control current is input into the current control voltage module to obtain the regulating voltage, and the regulating voltage and the input signal are loaded to the bias amplifying module together.

the frequency multiplication sampling module acquires ultrahigh frequency data and sends the ultrahigh frequency data to the ultrahigh frequency DSP; the ultra-high frequency DSP performs real-time fast Fourier transform on the input data to obtain a spectrum curve of the ultra-high frequency data, and calculates the total energy of the spectrum curve;

the ultrahigh frequency DSP compares the total energy E with an energy threshold E0 and calculates correction data; since the ultra-high frequency DSP converts signals in real time, E is a time-varying quantity.

the working process of the overload recognition model is as follows:

the digital signal input into the first DSP is subjected to time domain-frequency domain transformation according to a fixed time interval, and the transformation mode is Fourier transformation or wavelet transformation; the frequency domain signal carries out waveform energy calculation in real time, waveform energy is compared with an energy threshold value, and if the waveform energy exceeds the energy threshold value, the first DSP controls the closing of the final stage of the power amplifier;

when the total energy E of the spectrum curve exceeds E0, the correction data is negative, so that the bias voltage of the regulating voltage is reduced, and the distortion of the bias power amplifier module is further reduced; when the total energy E is smaller than E0, the correction data is positive, so that the voltage bias of the regulating voltage is increased, and the working effect of the power amplifier module is ensured.

Example 2:

referring to fig. 2, a circuit structure diagram of the present utility model is shown:

The first DSP chip used the TMS320C6713B series of Texas Instruments company.

The maximum clock frequency of the ultra-high frequency DSP chip is 300MHz.

Q1, Q2, Q3, Q5, Q7, Q8, R1, R2, R5, R6 and R8 constitute a proportional current replicator of the power output stage.

R7, OP-1 and C1 are connected in parallel to form a circuit for converting current into voltage and simultaneously carrying out low-pass filtering, and converting a current signal into a voltage signal and simultaneously carrying out low-pass filtering; the purpose of the low pass filtering is to remove out-of-band interference.

Q1, Q2, Q3, Q5 are PNP triodes, Q7, Q8 are NPN triodes; one end of R1, R2 and R5 is connected with Vcc, the other end of R1 is connected with a Q1 emitter, the other end of R2 is connected with a Q2 emitter, the other end of R3 is connected with a Q3 emitter and a Q5 base, the Q5 emitter is connected with Vcc, and the Q5 collector is grounded through R6 after being connected with the Q3 base;

the Q1 collector and the base are connected and then connected to the Q7 collector, the Q7 emitter is connected with the Q6 emitter, and the Q7 base is connected with the Q8 base, the Q8 collector and the collector of Q3; the collector of Q2 is connected with one end of R9 and the negative end of OP-1, and the other end of R9 is connected with the positive end of OP-1. R7, OP-1 and C1 are connected in parallel, and OP-1 is output to a high-speed ADC, i.e., an analog-to-digital converter.

The description of the foregoing embodiments has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to the particular embodiment, but, where applicable, may be interchanged and used with the selected embodiment even if not specifically shown or described. The same elements or features may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those skilled in the art. Numerous details are set forth, such as examples of specific parts, devices, and methods, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that the exemplary embodiments may be embodied in many different forms without the use of specific details, and neither should be construed to limit the scope of the disclosure. In certain example embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises" and "comprising" are inclusive and, therefore, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed and illustrated, unless specifically indicated. It should also be appreciated that additional or alternative steps may be employed.

Claims

1. A high-speed sampling technique based safety headphone amplifier comprising: the input end, the bias power amplifier module and the output end; the method is characterized in that: the system also comprises an information acquisition module, a frequency multiplication sampling module, an ultrahigh frequency DSP, a current sampling module, an analog-to-digital converter, a first digital signal processor/DSP, a digital-to-analog converter, a low-pass filter, a current-voltage converter and a current control voltage module;

2. The high-speed sampling technique based safety headphone amplifier of claim 1, wherein:

3. The high-speed sampling technique based safety headphone amplifier of claim 1, wherein:

the maximum clock frequency of the ultra-high frequency DSP chip is 300MHz.