CN115548054A

CN115548054A - Display substrate, preparation method thereof and display device

Info

Publication number: CN115548054A
Application number: CN202110944835.2A
Authority: CN
Inventors: 袁粲; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-06-30
Filing date: 2021-08-17
Publication date: 2022-12-30

Abstract

A display substrate, a preparation method thereof and a display device are provided, wherein the display substrate comprises a plurality of display units, and each display unit comprises a display area and a transparent area; the display area is provided with a first power line and a second power line along a first direction, a first scanning signal line, a second scanning connecting line and a first scanning connecting line along a second direction, the second scanning connecting line and the second scanning signal line are connected to form a first annular structure, the display area is also provided with a third scanning connecting line, and the third scanning connecting line, the first scanning connecting line and the first scanning signal line are connected to form a second annular structure; orthographic projections of the first annular structure, the first power line and the second power line on the substrate do not overlap; orthographic projections of the second annular structure, the first power line and the second power line on the substrate do not overlap. The cross point between the signal wires is optimized to be minimum under the condition of realizing the maintainable function, and then the yield of the product is improved.

Description

Display substrate, preparation method thereof and display device

Technical Field

The embodiment of the disclosure relates to but not limited to the technical field of display, and in particular relates to a display substrate, a preparation method thereof and a display device.

Background

An Organic Light Emitting Diode (OLED) is an active Light Emitting display device, and has the advantages of Light emission, ultra-thin thickness, wide viewing angle, high brightness, high contrast, low power consumption, and high response speed. According to different driving methods, the OLED can be classified into a Passive Matrix (PM) type and an Active Matrix (AM) type, where the AMOLED is a current driving device, and each sub-pixel is controlled by an independent Thin Film Transistor (TFT), and each sub-pixel can continuously and independently drive to emit light.

With the continuous development of display technology, OLED technology is increasingly applied to transparent displays. Transparent display is an important personalized display field of display technology, and refers to image display in a transparent state, so that a viewer can see not only images in a display device but also scenes behind the display device, and Virtual Reality (VR) and Augmented Reality (AR) and 3D display functions can be realized. In a transparent display device using the AMOLED technology, each pixel is generally divided into a display region and a transparent region, the display region is provided with a pixel driving circuit and a light emitting element to realize image display, and the transparent region realizes light transmission.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate, a preparation method thereof and a display device, which can improve the display effect.

The embodiment of the present disclosure provides a display substrate, including a substrate and a plurality of display units disposed on the substrate, where each display unit includes a display area and a transparent area, and the display area includes a plurality of sub-pixels; the display area is provided with a first power line and a second power line along a first direction, the first power line and the second power line extend along a second direction, the display area is provided with a first scanning signal line, a second scanning connecting line and a first scanning connecting line along the second direction, the second scanning connecting line and the second scanning signal line are connected with each other to form a first annular structure, a third scanning connecting line is arranged between the first scanning signal line and the first scanning connecting line in the display area, the third scanning connecting line, the first scanning connecting line and the first scanning signal line are connected with each other to form a second annular structure, and the first direction is crossed with the second direction; the orthographic projection of the first annular structure on the substrate does not overlap with the orthographic projection of the first power supply line and the second power supply line on the substrate; an orthographic projection of the second annular structure on the substrate does not overlap with orthographic projections of the first power line and the second power line on the substrate.

In an exemplary embodiment, an orthographic projection of the first annular structure on the substrate does not overlap an orthographic projection of the second annular structure on the substrate, which encompasses the orthographic projection of the first annular structure on the substrate.

In an exemplary embodiment, in a direction perpendicular to the display substrate, the sub-pixel includes a driving circuit layer disposed on the substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer including a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer; the first conducting layer comprises a compensation signal line and a first polar plate, the semiconductor layer comprises an active layer of a plurality of transistors, the second conducting layer comprises the first scanning signal line, the second scanning signal line, the first scanning connecting line, the second scanning connecting line, a second polar plate and gate electrodes of a plurality of transistors, the third conducting layer comprises the first power line, the second power line, the third scanning connecting line, a data signal line and source electrodes and drain electrodes of a plurality of transistors, and an overlapping region exists between the orthographic projection of the second polar plate on the substrate and the orthographic projection of the first polar plate on the substrate so as to form a first capacitor; the second scanning connecting line and the second scanning signal line are connected into an integral structure; the third scanning connecting line is electrically connected with the first scanning connecting line and the first scanning signal line through via holes respectively.

In an exemplary embodiment, at least one of the sub-pixels includes a first transistor, a second transistor, a third transistor, and a first capacitor including a first plate and a second plate, wherein: a gate electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to a data signal line, a second electrode of the first transistor is electrically connected to a gate electrode of the second transistor, a first electrode of the second transistor is electrically connected to the first power supply line, a second electrode of the second transistor is electrically connected to a first electrode of an organic electroluminescent diode, a gate electrode of the third transistor is electrically connected to the second scan signal line, a first electrode of the third transistor is electrically connected to a compensation signal line, a second electrode of the third transistor is electrically connected to a second electrode of the second transistor, and a second electrode of the organic electroluminescent diode is electrically connected to the second power supply line; the first electrode plate is electrically connected with a second pole of the second transistor, and the second electrode plate is electrically connected with a gate electrode of the second transistor.

In an exemplary embodiment, the plurality of sub-pixels include first sub-pixels, second sub-pixels, third sub-pixels, and fourth sub-pixels, the first sub-pixels and the second sub-pixels are alternately arranged to form a first row, and the third sub-pixels and the fourth sub-pixels are alternately arranged to form a second row in the first direction; in the second direction, the first sub-pixels and the third sub-pixels are alternately arranged to form a first column, and the second sub-pixels and the fourth sub-pixels are alternately arranged to form a second column; the first scanning connecting line and the second scanning connecting line are positioned in the first sub-pixel and the second sub-pixel, and the first scanning signal line and the second scanning signal line are positioned in the third sub-pixel and the fourth sub-pixel.

In an exemplary embodiment, at least one of the sub-pixels includes a first transistor including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, and a third transistor including a third active layer, a third gate electrode, a third source electrode, and a third drain electrode, wherein: a region where the second scanning signal line overlaps with the third active layer in the third sub-pixel and the fourth sub-pixel serves as a third gate electrode in the third sub-pixel and the fourth sub-pixel; the area where the second scanning connecting line is overlapped with the third active layer in the first sub-pixel and the second sub-pixel is used as a third gate electrode in the first sub-pixel and the second sub-pixel; a region where the first scanning signal line overlaps with the first active layer in the third sub-pixel and the fourth sub-pixel serves as a first gate electrode in the third sub-pixel and the fourth sub-pixel; the area where the first scan connection line overlaps the first active layer in the first and second sub-pixels serves as a first gate electrode in the first and second sub-pixels.

In an exemplary embodiment, at least one of the display regions further includes a compensation signal line extending in the second direction; the first gate electrode, the second gate electrode and the third gate electrode in the first sub-pixel and the second sub-pixel are in mirror symmetry relative to a vertical axis, the first gate electrode, the second gate electrode and the third gate electrode in the third sub-pixel and the fourth sub-pixel are in mirror symmetry relative to the vertical axis, and the vertical axis is the compensation signal line.

In an exemplary embodiment, the compensation signal line is provided with a compensation connection line protruding towards a first direction and a direction opposite to the first direction; the compensation connecting line is positioned at the adjacent position of the first sub-pixel and the third sub-pixel and the adjacent position of the second sub-pixel and the fourth sub-pixel; the compensation connection line is electrically connected with a third source electrode of the third transistor through a via hole.

In an exemplary embodiment, the third active layer of the first to fourth sub-pixels is disposed at a position close to the compensation connection line, and there is an overlapping region between an orthographic projection of the third active layer on the substrate and an orthographic projection of the compensation connection line on the substrate.

In an exemplary embodiment, the third active layer in the first sub-pixel and the third active layer in the third sub-pixel are integrally connected to each other, and the third active layer in the second sub-pixel and the third active layer in the fourth sub-pixel are integrally connected to each other.

In an exemplary embodiment, at least one of the sub-pixels further includes a first capacitor including a first electrode plate and a second electrode plate disposed opposite to each other, and the second gate electrode is disposed across the second active layer and connected to the second electrode plate to form an integral structure.

In an exemplary embodiment, the first plate in the first sub-pixel is provided with a first opening at a side close to the third sub-pixel and far away from the second sub-pixel; the first polar plate in the second sub-pixel is also provided with the first opening at one side close to the fourth sub-pixel and far away from the first sub-pixel; a second opening is formed in one side, close to the first sub-pixel and close to the fourth sub-pixel, of the first polar plate in the third sub-pixel; the first polar plate in the fourth sub-pixel is also provided with the second opening at one side close to the second sub-pixel and close to the third sub-pixel; the first active layer in the first sub-pixel and the second sub-pixel is arranged at a position close to the first opening, and the first active layer in the third sub-pixel and the fourth sub-pixel is arranged at a position close to the second opening.

In an exemplary embodiment, at least one of the sub-pixels further includes a second capacitor, the second capacitor includes a second plate and a third plate which are oppositely arranged, an overlapping region exists between an orthographic projection of the third plate on the substrate and an orthographic projection of the second plate on the substrate, and the third plate is electrically connected with the first plate through a via hole.

An embodiment of the present disclosure further provides a display device, including: a display substrate as described above.

The embodiment of the present disclosure further provides a method for manufacturing a display substrate, including: forming a plurality of display units on a substrate, wherein each display unit comprises a display area and a transparent area, the display area is provided with a first power line and a second power line along a first direction, the first power line and the second power line extend along a second direction, the display area is provided with a first scanning signal line, a second scanning connecting line and a first scanning connecting line along the second direction, the second scanning connecting line and the second scanning signal line are connected with each other to form a first annular structure, the display area is provided with a third scanning connecting line between the first scanning signal line and the first scanning connecting line, the third scanning connecting line, the first scanning connecting line and the first scanning signal line are connected with each other to form a second annular structure, and the first direction is crossed with the second direction; the orthographic projection of the first annular structure on the substrate is not overlapped with the orthographic projection of the first power supply line and the second power supply line on the substrate; the orthographic projection of the second annular structure on the substrate is not overlapped with the orthographic projection of the first power line and the second power line on the substrate.

According to the display substrate, the manufacturing method thereof and the display device, the first scanning signal line and the second scanning signal line are respectively subjected to annular winding design with the corresponding scanning connecting lines in the display area, the first power line and the second power line are avoided at the annular winding positions of the first scanning signal line and the second scanning signal line, the problem that the product yield is easily influenced due to the fact that the overlapping area of the power lines and other signal lines is large is solved, cross points between the signal lines can be optimized to be minimum under the function condition of maintenance, the product yield is further improved, and technical support is provided for transparent display products. In addition, the preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost and high in yield.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic plan view of a display substrate;

FIG. 3 is a schematic cross-sectional view of a display substrate;

FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

fig. 5 is a schematic structural diagram of a display panel according to an exemplary embodiment of the disclosure;

FIG. 6 is a schematic diagram showing an equivalent circuit of the pixel driving circuit in the four sub-pixels shown in FIG. 5;

fig. 7 is a schematic view after a first conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 8 is a schematic cross-sectional view of the AA region shown in FIG. 7;

FIG. 9 is a schematic view after patterning a semiconductor layer in accordance with an exemplary embodiment of the present disclosure;

FIG. 10 is a cross-sectional view of the AA area in FIG. 9;

FIG. 11 is a schematic view after patterning a second conductive layer in accordance with an exemplary embodiment of the present disclosure;

FIG. 12 is a cross-sectional view of the AA area in FIG. 11;

fig. 13 is a schematic view after a third insulation layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 14 is a cross-sectional view of the AA area in FIG. 13;

FIG. 15 is a schematic view after patterning a third conductive layer in accordance with an exemplary embodiment of the present disclosure;

FIG. 16 is a cross-sectional view of the AA area in FIG. 15;

FIG. 17 is a schematic view after forming a planarization layer pattern in accordance with an exemplary embodiment of the present disclosure;

FIG. 18 is a cross-sectional view of the AA region of FIG. 17;

fig. 19 is a schematic view after a first transparent conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 20 is a cross-sectional view of the AA area in FIG. 19;

FIG. 21 is a schematic view after an anode pattern is formed in accordance with an exemplary embodiment of the present disclosure;

FIG. 22 is a cross-sectional view of the AA area in FIG. 21;

fig. 23 is a schematic view after a first pixel defining layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 24 is a cross-sectional view of the AA area in FIG. 23;

fig. 25 is a schematic view after forming an organic light emitting layer pattern according to an exemplary embodiment of the present disclosure;

FIG. 26 is a schematic view after forming a cathode pattern in accordance with an exemplary embodiment of the present disclosure;

fig. 27 is a schematic diagram of a short-circuit failure point and a laser repair method of a display substrate according to an exemplary embodiment of the disclosure;

fig. 28 is a schematic diagram illustrating another method for repairing a short-circuit failure point and a laser of a display substrate according to an exemplary embodiment of the disclosure.

Description of reference numerals:

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

The drawing scale in this disclosure may be referenced in the actual process, but is not limited thereto. For example: the width-length ratio of the channel, the thickness and the interval of each film layer and the width and the interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in the present disclosure are only schematic structural views, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in a specific case to those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, that is, a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case where the direction of current flow during circuit operation changes, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other, and "source terminal" and "drain terminal" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical function" is not particularly limited as long as it can transmit and receive an electrical signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In this specification, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like is not strictly defined, and may be an approximate triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like, and some small deformations due to tolerances may exist, and a lead angle, a curved edge, deformation, or the like may exist.

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller connected to a data signal driver and a scan signal driver respectively, the data signal driver connected to a plurality of data signal lines (D1 to Dn) respectively, the scan signal driver connected to a plurality of scan signal lines (S1 to Sm) respectively, and a pixel array. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line and a pixel driving circuit. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may supply a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, \8230; \8230, and Dn using the gray scale values and the control signals received from the timing controller. For example, the data signal driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, \8230 \ 8230;, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number.

Fig. 2 is a schematic plan view of a display substrate. As shown in fig. 2, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, a third sub-pixel P3 emitting light of a third color, and a fourth sub-pixel P4 emitting light of a fourth color, the four sub-pixels may each include a circuit unit and a light emitting device, the circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit, the pixel driving circuit is electrically connected to the scan signal line and the data signal line, respectively, and the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line and output a corresponding current to the light emitting device under the control of the scan signal line. The light emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light emitting device is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting a red light, the second subpixel P2 may be a green subpixel (G) emitting a green light, the third subpixel P3 may be a white subpixel (W) emitting a white light, and the fourth subpixel P4 may be a blue subpixel (B) emitting a blue light.

In an exemplary embodiment, the shape of the sub-pixel may be a rectangular shape, a diamond shape, a pentagonal shape, or a hexagonal shape. In an exemplary embodiment, four sub-pixels may be arranged in a horizontal side-by-side manner to form a RWBG pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a Square (Square), diamond (Diamond) or vertical parallel manner, and the disclosure is not limited thereto.

In an exemplary embodiment, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as pixel rows, a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as pixel columns, and the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array.

Fig. 3 is a schematic cross-sectional structure diagram of a display substrate, which illustrates the structure of four sub-pixels of the display substrate. As shown in fig. 3, each sub-pixel in the display substrate may include a driving circuit layer 102 disposed on a substrate 10, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate, in a plane perpendicular to the display substrate.

In exemplary embodiments, the substrate 10 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light emitting structure layer 103 of each sub-pixel may include a light emitting device formed by a plurality of films, and the plurality of films may include an anode, a pixel defining layer, an organic light emitting layer, and a cathode, wherein the anode is connected to the pixel driving circuit, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, and the organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The encapsulation layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, which are stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, so as to ensure that external water vapor cannot enter the light-emitting structure layer 103.

In an exemplary embodiment, the organic light emitting layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), an light emitting layer (EML), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked. In an exemplary embodiment, the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all the sub-pixels may be a common layer connected together, the light emitting layers of all the sub-pixels may be a common layer connected together, or may be isolated from each other, and the light emitting layers of adjacent sub-pixels may overlap by a small amount. In some possible implementations, the display substrate may include other film layers, and the disclosure is not limited thereto.

In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Fig. 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in fig. 4, the pixel driving circuit has a 3T1C structure, and may include 3 transistors (a first transistor T1, a second transistor T2, and a third transistor T3), 1 storage capacitor C, and 6 signal lines (a data signal line D, a first scan signal line G1, a second scan signal line G2, a compensation signal line S, a first power supply line VDD, and a second power supply line VSS).

In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensating transistor. A first pole of the storage capacitor C is coupled to the control pole of the second transistor T2, a second pole of the storage capacitor C is coupled to the second pole of the second transistor T2, and the storage capacitor C is used for storing the potential of the control pole of the second transistor T2. The control electrode of the first transistor T1 is coupled to the first scan signal line G1, the first electrode of the first transistor T1 is coupled to the data signal line D, the second electrode of the first transistor T1 is coupled to the control electrode of the second transistor T2, and the first transistor T1 is configured to receive a data signal transmitted by the data signal line D under the control of the first scan signal line G1, so that the control electrode of the second transistor T2 receives the data signal. A control electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, a first electrode of the second transistor T2 is coupled to the first power line VDD, a second electrode of the second transistor T2 is coupled to the first electrode of the light emitting device, and the second transistor T2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by the control electrode of the second transistor T2. A control electrode of the third transistor T3 is coupled to the second scan signal line G2, a first electrode of the third transistor T3 is coupled to the compensation signal line S, a second electrode of the third transistor T3 is coupled to a second electrode of the second transistor T2, and the third transistor T3 is used for extracting the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing to compensate the threshold voltage Vth.

In an exemplary embodiment, the light emitting device may be an OLED including a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked, the first electrode of the OLED being coupled to the second electrode of the second transistor T2, the second electrode of the OLED being coupled to the second power line VSS, the OLED for emitting light of a corresponding brightness in response to a current of the second electrode of the second transistor T2.

In an exemplary embodiment, the signal of the first power line VDD is a signal continuously supplying a high level, and the signal of the second power line VSS is a signal of a low level. The first to third transistors T1 to T3 may be P-type transistors or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved.

In an exemplary embodiment, the first to third transistors T1 to T3 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ both a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, and the oxide thin film transistor has the advantages of low leakage current and the like. In an exemplary embodiment, a Low Temperature polysilicon thin film transistor and an Oxide thin film transistor may be integrated on a display substrate to form a Low Temperature Polysilicon Oxide (LTPO) display substrate, and may use advantages of the two, may implement high resolution (Pixel Per inc, PPI for short), may perform Low frequency driving, may reduce power consumption, and may improve display quality. In an exemplary embodiment, the light emitting device may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

In an exemplary embodiment, taking 3 transistors as N-type transistors as an example, the operation process of the pixel driving circuit illustrated in fig. 4 may include:

in the first stage A1, signals of the first scanning signal line G1 and the second scanning signal line G2 are high level signals, the data signal line D outputs a data voltage, the compensation signal line S outputs a compensation voltage, a signal of the first power line VDD is high level, and a signal of the second power line VSS is low level. The signal of the first scanning signal line G1 is a high level signal to turn on the first transistor T1, the data voltage output by the data signal line D is written into the first node N1, the potential of the first node N1 is pulled high to charge the storage capacitor C, and the potential of the first node N1 is V at this time ₁ ＝V _data . The signal of the second scanning signal line G2 is a high level signal, so that the third transistor T3 is turned on, the compensation voltage output by the compensation signal line S is written into the second node N2, and the potential V of the second node N2 at this time ₂ ＝V _s . Since the difference between the potentials of the first node N1 and the second node N2 is greater than the threshold voltage V of the second transistor T2 _th And the second transistor T2 is turned on, and the power voltage output by the first power line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on second transistor T2, so as to drive the OLED to emit light.

In the second stage A2, the signals of the first scanning signal line G1 and the second scanning signal line G2 are low level signals, so that the first transistor T1 and the third transistor T3 are turned off, the voltage in the storage capacitor C still makes the second transistor T2 in a conducting state, the power voltage output by the first power line VDD continuously pulls up the potential of the second node N2, and the OLED continuously emits light. When the potential of the second node N2 is equal to V _data -V _th At this time, the second transistor T2 is turned off and the OLED no longer emits light.

In an exemplary embodiment, in order to drive the OLED to normally emit light, both the OLED and the second transistor T2 are forward biased, and in the first stage, the first power line VDD outputs a power voltage greater than the data voltage output by the data signal line D, the data signal line D outputs a data voltage greater than the compensation voltage output by the compensation signal line S, and the compensation signal line S outputs a compensation voltage greater than the power voltage output by the second power line VSS.

However, in a large-sized transparent display product, the overlapping area of the power line and other signal lines is large, which easily affects the product yield, and the product reliability does not meet the process requirement.

An exemplary embodiment of the present disclosure provides a display substrate including a base and a plurality of display units disposed on the base, at least one of the display units including a display region and a transparent region, and at least one of the display regions including a plurality of sub-pixels.

The display device comprises at least one display area, a first power line and a second power line are arranged in the first direction, the first power line and the second power line extend in the second direction, a first scanning signal line, a second scanning connecting line and a first scanning connecting line are arranged in the second direction in the at least one display area, the second scanning connecting line and the second scanning signal line are connected into a first annular structure, a third scanning connecting line is arranged between the first scanning signal line and the first scanning connecting line in the at least one display area, the third scanning connecting line, the first scanning connecting line and the first scanning signal line are connected into a second annular structure, and the first direction is crossed with the second direction.

The orthographic projection of the first annular structure on the substrate and the orthographic projection of the first power line and the second power line on the substrate do not have an overlapping area; there is no overlapping area between the orthographic projection of the second annular structure on the substrate and the orthographic projection of the first power line and the second power line on the substrate.

The display substrate provided by the embodiment of the disclosure performs annular winding design on the first scanning signal line and the second scanning signal line and the corresponding scanning connecting lines respectively in the display area, and the annular winding positions of the first scanning signal line and the second scanning signal line avoid the first power line and the second power line, thereby avoiding the problem that the product yield is easily influenced because the overlapping area of the power lines and other signal lines is large, optimizing the cross points between the signal lines to the minimum under the functional condition of realizing maintenance, further improving the product yield, and providing technical support for transparent display products.

Fig. 5 is a schematic structural diagram of a display panel according to an exemplary embodiment of the disclosure, which illustrates a structure of four sub-pixels (a pixel unit), and fig. 6 is a schematic equivalent circuit diagram of a pixel driving circuit in the four sub-pixels illustrated in fig. 5. As shown in fig. 5 and 6, at least one pixel unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4, each including a pixel driving circuit and a storage capacitor, which are sequentially arranged in a direction parallel to the display substrate. In the following description, the sub-pixels each refer to a region where a pixel driving circuit is disposed. In an exemplary embodiment, the at least one pixel unit may further include a first scan signal line G1, a second scan signal line G2, a first power line VDD, a second power line VSS, and four data signal lines D (in fig. 6, the four data signal lines D are a first data signal line D1 to a fourth data signal line D4, respectively, the first subpixel P1 is connected to the first data signal line D1, the second subpixel P2 is connected to the second data signal line D2, the third subpixel P3 is connected to the third data signal line D3, and the fourth subpixel P4 is connected to the fourth data signal line D4), a compensation signal line S, and four pixel driving circuits.

In an exemplary embodiment, the first and second scan signal lines G1 and G2 may extend along a first direction D1 and be sequentially disposed along a second direction D2, the first direction D1 crossing the second direction D2. The first power line VDD, the data signal line D, and the compensation signal line S may extend along the second direction D2 and be disposed along the first direction D1 accordingly.

In an exemplary embodiment, four data signal lines D and one compensation signal line S are disposed between the first power line VDD and the second power line VSS, two data signal lines D of the four data signal lines D are located between the compensation signal line S and the first power line VDD, and the other two data signal lines D of the four data signal lines D are located between the compensation signal line S and the second power line VSS. Thus, four sub-pixels are formed between the first power line VDD and the second power line VSS by disposing four data signal lines D and one compensation signal line S, and correspondingly, four sub-pixels are also formed between two compensation signal lines S by disposing one first power line VDD, one second power line VSS and four data signal lines D.

In an exemplary embodiment, one first power line VDD, two data signal lines D, the compensation signal line S, another two data signal lines D, and one second power line VSS may be sequentially disposed along the first direction D1. In the first direction D1, the first and second sub-pixels P1 and P2 are alternately arranged to form a first row, and the third and fourth sub-pixels P3 and P4 are alternately arranged to form a second row; in the second direction D2, the first and third sub-pixels P1 and P3 are alternately arranged to form a first column, and the second and fourth sub-pixels P2 and P4 are alternately arranged to form a second column.

In an exemplary embodiment, among the 4 subpixels of at least one pixel unit, the pixel driving circuit in each subpixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. The first transistor T1 may include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor T2 may include a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, the third transistor T3 may include a third active layer, a third gate electrode, a third source electrode, and a third drain electrode, and the storage capacitor may include a first plate and a second plate.

In an exemplary embodiment, the first plate and the second plate are transparent conductive layers, forming a transparent storage capacitor.

In an exemplary embodiment, the first scan signal line G1 is connected to the gate electrode of the first transistor T1 in each sub-pixel, the second scan signal line G2 is connected to the gate electrode of the third transistor T3 in each sub-pixel, the data signal line D is connected to the first electrode of the first transistor T1 in each sub-pixel, the compensation signal line S is connected to the first electrode of the third transistor T3 in each sub-pixel, the first power supply line VDD is connected to the first electrode of the second transistor T2 in each sub-pixel, the second electrode of the first transistor T1 in each sub-pixel is connected to the gate electrode of the second transistor T2, the second electrode of the second transistor T2 in each sub-pixel is connected to the first electrode of the third transistor T3 and the anode of the light emitting device, the first electrode plate in each sub-pixel is connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3, respectively, and the second electrode plate of the second transistor T1 in each sub-pixel is connected to the second electrode of the first transistor T1 and the gate electrode of the third transistor T2, respectively.

In an exemplary embodiment, the at least one pixel cell may include a plurality of connection lines including at least two lateral power connection lines extending along the first direction D1 and two compensation connection lines extending along the first direction D1 and a direction opposite to the first direction D1, a four-by-four structure forming the first power line and a four-by-four structure forming the compensation signal line.

In an exemplary embodiment, one lateral power connection line is disposed at the first and second sub-pixels P1 and P2, and one end of the lateral power connection line is connected to the first power line VDD through a via hole and the other end is connected to the second transistor T2 in the first and second sub-pixels P1 and P2 through a via hole. Another lateral power connection line is disposed at the third and fourth sub-pixels P3 and P4, and one end of the lateral power connection line is connected to the first power line VDD through a via hole and the other end is connected to the second transistor T2 in the third and fourth sub-pixels P3 and P4 through a via hole. Thus, one first power line VDD can supply power signals to four subpixels.

In an exemplary embodiment, a compensation link line is disposed in the middle of one pixel unit, the compensation link line and the compensation signal line are integrally connected to each other, and the compensation link line is connected to the third transistor T3 in each sub-pixel through a via hole. Thus, one compensation signal line S can supply compensation signals to four sub-pixels.

According to the embodiment of the disclosure, the number of the signal lines is saved, the occupied space is reduced, the structure is simple, the layout space is reasonable, the space utilization rate is improved, and the improvement of the resolution ratio is facilitated.

In an exemplary embodiment, the driving circuit layer of the sub-pixel may include a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer stacked on the base in a direction perpendicular to the display substrate. The first conductive layer at least comprises a first polar plate of the storage capacitor, a compensation signal line and a compensation connecting line, the semiconductor layer at least comprises active layers of three transistors, the second conductive layer at least comprises a first scanning signal line, a second scanning signal line, a transverse power supply connecting line, a second polar plate of the storage capacitor and gate electrodes of the three transistors, and the third conductive layer at least comprises a first power supply line VDD, a second power supply line VSS, a data signal line D and first poles and second poles of the three transistors. At least an overlapping region exists between the orthographic projection of the first polar plate on the substrate and the orthographic projection of the second polar plate on the substrate, and a storage capacitor is formed.

In an exemplary embodiment, the second conductive layer may include first and second scan connection lines in the first and second sub-pixels P1 and P2, first and second scan signal lines in the third and fourth sub-pixels P3 and P4, and a second scan connection line connected to the second scan signal line in an integrated structure;

the third conductive layer may include a third scan connection line electrically connected to the first scan connection line and the first scan signal line through the via hole, respectively.

In an exemplary embodiment, the second conductive layer may include a vertical power connection line and an auxiliary power line, the first power line VDD is electrically connected to the vertical power connection line through a via to form a double-layered first power trace, and the second power line VSS is electrically connected to the auxiliary power line through a via to form a double-layered second power trace.

In an exemplary embodiment, the third conductive layer may include an auxiliary cathode, and the auxiliary cathode and the second power line VSS are connected to each other in an integrated structure.

In an exemplary embodiment, the sub-pixel further includes a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate in a direction perpendicular to the display substrate, the light emitting structure layer including an anode, and the auxiliary connection electrode is disposed on the same layer as the anode.

The following is an exemplary description through a process of manufacturing a display substrate. The "patterning process" referred to in the present disclosure includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist, and the like, for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, development, and the like, for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, the term "a and B are disposed in the same layer" means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the forward projection of B is located within the range of the forward projection of a" or "the forward projection of a includes the forward projection of B" means that the boundary of the forward projection of B falls within the boundary range of the forward projection of a, or the boundary of the forward projection of a overlaps with the boundary of the forward projection of B.

Fig. 7 to fig. 26 are schematic diagrams of a manufacturing process of a display substrate according to the present disclosure, which illustrate a layout structure of one display unit of a top emission OLED display substrate, each display unit includes a display area 100 and a transparent area 200, the display area 100 includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4, and a pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. In an exemplary embodiment, the process of preparing the display substrate may include the operations of:

(1) Forming a first conductive layer pattern, including: depositingbase:Sub>A first metal film onbase:Sub>A substrate, patterning the first metal film throughbase:Sub>A patterning process, and formingbase:Sub>A first conductive layer pattern on the substrate 10, where the first conductive layer pattern includesbase:Sub>A first plate 41 andbase:Sub>A compensation signal line S, each sub-pixel forms one first plate 41, and the compensation signal line S isbase:Sub>A stripe structure disposed between 4 sub-pixels, as shown in fig. 7 and 8, and fig. 8 isbase:Sub>A cross-sectional view alongbase:Sub>A-base:Sub>A direction in fig. 7.

In an exemplary embodiment, the first plate 41 serves as both a plate of the first capacitor and a shielding layer, and is configured to form the first capacitor with a second plate formed later, so as to shield the transistor, reduce the intensity of light irradiated onto the transistor, and reduce the leakage current, thereby reducing the influence of light on the characteristics of the transistor.

In an exemplary embodiment, the compensation signal line S extends in the second direction D2, a compensation connection line S-1 protruding in the first direction D1 and in a direction opposite to the first direction D1 is disposed on the compensation signal line S, and the compensation connection line S-1 is connected to a first pole of a subsequently formed third transistor for supplying a compensation signal to the third transistor in each sub-pixel.

In an exemplary embodiment, the first plate 41 is rectangular in shape, the first plate 41 in the first sub-pixel P1 and the first plate 41 in the second sub-pixel P2 are respectively provided with a first opening 45 at a position close to the middle of the pixel unit and far from the compensation signal line S, and the first plate 41 in the third sub-pixel P3 and the first plate 41 in the fourth sub-pixel P4 are respectively provided with a second opening 46 at a position close to the middle of the pixel unit and close to the compensation signal line S.

In an exemplary embodiment, the first conductive layer pattern in the first sub-pixel P1 and the first conductive layer pattern in the second sub-pixel P2 are mirror-symmetrical with respect to a vertical axis (the vertical axis may be the compensation signal line S), and the first conductive layer pattern in the third sub-pixel P3 and the first conductive layer pattern in the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis.

After the composition process, the first conductive layer pattern is formed in the display region 100, and the transparent region 200 has no corresponding film layer.

(2) Forming a semiconductor layer pattern including: on the substrate formed with the aforementioned pattern,base:Sub>A first insulating film andbase:Sub>A semiconductor film are sequentially deposited, and the semiconductor film is patterned bybase:Sub>A patterning process to formbase:Sub>A first insulating layer 61 covering the first conductive layer pattern, andbase:Sub>A semiconductor layer pattern formed on the first insulating layer 61, the semiconductor layer including the first active layer 11, the second active layer 21, and the third active layer 31 pattern provided in each sub-pixel, as shown in fig. 9 and 10, fig. 10 isbase:Sub>A sectional view taken alongbase:Sub>A-base:Sub>A direction of fig. 9. The first active layer 11 serves as an active layer of the first transistor, the second active layer 21 serves as an active layer of the second transistor, and the third active layer 31 serves as an active layer of the third transistor.

In an exemplary embodiment, in four sub-pixels, there is an overlapping region between an orthographic projection of the second active layer 21 on the substrate 10 and an orthographic projection of the first electrode plate 41 on the substrate 10, so that the first electrode plate 41 serving as a shielding layer can shield a channel region of the second transistor, thereby preventing light from affecting the channel and preventing the channel from affecting a display effect due to generation of photoleakage.

In an exemplary embodiment, the first active layer 11 in the first and second sub-pixels P1 and P2 is disposed adjacent to the first opening 45, and the first active layer 11 in the third and fourth sub-pixels P3 and P4 is disposed adjacent to the second opening 46.

In an exemplary embodiment, in the four sub-pixels P1 to P4, the third active layers 31 are all disposed near the compensation connecting line S-1, and there is an overlapping region between an orthographic projection of the third active layer 31 on the substrate 10 and an orthographic projection of the compensation connecting line S-1 on the substrate 10. In an exemplary embodiment, the third active layer 31 in the first sub-pixel P1 and the third active layer 31 in the third sub-pixel P3 are integrally connected to each other, and the third active layer 31 in the second sub-pixel P2 and the third active layer 31 in the fourth sub-pixel P4 are integrally connected to each other.

In an exemplary embodiment, the semiconductor layer pattern in the first sub-pixel P1 and the semiconductor layer pattern in the second sub-pixel P2 are mirror-symmetric with respect to a vertical axis, and the semiconductor layer pattern in the third sub-pixel P3 and the semiconductor layer pattern in the fourth sub-pixel P4 are mirror-symmetric with respect to a vertical axis.

In example embodiments, the semiconductor layer may employ a metal oxide such as an oxide containing indium and tin, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, an oxide containing indium and gallium and zinc, or the like. The semiconductor layer may be a single layer, or may be a double layer, or may be a multilayer.

After the patterning process, a semiconductor layer pattern is formed in the display region 100, and the transparent region 200 includes the substrate 10 and the first insulating layer 61 disposed on the substrate 10.

(3) Forming a second conductive layer pattern including: on the substrate formed with the aforementioned patterns,base:Sub>A second insulating film andbase:Sub>A second metal film are sequentially deposited, and the second insulating film and the second metal film are patterned bybase:Sub>A patterning process to formbase:Sub>A second insulating layer 62 pattern andbase:Sub>A second conductive layer pattern disposed on the second insulating layer 62, the second conductive layer pattern includingbase:Sub>A first scan signal line G1,base:Sub>A second scan signal line G2,base:Sub>A first scan connection line G1-1,base:Sub>A second scan connection line G2-1,base:Sub>A vertical power connection line 51,base:Sub>A horizontal power connection line 52, and an auxiliary power line 53 formed in each display cell, andbase:Sub>A second plate 42,base:Sub>A first gate electrode 12,base:Sub>A second gate electrode 22, andbase:Sub>A third gate electrode 32 formed in each sub-pixel, as shown in fig. 11 and 12, fig. 12 isbase:Sub>A sectional view taken alongbase:Sub>A-base:Sub>A direction in fig. 11.

In an exemplary embodiment, there is an overlap region between the orthographic projection of the second plate 42 on the substrate 10 and the orthographic projection of the first plate 41 on the substrate 10, and the first plate 41 and the second plate 42 form a first capacitance.

In the exemplary embodiment, the second plate 42 has an elongated rectangular shape, and the second plates 42 of the first and second sub-pixels P1 and P2 are respectively provided with a third opening 47 at a position near the middle of the pixel unit, and the second plates 42 of the third and fourth sub-pixels P3 and P4 are respectively provided with a fourth opening 48 at a position near the middle of the pixel unit.

In an exemplary embodiment, the first and second scan signal lines G1 and G2 each extend along the first direction D1, the second scan connection line G2-1 has an inverted "U" shape, the second scan connection line G2-1 and the second scan signal line G2 are integrally connected to each other, the first scan connection line G1-1 has a "one" shape, the first and second scan connection lines G1-1 and G2-1 are located in the first and second sub-pixels P1 and P2, and the first and second scan signal lines G1 and G2 are located in the third and fourth sub-pixels P3 and P4.

In an exemplary embodiment, there is an overlapping region where the orthographic projection of the second scan signal line G2 on the substrate overlaps the orthographic projection of the third active layer 31 in the third and fourth sub-pixels P3 and P4 on the substrate, and a region where the second scan signal line G2 overlaps the third active layer 31 in the third and fourth sub-pixels P3 and P4 serves as the gate electrode 32 of the third transistor T3 in the third and fourth sub-pixels P3 and P4. An overlapping region exists between the orthographic projection of the second scan connecting line G2-1 on the substrate and the orthographic projection of the third active layer 31 in the first sub-pixel P1 and the second sub-pixel P2 on the substrate, and a region where the second scan connecting line G2-1 overlaps the third active layer 31 in the first sub-pixel P1 and the second sub-pixel P2 serves as the gate electrode 32 of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2.

In the exemplary embodiment, the first scanning signal line G1 includes a "U" shaped bent portion, an overlapping region exists between an orthographic projection of the first scanning signal line G1 on the substrate and an orthographic projection of the first active layer 11 in the third sub-pixel P3 and the fourth sub-pixel P4 on the substrate, a region where the first scanning signal line G1 overlaps the first active layer 11 in the third sub-pixel P3 and the fourth sub-pixel P4 serves as the gate electrode 12 of the first transistor T1 in the third sub-pixel P3 and the fourth sub-pixel P4, an overlapping region exists between an orthographic projection of the first scanning connection line G1-1 on the substrate and an orthographic projection of the first active layer 11 in the first sub-pixel P1 and the second sub-pixel P2 on the substrate, and a region where the first scanning connection line G1 overlaps the first active layer 11 in the first sub-pixel P1 and the second sub-pixel P2 serves as the gate electrode 12 of the first transistor T1 in the first sub-pixel P1 and the second sub-pixel P2.

In an exemplary embodiment, the second gate electrode 22 straddles the second active layer 21 and is interconnected with the second plate 42 in an integrated structure.

In an exemplary embodiment, each display unit includes two longitudinal power connection lines 51 therein, and the two longitudinal power connection lines 51 are formed in the first and third sub-pixels P1 and P3 in a stripe structure extending along the second direction D2. In the first subpixel P1, the longitudinal power connection line 51 is positioned at one side of the second plate 42 in the opposite direction of the first direction D1. In the third subpixel P3, the longitudinal power connection line 51 is positioned at one side of the second plate 42 in the opposite direction of the first direction D1. The longitudinal power connection line 51 is configured to be connected with a first power line VDD formed subsequently, so as to form a double-layer wiring, ensure the reliability of power signal transmission, and reduce the resistance of the first power line.

In the exemplary embodiment, two lateral power connection lines 52 are included in each display unit, wherein one lateral power connection line 52 is located at an upper side of the pixel unit (i.e., at a side of the first and second sub-pixels P1 and P2 away from the third and fourth sub-pixels P3 and P4), and the other lateral power connection line 52 is located at a lower side of the pixel unit (i.e., at a side of the third and fourth sub-pixels P3 and P4 away from the first and second sub-pixels P1 and P2). Each of the lateral power connection lines 52 may be provided with a via hole, an orthographic projection of the via hole on the substrate and an orthographic projection of the compensation signal line and a subsequently formed data signal line on the substrate have an overlapping region, and the via hole is configured to reduce parasitic capacitance between the lateral power connection line 52 and the data signal line and the compensation signal line.

In an exemplary embodiment, the lateral power connection line 52 positioned at an upper side of the pixel unit may be interconnected with the longitudinal power connection line 51 positioned in the first sub-pixel P1 in an integrated structure, and the lateral power connection line 52 positioned at a lower side of the pixel unit may be interconnected with the longitudinal power connection line 51 positioned in the third sub-pixel P3 in an integrated structure.

In an exemplary embodiment, two auxiliary power lines 53 are included in each display unit, and the two auxiliary power lines 53 are formed in the second and fourth sub-pixels P2 and P4 in a stripe structure extending along the second direction D2. In the second subpixel P2, the auxiliary power line 53 is positioned at one side of the second plate 42 along the first direction D1. In the fourth subpixel P4, the auxiliary power line 53 is positioned at one side of the second plate 42 along the first direction D1. The auxiliary power line 53 is configured to be electrically connected to a second power line formed later, so as to form a double-layered wiring, ensure reliability of power signal transmission, and reduce resistance of the second power line.

In an exemplary embodiment, the second insulation layer 62 pattern may be the same as the second conductive layer pattern, i.e., the second insulation layer 62 is positioned under the second conductive layer (i.e., the side of the second conductive layer close to the substrate), and there is no second insulation layer 62 in the region other than the second conductive layer.

In an exemplary embodiment, the first, second, and

third gate electrodes

12, 22, and 32 in the first and second sub-pixels P1 and P2 are mirror-symmetrical with respect to a vertical axis, and the third and fourth sub-pixels P3 and P4 are mirror-symmetrical with respect to a vertical axis.

In an exemplary embodiment, the process further includes a conductimerization process. In the conductive treatment, after the second conductive layer pattern is formed, plasma treatment is performed using the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 as a shield, and a semiconductor layer in a region shielded by the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 (i.e., a region where the semiconductor layer overlaps with the first gate electrode 12, the second gate electrode 22, and the third gate electrode) is used as a channel region of the transistor, and a semiconductor layer in a region not shielded by the second conductive layer is treated as a conductive layer, thereby forming a conductive source-drain region.

After the patterning process, the second conductive layer pattern is formed in the display region 100, and the transparent region 200 includes the substrate 10, the first insulating layer 61 and the second insulating layer 62 stacked on the substrate 10, and the first scanning signal line G1 and the second scanning signal line G2 disposed on the second insulating layer 62.

(4) A third insulating layer pattern is formed. Forming the third insulation layer pattern includes: depositing a third insulating film on the substrate formed with the patterns, forming the patterns of the third insulating film by a composition process to form a third insulating layer 63 pattern covering the structure, wherein the third insulating layer 63 is provided with a plurality of via hole patterns, and the via hole patterns comprise: base:Sub>A first via hole V1 andbase:Sub>A second via hole V2 located at two sides of the first gate electrode 12,base:Sub>A third via hole V3 andbase:Sub>A fourth via hole V4 located at two sides of the second gate electrode 22,base:Sub>A fifth via hole V5 andbase:Sub>A sixth via hole V6 located at two sides of the third gate electrode 32,base:Sub>A plurality of seventh via holes V7 located at positions of the auxiliary power lines 53, an eighth via hole V8 located atbase:Sub>A position of the compensation connecting line S-1,base:Sub>A ninth via hole V9 located at an overlapping region of the first drain electrode 14 and the second plate 42 formed subsequently,base:Sub>A tenth via hole V10 located on the first plate 41 and overlapping with an opening region on the second plate 42,base:Sub>A plurality of eleventh via holes V11 located atbase:Sub>A position of the longitudinal power connecting line 51,base:Sub>A thirteenth via hole V13 located atbase:Sub>A position of the transverse power connecting line 52,base:Sub>A fourteenth via hole V14 located atbase:Sub>A position of the first scanning connecting line G1-1, andbase:Sub>A fifteenth via hole V15 located atbase:Sub>A position of the first scanning signal line G1, as shown in fig. 13 and 14, fig. 14 isbase:Sub>A cross-sectional view of fig. 13base:Sub>A-base:Sub>A.

The third insulating layer 63 in the first and second vias V1 and V2 is etched away to expose surfaces of both ends of the first active layer 11. The third insulating layer 63 in the third and fourth vias V3 and V4 is etched away to expose surfaces of both ends of the second active layer 21. The third insulating layer 63 in the fifth via hole V5 and the sixth via hole V6 is etched away to expose surfaces of both ends of the third active layer 31. The seventh via hole V7 is located at the position of the auxiliary power line 53, a plurality of seventh via holes V7 are disposed at intervals, and the third insulating layer 63 in the seventh via hole V7 is etched away to expose the surface of the auxiliary power line 53. The eighth via hole V8 is located at a position where the subsequently formed third source electrode 33 overlaps the compensation connecting line S-1, and the first insulating layer 61 and the third insulating layer 63 in the eighth via hole V8 are etched away to expose the surface of the compensation connecting line S-1. The ninth via hole V9 is formed on the second plate 42, and the third insulating layer 63 in the ninth via hole V9 is etched away to expose the surface of the second plate 42. The tenth via hole V10 in the first subpixel P1 and the second subpixel P2 is located at the third opening 47 of the second plate 42, the tenth via hole V10 in the third subpixel P3 and the fourth subpixel P4 is located at the fourth opening 48 of the second plate 42, and the first insulating layer 61 and the third insulating layer 63 in the tenth via hole V10 are etched away to expose the surface of the first plate 41. The eleventh via holes V11 are located at the positions of the longitudinal power connection line 51, the eleventh via holes V11 are disposed at intervals, and the third insulating layer 63 in the eleventh via holes V11 is etched away to expose the surface of the longitudinal power connection line 51. The thirteenth via hole V13 is located at a position where the lateral power connection line 52 overlaps with the second source electrode 23 to be formed later, and the third insulating layer 63 in the thirteenth via hole V13 is etched away to expose the surface of the lateral power connection line 52. The fourteenth via hole V14 is located at a position where the first scan connecting line G1-1 overlaps with a subsequently formed third scan connecting line 54, and the third insulating layer 63 in the fourteenth via hole V14 is etched away to expose the surface of the first scan connecting line G1-1. The fifteenth via hole V15 is located at a position where the first scanning signal line G1 overlaps with the subsequently formed third scanning connection line 54, and the third insulating layer 63 in the fifteenth via hole V15 is etched away to expose the surface of the first scanning signal line G1.

After the patterning process, a plurality of via patterns are formed in the display region 100, and the transparent region 200 includes a first insulating layer 61 and a second insulating layer 62 stacked on the substrate 10, a first scanning signal line G1 and a second scanning signal line G2 disposed on the second insulating layer 62, and a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2.

(5) Forming a third conductive layer pattern including: on the substrate formed with the aforementioned pattern, a third metal film is deposited, and the third metal film is patterned by a patterning process, thereby forming a third conductive layer pattern on the third insulating layer 63. The third conductive layer includes: one first power line VDD, one second power line VSS, four data signal lines D and two third scan connection lines 54 formed in each display cell, and the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34 and the third plate 43 pattern formed in each sub-pixel, as shown in fig. 15 and 16, fig. 16 isbase:Sub>A cross-sectional view taken alongbase:Sub>A-base:Sub>A direction in fig. 15.

In an exemplary embodiment, the first power line VDD, the second power line VSS, the compensation signal line S and the data signal line D are disposed in parallel, each extending along the second direction D2, the second power line VSS is disposed in the second subpixel P2 and the fourth subpixel P4, the first power line VDD is disposed in the first subpixel P1 and the third subpixel P3, the compensation signal line S is disposed between the first power line VDD and the second power line VSS, two data signal lines D are disposed between the second power line VSS and the compensation signal line S, and the other two data signal lines D are disposed between the first power line VDD and the compensation signal line S.

In an exemplary embodiment, the first power line VDD is connected to the vertical power connection line 51 and the horizontal power connection line 52 through a plurality of eleventh vias V11, the horizontal power connection line 52 is connected to the second source electrode 23 of each sub-pixel through a thirteenth via V13, the second source electrode 23 is connected to one end of the second active layer 21 through a third via V3, so that the connection between the second source electrode 23 and the first power line VDD is achieved, the first power line VDD and the vertical power connection line 51 form a double-layered routing, the reliability of power signal transmission is ensured, and the resistance of the first power line VDD is reduced.

In an exemplary embodiment, the second power line VSS is connected to the auxiliary power line 53 through a plurality of seventh vias V7, and the second power line VSS and the auxiliary power line 53 form a double-layered trace, which ensures reliability of power signal transmission and reduces resistance of the second power line VSS. In some possible implementations, the widths of the first power line VDD and the second power line VSS in the first direction D1 are both greater than the width of the compensation signal line S in the first direction D1, and the widths of the first power line VDD and the second power line VSS in the first direction D1 are both greater than the width of the data signal line D in the first direction D1, so that the resistances of the first power line VDD and the second power line VSS can be further reduced.

In an exemplary embodiment, the compensation connection line S-1 is connected to the third source electrode 33 of each sub-pixel through the eighth via hole V8. Because the compensation connecting line S-1 is arranged in the middle of the upper and lower sub-pixels of the display area 100, the compensation signal line S is arranged in the middle of the left and right sub-pixels of the display area 100, the compensation connecting line S-1 and the compensation signal line S are of an integrated structure which is mutually connected, and the third transistors of the left and right sub-pixels are symmetrically arranged relative to the compensation signal line S, the symmetrical design ensures that each display unit only needs to adopt one compensation signal line S, the RC delay of the compensation signal before being written into the transistor is basically the same, and the display uniformity is ensured.

In an exemplary embodiment, the third scan connecting line 54 is a straight line or a folded line structure extending along the second direction D2, the third scan connecting line 54 is connected to the first scan connecting line G1-1 through a fourteenth via V14, and the third scan connecting line 54 is connected to the first scan signal line G1 through a fifteenth via V15.

In an exemplary embodiment, the data signal line D of the first subpixel P1 is disposed at a side of the first subpixel P1 near the first power line VDD, the data signal line D of the second subpixel P2 is disposed at a side of the second subpixel P2 near the second power line VSS, the data signal line D of the third subpixel P3 is disposed at a side of the third subpixel P3 near the compensation signal line S, and the data signal line D of the fourth subpixel P4 is disposed at a side of the fourth subpixel P4 near the compensation signal line S.

In an exemplary embodiment, the first source electrode 13 is an integral structure connected with the data signal lines D, such that each data signal line D is respectively connected with the first source electrode 13 of the sub-pixel, the first source electrode 13 is connected with one end of the first active layer 11 through the first via V1, the first drain electrode 14 is connected with the other end of the first active layer 11 through the second via V2, and the first drain electrode 14 is also connected with the second gate electrode 22 and the second plate 42 through the ninth via V9, which realizes that the first drain electrode 14, the second gate electrode 22 and the second plate 42 have the same potential. The second source electrode 23 is connected to one end of the second active layer 21 through the third via hole V3, and is connected to the lateral power connection line 52 through the thirteenth via hole V13, and the lateral power connection line 52 is connected to the first power line VDD through the eleventh via hole V11, so that the second source electrode 23 is connected to the first power line VDD, and the second drain electrode 24 is connected to the other end of the second active layer 21 through the fourth via hole V4. The third source electrode 33 is connected to one end of the third active layer 31 through a fifth via hole V5, and is connected to the compensation connection line S-1 through an eighth via hole V8, the compensation connection line S-1 and the compensation signal line S are connected to each other to form an integrated structure, so that the third source electrode 33 is connected to the compensation signal line S, and the third drain electrode 34 is connected to the other end of the third active layer 31 through a sixth via hole V6. The second drain electrode 24, the third drain electrode 34 and the third polar plate 43 are connected to each other to form an integral structure, and the third polar plate 43 is connected to the first polar plate 41 through the tenth via hole V10, so that the second drain electrode 24 is simultaneously connected to the first polar plate 41 and the third polar plate 43, and the third drain electrode 34 is simultaneously connected to the first polar plate 41 and the third polar plate 43, thereby realizing that the second drain electrode 24, the third drain electrode 34, the first polar plate 41 and the third polar plate 43 have the same potential. An overlapping region exists between the orthographic projection of the third plate 43 on the substrate 10 and the orthographic projection of the second plate 42 on the substrate 10, and the third plate 43 and the second plate 42 form a second capacitor.

In an exemplary embodiment, the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34, and the third plate 43 in the first subpixel P1 and the second subpixel P2 are mirror-symmetric with respect to a vertical axis, and the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34, and the third plate 43 in the third subpixel P3 and the fourth subpixel P4 are mirror-symmetric with respect to a vertical axis.

After the patterning process, the third conductive layer pattern is formed in the display region 100, and the transparent region 200 includes a first insulating layer 61 and a second insulating layer 62 stacked on the substrate 10, a first scanning signal line G1 and a second scanning signal line G2 disposed on the second insulating layer 62, and a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2.

(6) Forming a fourth insulation layer and a planarization layer pattern, including: on the substrate formed with the above-mentioned pattern, deposit the fourth insulating film first, then coat the flat film, through the mask of the flat film, expose and develop, etch the fourth insulating film and form the fourth insulating layer 64 pattern covering the aforesaid structure, and set up the flat (PLN) layer 65 pattern on the fourth insulating layer 64, offer multiple via hole pattern on fourth insulating layer 64 and flat layer 65, multiple via hole pattern includes at least: fig. 17 and 18 showbase:Sub>A sixteenth via V16 located at the position of the third plate 43 in each sub-pixel of the display area 100 andbase:Sub>A seventeenth via V17 located on the second power line VSS, where fig. 18 isbase:Sub>A cross-sectional view taken along the directionbase:Sub>A-base:Sub>A in fig. 17.

In an exemplary embodiment, the sixteenth via V16 is positioned at the middle of the third plate 43, the fourth insulating layer 64 and the planarization layer 65 in the sixteenth via V16 are etched away to expose a surface of the third plate 43, and the fourth insulating layer 64 and the planarization layer 65 in the seventeenth via V17 are etched away to expose a surface of the second power line VSS.

After the patterning process, the transparent region 200 includes a first insulating layer 61 and a second insulating layer 62 stacked on the substrate 10, a first scanning signal line G1 and a second scanning signal line G2 disposed on the second insulating layer 62, a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2, and a fourth insulating layer 64 and a planarization layer 65 disposed on the third insulating layer 63.

(7) Forming a first transparent conductive layer pattern including: on the substrate formed with the aforementioned pattern,base:Sub>A first transparent conductive film is deposited, and patterned bybase:Sub>A patterning process, andbase:Sub>A first transparent conductive layer pattern is formed on the planarization layer 65, the first transparent conductive layer includingbase:Sub>A first anode 70 andbase:Sub>A first connection electrode 81, the first anode 70 being formed in each sub-pixel of the display area 100, the first anode 70 in each sub-pixel being connected to the drain electrode of the second transistor T2 throughbase:Sub>A sixteenth via V16 in the corresponding sub-pixel, the first connection electrode 81 being formed atbase:Sub>A position wherebase:Sub>A seventeenth via V17 is located on the second power line VSS in the display area 100, and the first connection electrode 81 being connected to the second power line VSS through the seventeenth via V17, as shown in fig. 19 and 20, and fig. 20 beingbase:Sub>A cross-sectional view of fig. 19 taken alongbase:Sub>A-base:Sub>A direction. Since the drain electrode of the second transistor T2, the drain electrode of the third transistor T3, and the third plate 43 in each sub-pixel are integrally connected to each other, the connection of the first anode 70 to the drain electrode of the second transistor T2 in each sub-pixel is achieved. In an exemplary embodiment, four first anodes 70 may form a red light emitting unit, a green light emitting unit, a blue light emitting unit, and a white light emitting unit.

In an exemplary embodiment, the first anode 70 may include two sub-anode blocks separately disposed and a connection structure connected to the two sub-anode blocks, respectively, and the two sub-anode blocks are connected to each other by the connection structure. As shown in fig. 19, the connection structure may include: the first connecting electrode 701 is in a U-shaped structure, and two ends of the first connecting electrode are respectively connected with one of the two sub-anode blocks; the second connection electrode 702 has one end connected to the driving transistor and the other end connected to the first connection electrode 701, so that the two sub-anode blocks are connected to each other through the connection structure.

If a dark spot or a bright spot occurs in any one of the sub-pixels of the display panel, a portion of the first connection electrode 701 in the connection structure may be laser cut, whereby one of the two sub-anode blocks from one sub-pixel may be electrically connected to the driving transistor and the other sub-anode block floats, whereby the sub-pixel may be normally driven.

In an exemplary embodiment, the four first anodes 70 are arranged in a Square (Square), the upper left first anode 70 is connected to the third plate 43 of the first subpixel P1 through the sixteenth via V16 of the first subpixel P1, the upper right first anode 70 is connected to the third plate 43 of the second subpixel P2 through the sixteenth via V16 of the second subpixel P2, the lower left first anode 70 is connected to the third plate 43 of the third subpixel P3 through the sixteenth via V16 of the third subpixel P3, and the lower right first anode 70 is connected to the third plate 43 of the fourth subpixel P4 through the sixteenth via V16 of the fourth subpixel P4. In some possible implementations, the arrangement of the first anodes 70 in the display area 100 may be adjusted according to actual needs, and the disclosure is not limited in this respect.

After the patterning process, the transparent region 200 includes a first insulating layer 61 and a second insulating layer 62 stacked on the substrate 10, a first scanning signal line G1 and a second scanning signal line G2 disposed on the second insulating layer 62, a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2, a fourth insulating layer 64 disposed on the third insulating layer 63, and a planarization layer 65.

(8) An anode pattern is formed. In an exemplary embodiment, the forming of the anode pattern may include: depositing a fourth metal film and a second transparent conductive film on the substrate formed with the patterns in sequence, patterning the fourth metal film and the second transparent conductive film through a patterning process to form a pattern of a second anode 71, a third anode 72, a second connection electrode 82 and a third connection electrode 83, wherein the second anode 71 is disposed on a side of the first anode 70 away from the substrate and connected with the first anode 70, the third anode 72 is disposed on a side of the second anode 71 away from the substrate and connected with the second anode 71, the second connection electrode 82 is disposed on a side of the first connection electrode 81 away from the substrate and connected with the first connection electrode 81, and the third connection electrode 83 is disposed on a side of the second connection electrode 82 away from the substrate and connected with the second connection electrode 82. The stacked first anode 70, second anode 71, and third anode 72 constitute an anode 74, and the stacked first connecting electrode 81, second connecting electrode 82, and third connecting electrode 83 constitute an auxiliary connecting electrode, as shown in fig. 21 and 22, and fig. 22 isbase:Sub>A cross-sectional view taken along the directionbase:Sub>A-base:Sub>A in fig. 21.

In an exemplary embodiment, the second anode 71 and the third anode 72 have a shape similar to that of the first anode 70 in a plane parallel to the display substrate, and an orthogonal projection of the second anode 71 on the base may be located within a range of an orthogonal projection of the first anode 70 on the base, and an orthogonal projection of the second anode 71 on the base may be located within a range of an orthogonal projection of the third anode 72 on the base. The second connection electrode 82 and the third connection electrode 83 have shapes similar to those of the first connection electrode 81 in a plane parallel to the display substrate, and an orthogonal projection of the second connection electrode 82 on the base may be located within a range of an orthogonal projection of the first connection electrode 81 on the base, and an orthogonal projection of the second connection electrode 82 on the base may be located within a range of an orthogonal projection of the third connection electrode 83 on the base.

In the exemplary embodiment, the first connection electrode 81 located at a side (lower side) of the second connection electrode 82 adjacent to the substrate has an edge protruding the outline of the second connection electrode 82 in a plane perpendicular to the display substrate to form an "eave" structure, the third connection electrode 83 located at a side (upper side) of the second connection electrode 82 away from the substrate has an edge protruding the outline of the second connection electrode 82, and the first connection electrode 81 and the third connection electrode 83 form an "eave" structure, so that the first connection electrode 81, the second connection electrode 82 and the third connection electrode 83 are stacked to form an "i" shape.

In the exemplary embodiment, the first anode 70 located on the side (lower side) of the second anode 71 adjacent to the substrate has an edge protruding beyond the outline of the second anode 71 to form a "roof-base" structure, and the third anode 72 located on the side (upper side) of the second anode 71 away from the substrate has an edge protruding beyond the outline of the second anode 71 to form an "eave" structure, such that the stacked first anode 70, second anode 71 and third anode 72 form an "i" shape.

In an exemplary embodiment, during the patterning of the fourth metal film and the second transparent conductive film, the first etching solution and the second etching solution may be respectively used for etching, and the etching is used to form an i-shaped structure of the auxiliary electrode and the anode. In an exemplary embodiment, the first etching solution may be an etching solution (ITO etching solution) for etching the transparent conductive material, and the second etching solution may be an etching solution (Metal etching solution) for etching the Metal material. In an exemplary embodiment, after forming a photoresist pattern through masking, exposure, and development of the photoresist, the etching process may include: the second transparent conductive film not covered by the photoresist is etched by using an ITO etching solution to expose the fourth metal film in the region not covered by the photoresist, thereby forming patterns of the third anode 72 and the third connection electrode 83. And then etching the exposed fourth Metal film using Metal etching solution to form a pattern of a second anode 71 and a second connection electrode 82. Since the Metal etching liquid etches the fourth Metal film at a rate greater than the first and second transparent conductive films, the side surfaces of the second anode 71 and the second connection electrode 82 are etched to be a pit. The first anode 70 under the second anode 71 and the third anode 72 over the second anode 71 both protrude a distance from the second anode 71, and the first connection electrode 81 under the second connection electrode 82 and the third connection electrode 83 over the second connection electrode 82 protrude a distance from the second connection electrode 82, forming an i-shaped structure.

In an exemplary embodiment, the fourth metal thin film material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material thereof, and the second transparent conductive material may employ Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like.

(9) And forming a pixel definition layer pattern. In an exemplary embodiment, the forming of the pixel defining layer pattern may include: base:Sub>A pixel defining film is coated on the substrate on which the patterns are formed, the pixel defining film is patterned bybase:Sub>A patterning process to formbase:Sub>A pattern ofbase:Sub>A Pixel Defining (PDL) layer 91, the pixel defining layer 91 is formed withbase:Sub>A first pixel opening K1 andbase:Sub>A second auxiliary electrode opening K2, the pixel defining layer 91 in the first pixel opening K1 is removed to exposebase:Sub>A portion of the surface of the third anode 72 in the anode, and the pixel defining layer 91 in the second auxiliary electrode opening K2 is removed to expose the entire surfaces of the second connecting electrode 82 and the third connecting electrode 83 in the auxiliary connecting electrode, as shown in fig. 23 and 24, fig. 24 isbase:Sub>A cross-sectional view taken alongbase:Sub>A-base:Sub>A direction in fig. 23.

In an exemplary embodiment, an orthogonal projection of the first pixel opening K1 on the substrate is located within a range of an orthogonal projection of the third anode 72 on the substrate, an orthogonal projection of the second auxiliary electrode opening K2 on the substrate is located within a range of an orthogonal projection of the first connection electrode 81 on the substrate, and orthogonal projections of the second connection electrode 82 and the third connection electrode 83 on the substrate are located within a range of an orthogonal projection of the second auxiliary electrode opening K2 on the substrate. The second auxiliary electrode opening K2 exposes the entire surfaces of the second connection electrode 82 and the third connection electrode 83, which means that the second auxiliary electrode opening has a second lower opening adjacent to one side of the substrate and a second upper opening away from one side of the substrate, and an orthogonal projection of the second connection electrode 82 and the third connection electrode 83 on the substrate is within an orthogonal projection range of the second lower opening on the substrate.

In an exemplary embodiment, the pixel defining layer may employ polyimide, acryl, or polyethylene terephthalate, or the like. The shape of the first pixel opening K1 may be similar to the shape of the plurality of anode blocks, and the shape of the second auxiliary electrode opening K2 may be rectangular in a plane parallel to the display substrate. The cross-sectional shapes of the first pixel opening K1 and the second auxiliary electrode opening K2 in a plane perpendicular to the display substrate may be rectangular, trapezoidal, or the like.

(10) An organic light emitting layer pattern is formed. In an exemplary embodiment, forming the organic light emitting layer pattern may include: an organic light emitting material is deposited on the substrate on which the aforementioned pattern is formed, and an organic light emitting layer 92 and an organic light emitting block pattern are formed, the organic light emitting layer 92 is disposed in a region other than the third connection electrode 83, the organic light emitting layer 92 is connected to the third anode 72 of the anode 74 through the first pixel opening K1, the organic light emitting block is disposed on a surface of the third connection electrode 83 on a side away from the substrate, and the organic light emitting block is disposed apart from the organic light emitting layer 92, as shown in fig. 25.

In other exemplary embodiments, the organic light emitting layer pattern may also be formed by inkjet printing, which is not limited by the embodiments of the present disclosure.

In the exemplary embodiment, the third connection electrode 83 protrudes a distance from the second connection electrode 82 due to the zigzag structure of the auxiliary electrode, and thus the organic light emitting material is disconnected at the side edges of the third connection electrode 83, the organic light emitting block is formed on the second upper surface of the third connection electrode 83, and the organic light emitting layer 92 is formed in the region except the third connection electrode 83, thereby achieving the mutual isolation of the organic light emitting layer 92 and the organic light emitting block. In an exemplary embodiment, an orthographic projection of the organic light emitting blocks on the substrate may be approximately equal to an orthographic projection of the third connection electrodes 83 on the substrate. The auxiliary electrode with the I-shaped structure is used for separating the organic light-emitting layer to form an isolated organic light-emitting block, so that the interference of the organic light-emitting block on emergent light is effectively avoided, the quality of the emergent light is improved, and the display quality is favorably improved.

In an exemplary embodiment, the organic light Emitting Layer may include a light Emitting Layer (EML), and any one or more of: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). In an exemplary embodiment, the organic light emitting layer may be formed by evaporation using a Fine Metal Mask (FMM) or an Open Mask (Open Mask), or by using an inkjet process.

In an exemplary embodiment, the organic light emitting layer may be prepared using the following preparation method. The method comprises the steps of firstly adopting an open mask to sequentially evaporate a hole injection layer and a hole transport layer, and forming a common layer of the hole injection layer and the hole transport layer on a display substrate. Subsequently, a fine metal mask is used to evaporate an electron blocking layer and a red light emitting layer on the red sub-pixel, evaporate an electron blocking layer and a green light emitting layer on the green sub-pixel, and evaporate an electron blocking layer and a blue light emitting layer on the blue sub-pixel, and the electron blocking layer and the light emitting layer of the adjacent sub-pixels may overlap slightly (for example, the overlapping portion occupies less than 10% of the area of the respective light emitting layer patterns), or may be isolated. And then, sequentially evaporating a hole blocking layer, an electron transport layer and an electron injection layer by using an open mask, and forming a common layer of the hole blocking layer, the electron transport layer and the electron injection layer on the display substrate.

In an exemplary embodiment, the electron blocking layer may serve as a microcavity adjusting layer of the light emitting device, and by designing the thickness of the electron blocking layer, the thickness of the organic light emitting layer between the cathode and the anode may satisfy the design of the microcavity length. In some exemplary embodiments, a hole transport layer, a hole blocking layer, or an electron transport layer in the organic light emitting layer may be used as a microcavity adjusting layer of the light emitting device, and the disclosure is not limited herein.

In an exemplary embodiment, the light emitting layer may include a Host (Host) material and a guest (Host) material doped in the Host material, and the doping ratio of the guest material of the light emitting layer is 1% to 20%. In the range of the doping proportion, on one hand, the host material of the light-emitting layer can effectively transfer exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light, and on the other hand, the host material of the light-emitting layer carries out 'dilution' on the guest material of the light-emitting layer, thereby effectively improving the fluorescence quenching caused by the mutual collision among molecules and the mutual collision among energies of the guest material of the light-emitting layer, and improving the light-emitting efficiency and the service life of the device. In an exemplary embodiment, the doping ratio refers to a ratio of the mass of the guest material to the mass of the light emitting layer, i.e., mass percentage. In an exemplary embodiment, the host material and the guest material may be co-evaporated by a multi-source evaporation process to be uniformly dispersed in the light emitting layer, and the doping ratio may be controlled by controlling an evaporation rate of the guest material during evaporation, or by controlling an evaporation rate ratio of the host material and the guest material. In an exemplary embodiment, the thickness of the light emitting layer may be about 10nm to 50nm.

In exemplary embodiments, the hole injection layer may employ an inorganic oxide such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or may employ a p-type dopant of a strong electron-withdrawing system and a dopant of a hole-transporting material. In an exemplary embodiment, the thickness of the hole injection layer may be about 5nm to 20nm.

In an exemplary embodiment, a material with high hole mobility, such as an arylamine compound, may be used for the hole transport layer, and the substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene, furan, or the like. In an exemplary embodiment, the thickness of the hole transport layer may be about 40nm to 150nm.

In exemplary embodiments, the hole blocking layer and the electron transport layer may employ aromatic heterocyclic compounds, for example, imidazole derivatives such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazolophenanthrin derivatives, and the like; oxazine derivatives such as pyrimidine derivatives and triazine derivatives; and compounds containing a nitrogen-containing six-membered ring structure (including compounds having a phosphine oxide substituent on the heterocyclic ring) such as quinoline derivatives, isoquinoline derivatives, and phenanthroline derivatives. In an exemplary embodiment, the hole blocking layer may have a thickness of about 5nm to 15nm, and the electron transport layer may have a thickness of about 20nm to 50nm.

In an exemplary embodiment, the electron injection layer may employ an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or a compound of these alkali metals or metals, or the like. In an exemplary embodiment, the thickness of the electron injection layer may be about 0.5nm to 2nm.

(11) Forming a cathode pattern. In an exemplary embodiment, the forming of the cathode pattern may include: a cathode material is deposited on the substrate on which the pattern is formed to form a pattern of a cathode 94, and the cathode 94 is connected to the organic light emitting layer 92 as shown in fig. 26.

In an exemplary embodiment, the cathode 94 may be a unitary structure that is connected together. The cathode 94 is disposed on the organic light emitting layer 92 in a region other than the auxiliary connection electrode. In the region of the auxiliary connection electrode, the cathode 94 is disposed on the exposed surface of the organic light emitting block on the one hand, and on the other hand, forms a structure that wraps the auxiliary connection electrode and the organic light emitting block.

So far, a light emitting structure layer pattern is prepared on the driving circuit layer, the light emitting structure layer comprises an anode, an auxiliary connection electrode, a pixel definition layer, an organic light emitting layer and a cathode, the organic light emitting layer is respectively connected with the anode and the cathode, the cathode is connected with the auxiliary connection electrode, and the auxiliary connection electrode is electrically connected with a second power line through the auxiliary cathode.

In an exemplary embodiment, the manufacturing process of the display substrate may further include forming an encapsulation layer pattern, and the forming of the encapsulation layer pattern may include: first, an open mask is used to deposit a first inorganic film by Plasma Enhanced Chemical Vapor Deposition (PECVD) to form a first packaging layer. And then, ink-jet printing organic materials on the first packaging layer by using an ink-jet printing process, and forming a second packaging layer after curing to form a film. And then, depositing a second inorganic film by using an open mask plate to form a third packaging layer, wherein the first packaging layer, the second packaging layer and the third packaging layer form the packaging layer. In an exemplary embodiment, the first encapsulation layer and the third encapsulation layer may be one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer, the second encapsulation layer may be made of a resin material, and a stacked structure of inorganic material/organic material/inorganic material is formed, and the organic material layer is disposed between the two inorganic material layers, so that it may be ensured that external moisture cannot enter the light emitting structure layer.

In an exemplary embodiment, after the encapsulation layer is prepared, a color film layer and a black matrix may be fabricated on another substrate through a patterning process to form a color film cover plate, a frame sealing adhesive is coated on a surface of the color film cover plate, and the color film cover plate and the display substrate are pressed to form the OLED display panel shown in fig. 5, where only the black matrix BM is shown in fig. 5, the color film layer is not shown, the black matrix has a plurality of opening regions arranged in a matrix, and the color film layer is filled in the opening regions.

In other exemplary embodiments, the color film layer and the black matrix may be prepared on the display substrate, and in this case, the color film layer and the black matrix may be prepared after the cathode is formed and before the encapsulation layer is formed. Through setting up black matrix, can effectively prevent the optical crosstalk between the adjacent sub-pixel, avoid colour mixture, improve display effect.

With reference to fig. 5 to 26, in each sub-pixel, the first active layer 11, the first gate electrode 12, the first source electrode 13 and the first drain electrode 14 form a first transistor T1, the second active layer 21, the second gate electrode 22, the second source electrode 23 and the second drain electrode 24 form a second transistor T2, the third active layer 31, the third gate electrode 32, the third source electrode 33 and the third drain electrode 34 form a third transistor T3, the first electrode plate 41 and the second electrode plate 42 form a first capacitor, the second electrode plate 42 and the third electrode plate 43 form a second capacitor, and the first capacitor and the second capacitor are in a parallel structure, so as to realize the storage of the potential of the second gate electrode 22 of the sub-pixel. The first transistor T1, the second transistor T2, the third transistor T3, the first capacitor, and the second capacitor in the first subpixel P1 and the second subpixel P2 are mirror-symmetrical with respect to the compensation signal line S, and the first transistor T1, the second transistor T2, the third transistor T3, the first capacitor, and the second capacitor in the third subpixel P3 and the fourth subpixel P4 are mirror-symmetrical with respect to the compensation signal line S.

In each sub-pixel, the first gate electrode 12 is connected to the first scanning signal line G1, the first source electrode 13 is connected to the data signal line D, and the first drain electrode 14 is connected to the second gate electrode 22 of the sub-pixel. The second gate electrode 22 is connected to the first drain electrode 14 of the sub-pixel, the second source electrode 23 is connected to the first power line VDD via the lateral power connection line 52, and the second drain electrode 24 is connected to the anode of the sub-pixel. The third gate electrode 32 is connected to the second scanning signal line G2, the third source electrode 33 is connected to the compensation signal line S, and the third drain electrode 34 is connected to the second drain electrode 24 of the subpixel. The first plate 41 is connected to the second drain electrode 24 and the third drain electrode 34 of the sub-pixel, the second plate 42 is connected to the second gate electrode 22 and the first drain electrode 14 of the sub-pixel, and the third plate 43 is connected to the second drain electrode 24 and the third drain electrode 34 of the sub-pixel. The anode 74 is connected to the second drain electrode 24 of the sub-pixel, and the cathode 94 covering all the sub-pixels is connected to the second power line VSS through an auxiliary connection electrode, so that the organic light emitting layer 92 between the anode 74 and the cathode 94 emits light of a corresponding luminance in response to a current of the second drain electrode 24 of the sub-pixel.

In an exemplary embodiment, the first, second, and third conductive layers may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, and the like. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer is called a Buffer (Buffer) layer for improving the water and oxygen resistance of the substrate, the second insulating layer is called a Gate Insulating (GI) layer, the third insulating layer is called an interlayer Insulating (ILD) layer, and the fourth insulating layer is called a Passivation (PVX) layer. The thickness of the second insulating layer is smaller than that of the third insulating layer, the thickness of the first insulating layer is smaller than the sum of the thicknesses of the second insulating layer and the third insulating layer, and the capacity of the storage capacitor is improved on the premise that the insulating effect is guaranteed. The planarization layer may be made of an organic material, the transparent conductive film may be made of ITO or IZO, and the pixel defining layer may be made of polyimide, acryl, or polyethylene terephthalate. The cathode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made using any one or more of the above metals.

In some possible implementations, the first insulating layer has a thickness of 3000 to 5000 angstroms, the second insulating layer has a thickness of 1000 to 2000 angstroms, the third insulating layer has a thickness of 4500 to 7000 angstroms, and the fourth insulating layer has a thickness of 3000 to 5000 angstroms. The first conductive layer has a thickness of 80 to 1200 angstroms, the second conductive layer has a thickness of 3000 to 5000 angstroms, and the third conductive layer has a thickness of 3000 to 9000 angstroms.

In example embodiments, the semiconductor layer may employ an oxide containing indium and tin, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, an oxide containing indium and gallium and zinc, or the like. The semiconductor layer may be a single layer, or may be a double layer, or may be a multilayer.

As shown in fig. 5 to 26, the display substrate provided by the present disclosure includes:

a substrate 10;

a first conductive layer disposed on the substrate 10, the first conductive layer including a first plate 41 and a compensation signal line S;

a first insulating layer 61 covering the first conductive layer;

a semiconductor layer disposed on the first insulating layer 61, the semiconductor layer including the first active layer 11, the second active layer 21, and the third active layer 31;

a second insulating layer 62 and a second conductive layer disposed on the second insulating layer 62, the second conductive layer including: a first scanning signal line G1, a second scanning signal line G2, a second plate 42, a longitudinal power connection line 51, a lateral power connection line 52, an auxiliary power line 53, a first gate electrode 12, a second gate electrode 22, and a third gate electrode 32, and a second insulating layer 62 is patterned the same as the second conductive layer; an overlapping region exists between the orthographic projection of the second polar plate 42 on the substrate 10 and the orthographic projection of the first polar plate 41 on the substrate 10, and the second polar plate 42 and the first polar plate 41 form a first capacitor;

a third insulating layer 63 covering the second conductive layer, on which a plurality of via holes are respectively formed;

a third conductive layer disposed on the third insulating layer 63, the third conductive layer including a first power line VDD, a second power line VSS, a data signal line D, a third scan connection line 54, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34, and a third electrode plate 43, the first power line VDD is connected to the longitudinal power connection line 51 and the lateral power connection line 52 through an eleventh via V11, the second power line VSS is connected to the auxiliary power line 53 through a seventh via V7, the first source electrode 13 is connected to the data signal line D as an integral structure, the second source electrode 23 is connected to one end of the second active layer 21 through a third via V3, the third source electrode 33 is connected to the compensation signal line S through an eighth via V8, the first drain electrode 14 is connected to the second gate electrode 22 and the second electrode plate 42 through a ninth via V9, the second drain electrode 24, the third drain electrode 34 and the third electrode plate 43 are connected to each other as an integral structure, the third electrode plate 43 is connected to the substrate 10 through a tenth via V9, and a projection area of the third electrode plate 42 on the substrate 10 exists;

a fourth insulating layer 64 and a flat layer 65 covering the third conductive layer, and a plurality of via holes are respectively formed thereon;

an anode 74 and an auxiliary connection electrode disposed on the planarization layer 65, the anode 74 including a first anode 70, a second anode 71, and a third anode 72 stacked, the auxiliary connection electrode including a first connection electrode 81, a second connection electrode 82, and a third connection electrode 83 stacked, the first anode 70 being connected to the drain electrode of the second transistor through a sixteenth via V16, the first connection electrode 81 being connected to a second power line VSS through a seventeenth via V17;

a pixel defining layer 91 disposed on the planarization layer 65, the pixel defining layer 91 defining a first pixel opening exposing the anode electrode at each sub-pixel, the pixel defining layer 91 defining a second auxiliary electrode opening exposing the auxiliary connection electrode on the second power line VSS;

an organic light emitting layer 92 disposed in the first pixel opening region and an organic light emitting block disposed in the second auxiliary electrode opening region, the organic light emitting layer 92 being connected to the anode, the organic light emitting block being disposed apart from the organic light emitting layer 92;

a cathode 94, the cathode 94 of the display region 100 being connected to the organic light emitting layer 92, the cathode of the transparent region being connected to a second power line VSS via an auxiliary connection electrode;

and an encapsulation layer covering the structure.

When a short-circuit fault point occurs between the first scanning connecting line and/or the second scanning connecting line and other signal lines in the driving circuit layer, the first scanning connecting line and/or the second scanning connecting line on two sides of the short-circuit fault point can be cut off through laser cutting, so that the short-circuit fault can be repaired. Illustratively, as shown in fig. 27, when a short-circuit fault point occurs at an overlapping position of the data signal line and the first scan connection line, the first scan connection line on both sides of the short-circuit fault point may be cut by laser cutting to repair the short-circuit fault.

In the display substrate according to the embodiment of the present disclosure, as shown in fig. 28, when a short-circuit fault point occurs between a certain sub-anode block and another signal line in the driving circuit layer, a position of the first connection electrode in the connection structure on one side of the sub-anode block may be cut by laser, so that another sub-anode block in the sub-pixel corresponding to the sub-anode block may be electrically connected to the driving transistor, and the sub-anode block floats to repair the short-circuit fault.

The structure and the manufacturing process thereof shown in the present disclosure are only an exemplary illustration, and in an exemplary embodiment, the corresponding structure may be changed and a patterning process may be added or reduced according to actual needs. For example, the display area may include 3 sub-pixels. As another example, the pixel drive circuit may be 5T1C or 7T1C. For another example, other electrodes or leads may be disposed in the film structure, and the disclosure is not limited thereto.

It can be seen from the structure and the preparation process of the display substrate described above that, the display substrate provided by the present disclosure performs the ring winding design of the first scanning signal line and the second scanning signal line with the corresponding scanning connection lines respectively in the display area, and the ring winding positions of the first scanning signal line and the second scanning signal line avoid the first power line and the second power line, thereby avoiding the problem that the product yield is easily affected due to the large overlapping area of the power line and other signal lines, optimizing Cross (Cross) points between the signal lines to the minimum under the functional condition of realizing maintenance, further improving the product yield, and providing technical support for transparent display products.

According to the display substrate provided by the disclosure, the second plate made of the metal oxide material is used as the polar plate of the storage capacitor, the second plate and the first polar plate in the first conducting layer and the third polar plate in the third conducting layer respectively form the storage capacitor, the first polar plate and the third polar plate have the same potential, and the second plate has the potential different from the first polar plate and the third polar plate, so that two storage capacitors connected in parallel are formed among the first polar plate, the second polar plate and the third polar plate, the capacity of the storage capacitor is effectively increased, and high-resolution display is facilitated.

The preparation process can be realized by utilizing the existing mature preparation equipment, has small improvement on the existing process, can be well compatible with the existing preparation process, and has the advantages of simple process realization, easy implementation, high production efficiency, low production cost and high yield. The design of the present disclosure can repair the sub-pixel, and the yield of the product is improved by more than one time.

In an exemplary embodiment, the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), a quantum dot light emitting diode display (QDLED), and the like, and the disclosure is not limited thereto.

The present exemplary embodiment also provides a method of manufacturing a display substrate, which may include a plurality of sub-pixels; the preparation method can comprise the following steps:

forming a plurality of display units on a substrate, wherein at least one display unit comprises a display area and a transparent area, a first power line and a second power line are arranged in at least one display area along a first direction, the first power line and the second power line extend along a second direction, a first scanning signal line, a second scanning connecting line and a first scanning connecting line are arranged in at least one display area along the second direction, the second scanning connecting line and the second scanning signal line are mutually connected to form a first annular structure, a third scanning connecting line is arranged in at least one display area between the first scanning signal line and the first scanning connecting line, the third scanning connecting line, the first scanning connecting line and the first scanning signal line are mutually connected to form a second annular structure, and the first direction crosses the second direction; the orthographic projection of the first annular structure on the substrate and the orthographic projection of the first power supply line and the second power supply line on the substrate do not have an overlapping area; and no overlapping area exists between the orthographic projection of the second annular structure on the substrate and the orthographic projection of the first power supply line and the second power supply line on the substrate.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the purpose of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. A display substrate is characterized by comprising a substrate and a plurality of display units arranged on the substrate, wherein each display unit comprises a display area and a transparent area, and the display area comprises a plurality of sub-pixels;

the display area is provided with a first power line and a second power line along a first direction, the first power line and the second power line extend along a second direction, the display area is provided with a first scanning signal line, a second scanning connecting line and a first scanning connecting line along the second direction, the second scanning connecting line and the second scanning signal line are mutually connected to form a first annular structure, a third scanning connecting line is arranged between the first scanning signal line and the first scanning connecting line in the display area, the third scanning connecting line, the first scanning connecting line and the first scanning signal line are mutually connected to form a second annular structure, and the first direction is crossed with the second direction;

the orthographic projection of the first annular structure on the substrate is not overlapped with the orthographic projection of the first power supply line and the second power supply line on the substrate; an orthographic projection of the second annular structure on the substrate does not overlap with orthographic projections of the first power line and the second power line on the substrate.

2. The display substrate of claim 1, wherein an orthographic projection of the first annular structure on the base does not overlap an orthographic projection of the second annular structure on the base, the orthographic projection of the second annular structure on the base encompassing the orthographic projection of the first annular structure on the base.

3. The display substrate according to claim 1, wherein the sub-pixel comprises a driving circuit layer disposed on the substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate in a direction perpendicular to the display substrate, the driving circuit layer comprising a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer;

the first conducting layer comprises a compensation signal line and a first polar plate, the semiconductor layer comprises an active layer of a plurality of transistors, the second conducting layer comprises the first scanning signal line, the second scanning signal line, the first scanning connecting line, the second scanning connecting line, a second polar plate and gate electrodes of a plurality of transistors, the third conducting layer comprises the first power line, the second power line, the third scanning connecting line, a data signal line and source electrodes and drain electrodes of a plurality of transistors, and an overlapping region exists between the orthographic projection of the second polar plate on the substrate and the orthographic projection of the first polar plate on the substrate so as to form a first capacitor;

the second scanning connecting line and the second scanning signal line are connected into an integral structure;

the third scanning connecting line is electrically connected with the first scanning connecting line and the first scanning signal line through a via hole respectively.

4. The display substrate of claim 1, wherein at least one of the sub-pixels comprises a first transistor, a second transistor, a third transistor, and a first capacitor, the first capacitor comprising a first plate and a second plate, wherein:

a gate electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to a data signal line, a second electrode of the first transistor is electrically connected to a gate electrode of the second transistor, a first electrode of the second transistor is electrically connected to the first power supply line, a second electrode of the second transistor is electrically connected to a first electrode of an organic electroluminescent diode, a gate electrode of the third transistor is electrically connected to the second scan signal line, a first electrode of the third transistor is electrically connected to a compensation signal line, a second electrode of the third transistor is electrically connected to a second electrode of the second transistor, and a second electrode of the organic electroluminescent diode is electrically connected to the second power supply line; the first polar plate is electrically connected with a second pole of the second transistor, and the second polar plate is electrically connected with a gate electrode of the second transistor.

5. The display substrate according to claim 1, wherein the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and in the first direction, the first sub-pixel and the second sub-pixel are alternately arranged to form a first row, and the third sub-pixel and the fourth sub-pixel are alternately arranged to form a second row; in the second direction, the first sub-pixels and the third sub-pixels are alternately arranged to form a first column, and the second sub-pixels and the fourth sub-pixels are alternately arranged to form a second column;

the first scanning connecting line and the second scanning connecting line are positioned in the first sub-pixel and the second sub-pixel, and the first scanning signal line and the second scanning signal line are positioned in the third sub-pixel and the fourth sub-pixel.

6. The display substrate according to claim 5, wherein at least one of the sub-pixels comprises a first transistor, a second transistor, and a third transistor, wherein the first transistor comprises a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the second transistor comprises a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the third transistor comprises a third active layer, a third gate electrode, a third source electrode, and a third drain electrode, and wherein:

a region where the second scanning signal line overlaps with the third active layer in the third sub-pixel and the fourth sub-pixel serves as a third gate electrode in the third sub-pixel and the fourth sub-pixel; the region where the second scanning connecting line is overlapped with the third active layer in the first sub-pixel and the second sub-pixel is used as a third gate electrode in the first sub-pixel and the second sub-pixel;

a region where the first scanning signal line overlaps with the first active layer in the third sub-pixel and the fourth sub-pixel serves as a first gate electrode in the third sub-pixel and the fourth sub-pixel; the area where the first scanning connection line overlaps with the first active layer in the first sub-pixel and the second sub-pixel is used as a first gate electrode in the first sub-pixel and the second sub-pixel.

7. The display substrate of claim 6, wherein at least one of the display regions further comprises a compensation signal line extending in a second direction;

the first gate electrode, the second gate electrode and the third gate electrode in the first sub-pixel and the second sub-pixel are in mirror symmetry relative to a vertical axis, the first gate electrode, the second gate electrode and the third gate electrode in the third sub-pixel and the fourth sub-pixel are in mirror symmetry relative to the vertical axis, and the vertical axis is the compensation signal line.

8. The display substrate according to claim 7, wherein the compensation signal line is provided with a compensation connection line protruding in a first direction and in a direction opposite to the first direction;

the compensation connecting line is positioned at the adjacent position of the first sub-pixel and the third sub-pixel and the adjacent position of the second sub-pixel and the fourth sub-pixel;

the compensation connection line is electrically connected with a third source electrode of the third transistor through a via hole.

9. The display substrate of claim 8, wherein the third active layers of the first to fourth sub-pixels are disposed close to the compensation connection line, and an overlapping region exists between an orthographic projection of the third active layer on the substrate and an orthographic projection of the compensation connection line on the substrate.

10. The display substrate of claim 8, wherein the third active layer in the first sub-pixel and the third active layer in the third sub-pixel are of interconnected integral structure, and wherein the third active layer in the second sub-pixel and the third active layer in the fourth sub-pixel are of interconnected integral structure.

11. The display substrate of claim 6, wherein at least one of the sub-pixels further comprises a first capacitor comprising a first plate and a second plate disposed opposite to each other, and the second gate electrode crosses over the second active layer and is connected to the second plate to form a unitary structure.

12. The display substrate according to claim 11, wherein the first plate in the first sub-pixel is provided with a first opening on a side close to the third sub-pixel and far from the second sub-pixel; the first polar plate in the second sub-pixel is also provided with the first opening at one side close to the fourth sub-pixel and far away from the first sub-pixel;

a second opening is formed in one side, close to the first sub-pixel and close to the fourth sub-pixel, of the first polar plate in the third sub-pixel; the first polar plate in the fourth sub-pixel is also provided with the second opening at one side close to the second sub-pixel and close to the third sub-pixel;

the first active layer in the first sub-pixel and the second sub-pixel is arranged at a position close to the first opening, and the first active layer in the third sub-pixel and the fourth sub-pixel is arranged at a position close to the second opening.

13. The display substrate according to claim 11, wherein at least one of the sub-pixels further comprises a second capacitor, the second capacitor comprises a second plate and a third plate which are oppositely arranged, an overlapping region exists between an orthographic projection of the third plate on the substrate and an orthographic projection of the second plate on the substrate, and the third plate is electrically connected with the first plate through a via hole.

14. A display device, comprising: a display substrate as claimed in any one of claims 1 to 13.

15. A method for manufacturing a display substrate, comprising:

forming a plurality of display units on a substrate, wherein each display unit comprises a display area and a transparent area, the display area is provided with a first power line and a second power line along a first direction, the first power line and the second power line extend along a second direction, the display area is provided with a first scanning signal line, a second scanning connecting line and a first scanning connecting line along the second direction, the second scanning connecting line and the second scanning signal line are connected with each other to form a first annular structure, the display area is provided with a third scanning connecting line between the first scanning signal line and the first scanning connecting line, the third scanning connecting line, the first scanning connecting line and the first scanning signal line are connected with each other to form a second annular structure, and the first direction is crossed with the second direction; the orthographic projection of the first annular structure on the substrate does not overlap with the orthographic projection of the first power supply line and the second power supply line on the substrate; an orthographic projection of the second annular structure on the substrate does not overlap with orthographic projections of the first power line and the second power line on the substrate.