CN115547931B - Manufacturing method of semiconductor device, semiconductor device and transistor - Google Patents
Manufacturing method of semiconductor device, semiconductor device and transistor Download PDFInfo
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- CN115547931B CN115547931B CN202211546019.7A CN202211546019A CN115547931B CN 115547931 B CN115547931 B CN 115547931B CN 202211546019 A CN202211546019 A CN 202211546019A CN 115547931 B CN115547931 B CN 115547931B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
The application provides a manufacturing method of a semiconductor device, the semiconductor device and a transistor, wherein the method comprises the following steps: firstly, providing a substrate comprising a first area and a second area which are adjacent, wherein the first area comprises a plurality of first subregions arranged at intervals and a plurality of second subregions arranged at intervals; then, performing first preset treatment on the plurality of first sub-regions and the second region, and enabling part of the second region to form a preliminary doping region; then, performing second preset treatment on the plurality of second sub-regions and the preliminary doping regions to enable the plurality of second sub-regions to form second doping regions and the preliminary doping regions to form target doping regions; and finally, forming a first device layer on part of the surface of the substrate to obtain a first device, and forming a second device layer on part of the surface of the substrate to obtain a second device. The starting voltage of the second device is ensured to be smaller, and the performance of the semiconductor device is ensured to be better.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor device, and a transistor.
Background
Because a Native MOS (Metal Oxide Semiconductor Field Effect Transistor) has a smaller turn-on voltage, that is, the device can be turned on to work only by applying a small voltage, the Native MOS is mainly used in a specific circuit.
Currently, in the development of medium voltage device process, the design of Native MOS (intrinsic MOS transistor) does not need additional mask, which shares the mask during ion implantation with N +/P + shared source and Drain regions, and shares LDD (Lightly Doped Drain) mask with MV (medium voltage) NLDD (N Lightly Doped Drain)/PLDD (P Lightly Doped Drain), and Native NMOS (intrinsic MOS N-transistor) and HPD (high voltage P-drift) share Well mask.
However, since the Native NMOS and the HPD are currently shared masks, the Well of the Native NMOS, i.e. the HPD concentration is too high, which results in a large threshold voltage of the Native NMOS and a slow turn-on voltage, such that the turn-on voltage is about 0.5V (generally, the turn-on voltage of the Native MOS is less than 0.2V), which cannot meet the customer requirements for the Native MOS device.
In addition, in order to reduce the turn-on voltage of Native MOS, the doping amount of Native NMOS Well, i.e. the doping amount of HPD, is generally reduced to achieve the purpose of reducing the turn-on voltage, for example, when HPD is reduced by 1/2, the turn-on voltage can be reduced to about 0.2V.
However, if the purpose of reducing the turn-on voltage is achieved by reducing the doping amount of the HPD, it is necessary to add a mask to achieve the purpose of achieving two different implantation concentrations for the HPD of the Native NMOS and the HPD of the other region, and the increase of the mask will increase the manufacturing process and the manufacturing cost.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a method for manufacturing a semiconductor device, and a transistor, so as to solve the problems of a depletion transistor in the prior art, such as a large turn-on voltage and a high cost.
According to an aspect of an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent, the first area comprises a plurality of first sub-areas which are arranged at intervals, and a plurality of second sub-areas which are arranged at intervals; performing first predetermined processing on the plurality of first sub-regions and the second region, so that the plurality of first sub-regions form a first doped region, and a part of the second region forms a preliminary doped region; performing second predetermined processing on the plurality of second sub-regions and the preliminary doping region, so that the plurality of second sub-regions form a second doping region and the preliminary doping region forms a target doping region, wherein the first predetermined processing and the second predetermined processing respectively comprise ion implantation, the first predetermined processing and the second predetermined processing have different doping types and different doping concentrations; forming a first device layer on a part of the surface of the substrate to obtain a first device, and forming a second device layer on a part of the surface of the substrate to obtain a second device, wherein the projection of the first device layer in the substrate is located in the first doped region or the second doped region, and the projection of the second device layer in the substrate is located in the target doped region.
Optionally, performing a first predetermined process on the plurality of first sub-regions and the second region, so that the plurality of first sub-regions form a first doped region, and a part of the second region forms a preliminary doped region, includes: forming a first mask layer on the surface of the substrate; and by taking the first mask layer as a mask, forming the first doping regions in the plurality of first sub-regions and forming the preparation doping regions in part of the second region through the first preset treatment.
Optionally, performing a second predetermined process on the plurality of second sub-regions and the preliminary doping region, so that the plurality of second sub-regions form a second doping region, and the preliminary doping region forms a target doping region, including: forming a second mask layer on the surface of the substrate; and forming the second doping area in the plurality of second sub-areas by using the second mask layer as a mask through the second preset treatment, wherein the preparation doping area forms the target doping area.
Optionally, providing a substrate comprising: providing a preparation base, and carrying out thermal oxidation treatment on the preparation base to enable the preparation base to form a laminated substrate and an oxidation layer, wherein the substrate comprises the first area and the first preparation area which are adjacent; and at least carrying out the ion implantation on the first preparation area to obtain a preset well region, so that the first preparation area forms the second area to obtain the substrate.
Optionally, forming a first device layer on a portion of the surface of the substrate to obtain a first device, including: forming a first gate structure on a part of exposed surface of the oxide layer, wherein the first gate structure comprises a first gate oxide layer and a first gate which are sequentially stacked, and the projection of the first gate structure in the substrate covers one first doped region or one second doped region; and respectively forming a first source region and a first drain region in the substrate at two sides of the first gate structure to obtain the first device.
Optionally, forming a second device layer on a portion of the surface of the substrate to obtain a second device, including: forming a second gate structure on a part of the exposed surface of the oxide layer, wherein the second gate structure comprises a second gate oxide layer and a second gate which are sequentially stacked, and the projection of the second gate structure in the substrate covers the target doping region; and respectively forming a second source region and a second drain region in the substrate at two sides of the second gate structure to obtain the second device.
Optionally, the doping type with a higher doping concentration in the first predetermined treatment and the second predetermined treatment is a predetermined type, and the doping type of the substrate is different from the predetermined type.
Optionally, the first device includes a high-voltage MOS transistor, and the second device includes a depletion-mode MOS transistor.
According to another aspect of the embodiments of the present invention, there is also provided a semiconductor device manufactured by any one of the methods.
According to another aspect of the embodiments of the present invention, there is also provided a transistor manufactured by any one of the methods or the semiconductor device.
In an embodiment of the present invention, in a method for manufacturing a semiconductor device, first, a substrate including a first region and a second region that are adjacent to each other is provided, where the first region includes a plurality of first sub-regions arranged at intervals and a plurality of second sub-regions arranged at intervals; then, performing first predetermined processing on the plurality of first sub-regions and the second region, so that the plurality of first sub-regions form a first doped region, and part of the second region forms a preliminary doped region; then, performing second predetermined processing on the plurality of second sub-regions and the preliminary doping region, so that the plurality of second sub-regions form a second doping region and the preliminary doping region forms a target doping region, wherein the first predetermined processing and the second predetermined processing respectively include ion implantation, the first predetermined processing and the second predetermined processing have different doping types, and in addition, the first predetermined processing and the second predetermined processing have different doping concentrations; and finally, forming a first device layer on part of the surface of the substrate to obtain a first device, and forming a second device layer on part of the surface of the substrate to obtain a second device, wherein the projection of the first device layer in the substrate is located in the first doped region or the second doped region, and the projection of the second device layer in the substrate is located in the target doped region. Compared with the problems of larger turn-on voltage and higher cost of the depletion transistor in the prior art, in the method for manufacturing the semiconductor device, the substrate including the first region and the second region is provided, the first region includes a plurality of first sub-regions and a plurality of second sub-regions which are arranged at intervals, the first predetermined treatment, namely ion implantation, is performed on the plurality of first sub-regions and the plurality of second regions, so that the plurality of first sub-regions and the plurality of second regions form the first doped region and the preliminary doped region respectively, and then the second predetermined treatment, namely another ion implantation, is performed on the plurality of second sub-regions and the preliminary doped region, so that the plurality of second sub-regions form the second doped region, meanwhile, the preparation doping area forms the target doping area, different doping types and doping concentrations of the first preset processing and the second preset processing are different, so that different doping types are formed in different areas in the first area, and the same area in the second area is subjected to ion implantation of two different doping types and different doping concentrations, so that the two doping types in the second area can be partially neutralized, the obtained doping concentration of the target doping area is ensured to be small, the starting voltage of the second device is ensured to be small due to the fact that the doping concentration of the target doping area is in direct proportion to the starting voltage, namely, the small doping concentration ensures that the starting voltage of the second device is small, the problems that the starting voltage of a depletion transistor is large and the cost is high in the prior art are solved, and the starting voltage of the semiconductor device is ensured to be small, the performance of the semiconductor device is guaranteed to be good.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 shows a schematic flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application;
FIG. 2 shows a schematic structural diagram obtained after formation of an oxide layer according to an embodiment of the present application;
FIG. 3 shows a schematic structural diagram of a substrate according to an embodiment of the present application;
FIG. 4 illustrates a schematic structural diagram obtained after forming a first mask layer according to an embodiment of the present application;
FIG. 5 illustrates a schematic structural diagram resulting from the formation of a first doped region and a preliminary doped region in accordance with an embodiment of the present application;
FIG. 6 shows a schematic structural diagram obtained after removing the first mask layer according to an embodiment of the present application;
FIG. 7 shows a schematic structural diagram obtained after forming a second mask layer according to an embodiment of the present application;
FIG. 8 illustrates a schematic structural diagram obtained after forming a second doped region and a target doped region according to an embodiment of the present application;
FIG. 9 is a schematic diagram illustrating a structure obtained after removing the second mask layer according to an embodiment of the present disclosure;
fig. 10 shows a schematic structural diagram obtained after forming a first gate structure and a second gate structure according to an embodiment of the present application;
FIG. 11 illustrates a schematic structural diagram resulting from the formation of source and drain regions in accordance with an embodiment of the present application;
fig. 12 shows a schematic diagram comparing turn-on voltages of a semiconductor device according to an embodiment of the present application with a prior art device.
Wherein the figures include the following reference numerals:
10. a substrate; 20. a first mask layer; 30. a second mask layer; 40. a first gate structure; 50. a second gate structure; 101. a first region; 102. a second region; 103. a first doped region; 104. preparing a doped region; 105. a second doped region; 106. a target doped region; 107. a substrate; 108. a first preparation area; 109. presetting a well region; 110. a first source region; 111. a first drain region; 112. a second source region; 113. a second drain region; 114. an oxide layer; 401. a first gate oxide layer; 402. a first gate electrode; 501. a second gate oxide layer; 502. a second gate.
Detailed Description
It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As mentioned in the background, the problem of the prior art that the on-voltage of the depletion transistor is large and the cost is high is solved, and in order to solve the problem, in an exemplary embodiment of the present application, a method for manufacturing a semiconductor device, a semiconductor device and a transistor are provided.
According to an embodiment of the present application, a method of fabricating a semiconductor device is provided.
Fig. 1 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, as shown in fig. 3, providing a substrate 10, where the substrate 10 includes a first region 101 and a second region 102 that are adjacent to each other, where the first region 101 includes a plurality of first sub-regions arranged at intervals and a plurality of second sub-regions arranged at intervals;
step S102, as shown in fig. 5, performing a first predetermined process on the plurality of first sub-regions and the second region 102, so that a first doped region 103 is formed in the plurality of first sub-regions, and a preliminary doped region 104 is formed in a portion of the second region 102;
step S103, as shown in fig. 5 to 8, performing a second predetermined process on the plurality of second sub-regions and the preliminary doping region 104, so that a second doping region 105 is formed in the plurality of second sub-regions, and a target doping region 106 is formed in the preliminary doping region 104, wherein the first predetermined process and the second predetermined process respectively include ion implantation, the first predetermined process and the second predetermined process have different doping types, and the first predetermined process and the second predetermined process have different doping concentrations;
step S104, forming a first device layer on a part of the surface of the substrate to obtain a first device, and forming a second device layer on a part of the surface of the substrate to obtain a second device, wherein a projection of the first device layer on the substrate is located in the first doped region or the second doped region, and a projection of the second device layer on the substrate is located in the target doped region.
In the manufacturing method of the semiconductor device, first, a substrate including a first region and a second region which are adjacent to each other is provided, wherein the first region includes a plurality of first sub-regions which are arranged at intervals and a plurality of second sub-regions which are arranged at intervals; then, performing a first predetermined process on the plurality of first sub-regions and the plurality of second regions, so that a first doped region is formed in the plurality of first sub-regions, and a preliminary doped region is formed in a portion of the plurality of second regions; then, performing a second predetermined process on the plurality of second sub-regions and the preliminary doping region to form a second doping region in the plurality of second sub-regions and a target doping region in the preliminary doping region, wherein the first predetermined process and the second predetermined process respectively include ion implantation, and the first predetermined process and the second predetermined process have different doping types and different doping concentrations; and finally, forming a first device layer on part of the surface of the substrate to obtain a first device, and forming a second device layer on part of the surface of the substrate to obtain a second device, wherein the projection of the first device layer in the substrate is positioned in the first doping region or the second doping region, and the projection of the second device layer in the substrate is positioned in the target doping region. Compared with the problems of larger turn-on voltage and higher cost of the depletion transistor in the prior art, the method for manufacturing the semiconductor device of the present application includes providing the substrate including the first region and the second region, wherein the first region includes a plurality of first sub-regions and a plurality of second sub-regions that are disposed at intervals, performing the first predetermined process, i.e., ion implantation, on the plurality of first sub-regions and the plurality of second regions to form the first doped region and the preliminary doped region, respectively, and performing the second predetermined process, i.e., another ion implantation, on the plurality of second sub-regions and the preliminary doped region to form the second doped region, meanwhile, the preparation doping area forms the target doping area, different doping types and doping concentrations of the first preset processing and the second preset processing are different, so that different doping types are formed in different areas in the first area, and the same area in the second area is subjected to ion implantation of two different doping types and different doping concentrations, so that the two doping types in the second area can be partially neutralized, the obtained doping concentration of the target doping area is ensured to be small, the starting voltage of the second device is ensured to be small due to the fact that the doping concentration of the target doping area is in direct proportion to the starting voltage, namely, the small doping concentration ensures that the starting voltage of the second device is small, the problems of large starting voltage and high cost of a depletion transistor in the prior art are solved, and the starting voltage of the semiconductor device is ensured to be small, the performance of the semiconductor device is guaranteed to be good.
In the prior art, in order to form a high-voltage transistor and a depletion transistor on the same substrate, and because the depletion transistor needs a smaller starting voltage, the high-voltage transistor needs a higher starting voltage, and in addition, because the doping concentration of a doping region is in direct proportion to the starting voltage, in order to form a doping region with a smaller doping concentration in the depletion transistor in the prior art, the depletion transistor is doped with a lower concentration first, then the doping region with a smaller concentration is covered by a mask plate, and then the doping with a higher concentration is carried out on other regions, so that a device with two starting voltages can be formed on the same substrate.
In a specific embodiment, when the substrate is N-type, the first predetermined process ion implantation has a doping type of N, the second predetermined process ion implantation has a doping type of P, and the doping concentration of the second predetermined process is greater than the doping concentration of the first predetermined process; second, the doping type of the ion implantation of the first predetermined process is P, the doping type of the ion implantation of the second predetermined process is N, the doping concentration of the first predetermined process is greater than the doping concentration of the second predetermined process, and the resulting transistor is a P-type transistor. More specifically, the ion implantation with higher energy is performed first, and then the ion implantation with lower energy is performed.
Specifically, P-type doping is mainly achieved by doping with a trivalent impurity element such as boron or gallium, and N-type doping is mainly achieved by doping with a pentavalent impurity element such as phosphorus or arsenic.
In addition, when the substrate is a P-type substrate, the first process may be a process in which the first process is performed with a doping type of P, the second process may be performed with an ion implantation with a doping type of N, and the second process may be performed with a doping concentration higher than the first process; second, the doping type of the ion implantation of the first predetermined process is N, the doping type of the ion concentration of the second predetermined process is P, the doping concentration of the first predetermined process is greater than the doping concentration of the second predetermined process, and the resulting transistor is an N-type transistor.
Specifically, one of the first sub-regions is adjacent to two of the second sub-regions, that is, a plurality of the first sub-regions and a plurality of the second sub-regions are arranged in one-to-one correspondence.
According to an embodiment of the present application, performing a first predetermined process on a plurality of the first sub-regions and the second region, so that the plurality of the first sub-regions form a first doped region and a part of the second region forms a preliminary doped region, includes: as shown in fig. 4, a first mask layer 20 is formed on the surface of the substrate 10; as shown in fig. 5, the first mask layer 20 is used as a mask to form the first doped regions 103 in the plurality of first sub-regions and the preliminary doped regions 104 in the second regions 102 by the first predetermined process. The first mask layer is formed on the surface of the substrate, so that the oxide layers corresponding to the first sub-regions and part of the second regions are exposed, and then the first mask layer is used as a mask to perform ion implantation on the first sub-regions and the second regions to obtain the preliminary doping region which is the first doping region, so that the first doping region and the preliminary doping region can be formed through a simpler process, and the semiconductor device is ensured to be simpler in manufacturing process.
Specifically, as shown in fig. 6, after the first doping region 103 and the preliminary doping region 104 are formed, the method further includes: the first mask layer is removed to obtain the structure shown in fig. 6.
In order to further ensure that the semiconductor device has low manufacturing cost and good performance, according to another specific embodiment of the present application, performing a second predetermined process on the plurality of second sub-regions and the preliminary doping region, so that the plurality of second sub-regions form a second doping region, and the preliminary doping region forms a target doping region, includes: as shown in fig. 7, a second mask layer 30 is formed on the surface of the substrate 10; as shown in fig. 8, the second mask layer 30 is used as a mask to form the second doping regions 105 in the plurality of second sub-regions and the target doping regions 106 in the preliminary doping regions by the second predetermined process. The second mask layer is formed on the surface of the substrate, so that the oxide layers corresponding to the second sub-regions and the preliminary doping regions are exposed, and then the second mask layer is used as a mask to perform ion implantation on the second sub-regions and the preliminary doping regions to obtain a plurality of second doping regions and target doping regions, namely, doping of a second type and concentration is performed on the basis of the original preliminary doping regions, so that partial neutralization of two kinds of doping is realized, the doping concentration of the target doping regions is ensured to be small, the starting voltage of the second device formed by the target doping regions is further ensured to be small, and the performance of the semiconductor device is further ensured to be good.
Specifically, as shown in fig. 9, after the second doping region 105 and the target doping region 106 are formed, the method further includes: the second mask layer is removed to obtain the structure shown in fig. 9.
In addition, the second preset treatment is carried out on the basis of the original preliminary doping area, namely, mask plates for the preliminary doping area in the prior art are reduced, and the manufacturing cost of the semiconductor device is further ensured to be low.
According to yet another specific embodiment of the present application, there is provided a substrate comprising: as shown in fig. 2, providing a preliminary base, and performing thermal oxidation treatment on the preliminary base to form a laminated substrate 107 and an oxide layer 114 on the preliminary base, wherein the substrate 107 includes the first region 101 and the first preliminary region 108 adjacent to each other; as shown in fig. 3, the ion implantation is performed on at least the first preliminary region to obtain a predetermined well region 109, so that the second region 102 is formed in the first preliminary region to obtain the substrate 10. By providing the preliminary substrate including the first region and the first preliminary region, and performing the ion implantation on the first preliminary region to obtain the predetermined well region, the first preliminary region forms the second region, so that the first device and the second device having two different turn-on voltages can be formed on the basis of the first region and the second region, thereby further ensuring better performance of the semiconductor device.
Of course, not only the second region may include the predetermined well region, but also the first region may include the predetermined well region, which is specifically manufactured according to actual requirements.
In order to further ensure that the performance of the semiconductor device is better, according to an embodiment of the present application, a first device layer is formed on a portion of the surface of the substrate, so as to obtain a first device, including: as shown in fig. 10, a first gate structure 40 is formed on a portion of an exposed surface of the oxide layer 114, the first gate structure 40 includes a first gate oxide layer 401 and a first gate 402 stacked in sequence, and a projection of the first gate structure 40 in the substrate 10 covers one of the first doped region 103 and the second doped region 105; as shown in fig. 11, a first source region 110 and a first drain region 111 are formed in the substrate on both sides of the first gate structure 40, respectively, to obtain the first device. The first gate oxide layer and the first gate are formed on the partial exposed surface of the oxide layer, the projection of the first gate structure including the first gate oxide layer and the first gate in the substrate covers one first doped region or one second doped region, and the first source region and the second drain region are formed, so that the performance of the first device can be realized, and the good performance of the first device is further ensured.
Of course, the first device may include at least a first sidewall structure and a plurality of first isolation walls instead of the first gate structure, the first source region, and the first drain region, wherein the first sidewall structure covers a sidewall of the first gate structure, and the first isolation walls are located in the substrate and are used for isolation.
In order to further ensure that the performance of the semiconductor device is better, according to another specific embodiment of the present application, a second device layer is formed on a portion of the surface of the substrate, so as to obtain a second device, including: as shown in fig. 10, a second gate structure 50 is formed on a portion of the exposed surface of the oxide layer 114, the second gate structure 50 includes a second gate oxide layer 501 and a second gate 502 stacked in sequence, and a projection of the second gate structure 50 in the substrate covers the target doping region 106; as shown in fig. 11, a second source region 112 and a second drain region 113 are formed in the substrate on both sides of the second gate structure 50, respectively, to obtain the second device. The second gate structure is formed on a part of the exposed surface of the oxide layer, the second gate structure comprises the second gate oxide layer and the second gate, the projection of the second gate structure in the substrate covers the target doping region, and the second source region and the second drain region are formed to obtain the second device, namely the doping concentration of the target doping region corresponding to the second device is low, so that the starting voltage of the second device is ensured to be low, and the performance of the second device is further ensured to be good.
Of course, the second device at least includes a second sidewall structure and a plurality of second isolation walls, where the second sidewall structure covers a sidewall of the second gate structure, and the second isolation walls are located in the substrate to perform an isolation function, rather than the second gate structure, the second source region, and the second drain region.
According to still another embodiment of the present application, the doping type with a higher doping concentration in the first predetermined process and the second predetermined process is a predetermined type, and the doping type of the substrate is different from the predetermined type. Since the doping type with higher doping concentration in the first predetermined processing and the second predetermined processing is the predetermined type, and the doping type of the substrate is different from the predetermined type, a depletion transistor with smaller turn-on voltage can be obtained, and the better performance of the semiconductor device is further ensured.
Specifically, in the case where the predetermined type is N, the substrate is a P-type substrate, and the resulting device is an N-type device; in the case where the predetermined type is P, the substrate is an N-type substrate, and the resulting device is a P-type device.
According to a specific embodiment of the present application, the first device includes a high voltage MOS transistor, and the second device includes a depletion type MOS transistor.
Specifically, the turn-on voltage of the second device is smaller than the turn-on voltage of the first device, that is, two devices with different turn-on voltages are formed on the same substrate, and of course, a plurality of devices with various turn-on voltages can be obtained by controlling the doping concentration.
In a specific embodiment, the turn-on voltage of the depletion transistor is generally required to be less than 0.2V, and in the prior art, if the manufacturing method of the semiconductor device is not used, the turn-on voltage of a directly manufactured device is generally about 0.5V, and if the doping concentration is reduced by adding a mask plate, the turn-on voltage is about 0.2V, but the manufacturing cost is high.
Fig. 12 shows a relationship between a threshold voltage and a saturation current under different process conditions, where Base is a Native MOS of the prior art, HPD + HND is a semiconductor device of the present application, HPD-1/2 is a device obtained by reducing the HPD concentration in the Native MOS of the prior art by half, and HPD-1/3 is a device obtained by reducing the HPD concentration in the Native MOS of the prior art by one third, as shown in fig. 12, the turn-on voltage of the depletion transistor obtained by the above method for manufacturing a semiconductor device of the present application is less than 0.1V, and the turn-on voltage of the device obtained by directly reducing the doping concentration in the prior art is greater than 0.2V and is proportional to the doping concentration.
The embodiment of the application also provides a semiconductor device which is manufactured by adopting any one of the methods.
In the semiconductor device of the present application, the substrate including the first region and the second region is provided, the first region includes a plurality of first sub-regions and a plurality of second sub-regions arranged at intervals, the first predetermined process, i.e., ion implantation, is performed on the plurality of first sub-regions and the plurality of second sub-regions, so that the plurality of first sub-regions and the plurality of second sub-regions form the first doped region and the preliminary doped region, respectively, and the second predetermined process, i.e., another ion implantation, is performed on the plurality of second sub-regions and the preliminary doped region, the second doping regions are formed by a plurality of second sub-regions, the target doping region is formed by the preliminary doping region, different doping types are formed in different regions in the first region due to different doping types and doping concentrations of the first predetermined process and the second predetermined process, and the two doping types in the second region can be partially neutralized by the same region in the second region through ion implantation of two different doping types and different doping concentrations, so that the obtained doping concentration of the target doping region is ensured to be smaller, the starting voltage of the second device is ensured to be smaller due to the fact that the doping concentration of the target doping region is in direct proportion to the starting voltage, namely the smaller doping concentration ensures that the starting voltage of the second device is smaller, and the problems of larger starting voltage and higher cost of a depletion transistor in the prior art are solved, the starting voltage of the semiconductor device is ensured to be smaller, and the performance of the semiconductor device is ensured to be better.
The embodiment of the present application further provides a transistor, where the transistor is manufactured by using any one of the above methods, or the above semiconductor device.
The transistor described above is manufactured by any of the above-described methods, or is the semiconductor device described above. Compared with the problems of larger starting voltage and higher cost of the depletion transistor in the prior art, the transistor of the present application, by providing the substrate including the first region and the second region, the first region including a plurality of the first sub-regions and a plurality of the second sub-regions arranged at intervals, and by first performing the first predetermined process on the plurality of the first sub-regions and the plurality of the second regions, that is, ion implantation is performed to form the first doped region and the preliminary doped region in the plurality of first sub-regions and the second region, respectively, and the second predetermined process is performed on the plurality of second sub-regions and the preliminary doped region, that is, another ion implantation is performed so that the second doped regions are formed in the plurality of second sub-regions and the target doped region is formed in the preliminary doped region, because the doping type and the doping concentration of the first predetermined processing and the second predetermined processing are different, different doping types are formed in different areas in the first area, and the same region in the second region is implanted with ions of two different doping types and different doping concentrations, so that the two doping types in the second region can be partially neutralized, and the obtained doping concentration of the target doping region is ensured to be small, and because the doping concentration of the target doping region is in direct proportion to the turn-on voltage, the smaller doping concentration ensures that the starting voltage of the second device is smaller, the problems of larger starting voltage and higher cost of a depletion transistor in the prior art are solved, the smaller starting voltage of the semiconductor device is ensured, and the better performance of the semiconductor device is ensured.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) In the method for manufacturing the semiconductor device, first, a substrate including a first region and a second region which are adjacent to each other is provided, wherein the first region includes a plurality of first sub-regions which are arranged at intervals and a plurality of second sub-regions which are arranged at intervals; then, performing a first predetermined process on the plurality of first sub-regions and the plurality of second regions, so that a first doped region is formed in the plurality of first sub-regions, and a preliminary doped region is formed in a portion of the plurality of second regions; then, performing a second predetermined process on the plurality of second sub-regions and the preliminary doping region to form a second doping region in the plurality of second sub-regions and a target doping region in the preliminary doping region, wherein the first predetermined process and the second predetermined process respectively include ion implantation, and the first predetermined process and the second predetermined process have different doping types and different doping concentrations; and finally, forming a first device layer on part of the surface of the substrate to obtain a first device, and forming a second device layer on part of the surface of the substrate to obtain a second device, wherein the projection of the first device layer in the substrate is positioned in the first doping region or the second doping region, and the projection of the second device layer in the substrate is positioned in the target doping region. Compared with the problems of larger turn-on voltage and higher cost of the depletion transistor in the prior art, the method for manufacturing the semiconductor device of the present application includes providing the substrate including the first region and the second region, wherein the first region includes a plurality of first sub-regions and a plurality of second sub-regions that are disposed at intervals, performing the first predetermined process, i.e., ion implantation, on the plurality of first sub-regions and the plurality of second regions to form the first doped region and the preliminary doped region, respectively, and performing the second predetermined process, i.e., another ion implantation, on the plurality of second sub-regions and the preliminary doped region to form the second doped region, meanwhile, the preparation doping area forms the target doping area, different doping types and doping concentrations of the first preset processing and the second preset processing are different, so that different doping types are formed in different areas in the first area, and the same area in the second area is subjected to ion implantation of two different doping types and different doping concentrations, so that the two doping types in the second area can be partially neutralized, the obtained doping concentration of the target doping area is ensured to be small, the starting voltage of the second device is ensured to be small due to the fact that the doping concentration of the target doping area is in direct proportion to the starting voltage, namely, the small doping concentration ensures that the starting voltage of the second device is small, the problems of large starting voltage and high cost of a depletion transistor in the prior art are solved, and the starting voltage of the semiconductor device is ensured to be small, the performance of the semiconductor device is ensured to be better.
2) In the semiconductor device of the present application, by providing the substrate including the first region and the second region, wherein the first region includes a plurality of first sub-regions and a plurality of second sub-regions arranged at intervals, the first predetermined process, i.e. ion implantation, is performed on the plurality of first sub-regions and the plurality of second sub-regions, so that the first doped region and the preliminary doped region are formed in the plurality of first sub-regions and the plurality of second sub-regions, respectively, and then the second predetermined process, i.e. another ion implantation, is performed on the plurality of second sub-regions and the preliminary doped region, so that the plurality of second sub-regions form the second doped region, and the preliminary doped region forms the target doped region, wherein the first predetermined process and the second predetermined process are different in doping type and doping concentration, so that different regions in the first region form different doping types, and the second predetermined process is different in doping concentration, and the doping concentration of the second region is different from each other, so that the problem of the transistor is guaranteed by the fact that the transistor is turned on voltage is higher than the transistor, and the problem of the transistor is guaranteed by the second predetermined process, and the second predetermined process is reduced in the second doped region, and the transistor is guaranteed by the second predetermined process, and the transistor is reduced in the transistor on-state of the transistor, the starting voltage of the semiconductor device is ensured to be smaller, and the performance of the semiconductor device is ensured to be better.
3) The transistor of the present application is manufactured by any one of the above methods, or is the semiconductor device described above. Compared with the problems of larger starting voltage and higher cost of the depletion transistor in the prior art, the transistor of the application, by providing the substrate including the first region and the second region, the first region including a plurality of the first sub-regions and a plurality of the second sub-regions arranged at intervals, and by first performing the first predetermined process on the plurality of the first sub-regions and the plurality of the second regions, that is, ion implantation is performed to form the first doped region and the preliminary doped region in the plurality of first sub-regions and the second region, respectively, and the second predetermined process is performed on the plurality of second sub-regions and the preliminary doped region, that is, another ion implantation is performed so that the second doped regions are formed in the plurality of second sub-regions and the target doped region is formed in the preliminary doped region, because the doping types and the doping concentrations of the first predetermined treatment and the second predetermined treatment are different, different doping types are formed in different regions in the first region, and the same region in the second region is implanted with ions of two different doping types and different doping concentrations, so that the two doping types in the second region can be partially neutralized, and the obtained doping concentration of the target doping region is ensured to be small, and because the doping concentration of the target doping region is in direct proportion to the turn-on voltage, the smaller doping concentration ensures that the starting voltage of the second device is smaller, the problems of larger starting voltage and higher cost of a depletion transistor in the prior art are solved, the smaller starting voltage of the semiconductor device is ensured, and the better performance of the semiconductor device is ensured.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. A method of fabricating a semiconductor device, the method comprising:
providing a substrate, wherein the substrate comprises a first area and a second area which are adjacent, and the first area comprises a plurality of first sub-areas arranged at intervals and a plurality of second sub-areas arranged at intervals;
performing first predetermined processing on the plurality of first sub-regions and the second region, so that the plurality of first sub-regions form a first doped region, and a part of the second region forms a preliminary doped region;
performing second predetermined processing on the plurality of second sub-regions and the preliminary doping region, so that the plurality of second sub-regions form a second doping region and the preliminary doping region forms a target doping region, wherein the first predetermined processing and the second predetermined processing respectively comprise ion implantation, the first predetermined processing and the second predetermined processing have different doping types and different doping concentrations;
forming a first device layer on a part of the surface of the substrate to obtain a first device, and forming a second device layer on a part of the surface of the substrate to obtain a second device, wherein the projection of the first device layer in the substrate is located in the first doping region or the second doping region, and the projection of the second device layer in the substrate is located in the target doping region,
providing a substrate comprising:
providing a preparation base, and carrying out thermal oxidation treatment on the preparation base to enable the preparation base to form a laminated substrate and an oxidation layer, wherein the substrate comprises the first area and the first preparation area which are adjacent;
and at least carrying out the ion implantation on the first preparation area to obtain a preset well region, so that the first preparation area forms the second area to obtain the substrate.
2. The method of claim 1, wherein performing a first predetermined process on the plurality of first sub-regions and the second region such that the plurality of first sub-regions form a first doped region and a portion of the second region forms a preliminary doped region comprises:
forming a first mask layer on the surface of the substrate;
and by taking the first mask layer as a mask, forming the first doping area by the plurality of first sub-areas through the first preset treatment, and forming the preparation doping area by part of the second area.
3. The method of claim 1, wherein performing a second predetermined process on the plurality of second sub-regions and the preliminary doped region such that the plurality of second sub-regions form a second doped region and the preliminary doped region forms a target doped region comprises:
forming a second mask layer on the surface of the substrate;
and forming the second doping area in the plurality of second sub-areas by using the second mask layer as a mask through the second preset treatment, wherein the preparation doping area forms the target doping area.
4. The method of claim 1, wherein forming a first device layer on a portion of the surface of the substrate to obtain a first device comprises:
forming a first gate structure on a part of exposed surface of the oxide layer, wherein the first gate structure comprises a first gate oxide layer and a first gate which are sequentially stacked, and the projection of the first gate structure in the substrate covers one first doped region or one second doped region;
and respectively forming a first source region and a first drain region in the substrate at two sides of the first gate structure to obtain the first device.
5. The method of claim 1, wherein forming a second device layer on a portion of the surface of the substrate, resulting in a second device, comprises:
forming a second gate structure on a part of the exposed surface of the oxide layer, wherein the second gate structure comprises a second gate oxide layer and a second gate which are sequentially stacked, and the projection of the second gate structure in the substrate covers the target doping region;
and respectively forming a second source region and a second drain region in the substrate at two sides of the second gate structure to obtain the second device.
6. The method according to any one of claims 1 to 5, wherein the doping type having a higher doping concentration in the first predetermined process and the second predetermined process is a predetermined type, and the doping type of the substrate is different from the predetermined type.
7. The method of any of claims 1-5, wherein the first device comprises a high voltage MOS transistor and the second device comprises a depletion MOS transistor.
8. A semiconductor device manufactured by the method according to any one of claims 1 to 7.
9. A transistor produced by the method of any one of claims 1 to 7 or the semiconductor device of claim 8.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004297030A (en) * | 2003-02-06 | 2004-10-21 | Ricoh Co Ltd | Semiconductor device, method of manufacturing thereof, and application device thereof |
| JP2016164967A (en) * | 2015-02-25 | 2016-09-08 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor integrated circuit device and method of manufacturing the same |
| CN106548943A (en) * | 2015-09-23 | 2017-03-29 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN108847423A (en) * | 2018-05-30 | 2018-11-20 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor devices and its manufacturing method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4976624B2 (en) * | 2000-09-01 | 2012-07-18 | セイコーインスツル株式会社 | Complementary MOS semiconductor device and manufacturing method thereof |
| US6849492B2 (en) * | 2002-07-08 | 2005-02-01 | Micron Technology, Inc. | Method for forming standard voltage threshold and low voltage threshold MOSFET devices |
| US7005354B2 (en) * | 2003-09-23 | 2006-02-28 | Texas Instruments Incorporated | Depletion drain-extended MOS transistors and methods for making the same |
| KR101175228B1 (en) * | 2009-12-04 | 2012-08-21 | 매그나칩 반도체 유한회사 | Semiconductor device |
| TWI621273B (en) * | 2017-04-27 | 2018-04-11 | 立錡科技股份有限公司 | High Voltage Depletion Mode MOS Device with Adjustable Threshold Voltage and Manufacturing Method Thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004297030A (en) * | 2003-02-06 | 2004-10-21 | Ricoh Co Ltd | Semiconductor device, method of manufacturing thereof, and application device thereof |
| JP2016164967A (en) * | 2015-02-25 | 2016-09-08 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor integrated circuit device and method of manufacturing the same |
| CN106548943A (en) * | 2015-09-23 | 2017-03-29 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN108847423A (en) * | 2018-05-30 | 2018-11-20 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor devices and its manufacturing method |
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