CN115529711A - Ion accelerator standardized power supply controller and dynamic local reconfigurable method thereof - Google Patents

Abstract

The invention relates to an ion accelerator standardized power supply controller and a dynamic local reconfigurable method thereof, wherein the method comprises the following steps: the main board is provided with a communication interface for the communication between the power supply controller and other equipment; the standardized custom interface is used for connecting the mainboard with the daughter boards with different functions, the WR daughter board and the power supply module; the main control board interface is used for collecting all controllable signals of the main board to the main control board; the main control board is provided with an ARM processor and an FPGA; an embedded EPICS application program is configured in the ARM processor and used for reading and writing the FPGA, directly publishing relevant variables in the main control board into standard PV variables supported by EPICS, and then communicating with an upper computer; a modularized bottom layer regulator frame is configured in the FPGA, and monitoring and control of different types of accelerator power supply main circuits are realized by carrying out dynamic local reconfiguration on corresponding modules. The invention can be widely applied to the field of ion accelerators.

Description

Ion accelerator standardized power supply controller and dynamic local reconfigurable method thereof

Technical Field

The invention relates to a standardized power supply controller for a magnet power supply in an ion accelerator and a dynamic local reconfigurable method thereof, belonging to the field of ion accelerators.

Background

An ion accelerator is an accelerating device for accelerating ions through a high-frequency electric field on a certain linear or circular track, and makes charged particles do linear or periodic motion in a magnetic field and continuously accelerate in the electric field, so that the ions obtain a high speed. In order to restrain the ions in a certain orbit, a restraining magnetic field is generated by exciting current generated by a plurality of magnet power supplies, and a certain orbit is provided for the ion beam current. There are also occasions where voltage sources are required, such as power sources, electrostatic deflection plates, magnet power supply pre-stage voltage sources, force excitation voltage sources, etc. Various types of power supplies can be classified according to different characteristics, and generally, a large-sized ion accelerator generally consists of dozens of types of power supplies and hundreds of specifications of power supplies.

The accelerator magnet power source is one of the most diverse types and specifications of current sources. The existing magnet power supply is digitalized, and due to the fact that the working principle and the control mode of different types of magnet power supplies are different, the embedded controller hardware of the magnet power supply and control programs in the embedded controller hardware are different in type and version, communication interfaces and control protocols are greatly different, even the situation of multi-level protocol conversion exists, the reliability of communication is low, and the workload of program modification and upgrading is large.

The core function of the magnetic iron power supply controller is to control the main circuit and related hardware in the power supply and realize the function and index of the magnetic iron power supply. Because the types and specifications of the accelerator magnet power supplies are the most, the working principles and circuit structures of different magnet power supplies are completely different, and the current regulators in the magnet power supply controllers are also greatly different. At present, the design based on an FPGA regulator is based on a programming mode of interconnection of code function modules, different PWM strategies are adopted for different circuit topologies, and links such as filtering, current regulation strategies, current output modes and the like are possibly different. These functional modules are currently code-based, and the modification, replacement, debugging and upgrading of the modules are manually completed by programmers from the code level. Each time the local function is adjusted or optimized, the local function needs to be compiled and debugged globally, which takes a long time to complete. If new functionality is to be added, the entire program structure is adjusted, sometimes introducing new errors. In a word, the programming mode is that programming, compiling, simulating, downloading, debugging, testing and other links are required to be carried out every time when a digit is modified, and the whole process is required to be completed even if the digit is modified, so that the time consumption is long. It can be seen that the programming mode of this kind of module interconnection is relatively fixed, lacks flexibility, and the technical staff work load is big, and is inefficient, also makes mistakes easily. The present compiling and debugging mode of program does not support isolation of local problems. This mode affects the efficiency of controller software design, maintenance and upgrade.

Parameter monitoring management of accelerator magnet power supply is also a very important aspect. The existing accelerator magnetic iron power controller basically adopts an embedded microcontroller to complete the transmission of communication parameters. Most of them are based on custom protocols to deliver parameters. The communication protocol has limited programmable resources, limited number of processing threads and slow response speed, is usually single connection, and does not support a multi-connection and connection management mechanism. The parameters of the magnetoferroelectricity controller are often provided with a plurality of sets after the power supply is debugged, and meanwhile, the parameters of the magnetoelectricity controller can be monitored and recorded at a plurality of terminals (a plurality of local terminals and a plurality of remote terminals), so that the requirements on the parameter processing and responding capability of the magnetoelectricity controller of the accelerator are difficult to fulfill at present. Therefore, with the increasing demand of the new generation accelerator for power performance in the future, real-time monitoring, storage and management of power parameters in multiple interfaces is an important problem to be solved by the power controller.

Because the updating of the circuit topology and the power device is relatively slow, the hardware upgrading can not be considered for a long time, and therefore, the flexibility and the expansibility of a hardware platform are not considered by most power controller hardware. The hardware of the accelerator power supply controller is relatively stable, and most of them adopt a hardware scheme. However, with the development of accelerator technology, the demand of new generation accelerators on power supply is higher and higher, new demands and new technologies are continuously appeared in the future, and simultaneously, hardware cannot meet the demands and applications, so that how to design hardware circuits, hardware layouts and interfaces of the controller to increase the flexibility and expansibility of the hardware needs to be considered. Generally, the core board, the ADC board, the DAC board, and the PWM interface may have different requirements for different power supplies, and if one of the solutions is adopted, waste may be caused, or the whole hardware architecture may be adjusted because the local performance cannot meet the requirements. In addition, with the continuous improvement of the accelerator on the power performance, the throughput and the processing capability of the communication interface of the existing data cannot meet the requirements, and the communication interface needs to be upgraded to meet the future application. How to perform reliable and real-time cascade expansion on the basis of the existing hardware scheme is also an important problem to be solved by the controller.

At present, the inside of an accelerator power supply has no time reference, if the inside of a power supply controller needs synchronization and relative time, the synchronization and the relative time are realized by an external trigger and a counter counting mode, and the synchronization of the trigger time precision is lower. If a time service system with higher synchronization precision needs to be supported, a power supply controller needs to design and add a support board card and an interface for the high-precision time service systems. Through the board cards and the interfaces, the power supply controller can obtain an absolute and accurate time tag of the system, and can print an accurate time tag on the data of the accelerator power supply, so that more accurate synchronization and tag functions are provided. The performance improvement of the future generation of accelerators inevitably requires that the power supply has more accurate time synchronism, and meanwhile, the data can be provided with accurate time tags so as to facilitate the system analysis, prediction and protection of the normal and abnormal states of the power supply and the related equipment thereof.

In addition, with the development of science and technology, the fields of medical ion accelerators, nuclear waste upgrading treatment, isotope production and the like put higher requirements on the long-term operation reliability of a new-generation high-power high-current strong accelerator power supply. The method for improving the reliability of the accelerator power supply system by increasing the reliability of a single power supply is limited because all power supplies of the accelerator power supply system generally need to work in a certain state at the same time to ensure the normal operation of the accelerator, which is equivalent to the series work of all power supplies, and even if one power supply deviates from the set output value, the system is also influenced. The reliability increase of a single power supply is limited, and thus conventional power supply controllers tend to ignore how the reliability of the power supply can be better supported and increased. The parallel connection of module power supplies is known as a main means for improving the reliability, flexible change and combination of the existing accelerator power supplies, and the existing accelerator power supply controller usually only focuses on the adjustment and control of the current of a single power supply and lacks the support for the serial and parallel connection, linkage and bus of the module power supplies. In addition, the access, exit, abnormality and service life of the module power supply can be combined into a combined power supply with higher reliability only by the support of a corresponding management strategy of the controller. Therefore, for an accelerator power supply with high reliability requirement, a controller needs a control interface and a management mechanism for series and parallel connection of module power supplies.

In summary, in the field of ion accelerators, a universal, unified and standardized power supply controller and a software design method thereof are lacking at present, so that the quality and reliability of the power supply controller of the accelerator are improved, the efficiency of design, debugging, maintenance and upgrading of the power supply controller is improved, the cost is reduced, the universality, flexibility and expandability of the power supply controller are realized, and the requirements of future new generation accelerators (CiADS, HIAF, isotopes, super-heavy cores, medical accelerators, superconducting accelerators and the like) on high-quality and high-reliability accelerator power supplies are met.

Disclosure of Invention

In view of the above problems, the present invention provides a standardized, universal, and unified power supply controller for an ion accelerator and a dynamic local reconfigurable method thereof, which realizes the universality and unification of hardware and software of the power supply controller for the ion accelerator and the standardization of the power supply controller in the field of the ion accelerator.

In order to realize the purpose, the invention adopts the following technical scheme:

in a first aspect, the present invention provides an ion accelerator normalized power supply controller comprising: the system comprises a case, a main board, a main control board and a plurality of sub-boards, wherein the main board, the main control board and the sub-boards are arranged in the case; various standardized interfaces are arranged on the main board, and comprise a communication interface, a standardized user-defined interface and a main control board interface; the communication interface is used for realizing communication between the power supply controller and the inside and outside equipment of the accelerator power supply; the standardized custom interface is used for realizing the connection between the main board and the daughter boards with different functions and providing a power interface for connecting a power module; the main control board interface is used for realizing the connection between the main control board and the main board and collecting all controllable signals received by the main board to the main control board; an ARM processor and an FPGA are arranged in the main control board; an embedded EPICS application program is configured in the ARM processor and used for reading and writing the FPGA, issuing related variables in the main control board into standard PV variables supported by EPICS, and then communicating with an upper computer; and a modularized bottom-layer regulator frame is configured in the FPGA, and monitoring and control of accelerator power main circuits of different types are realized by performing dynamic local reconfiguration on corresponding modules in the modularized bottom-layer regulator frame.

Further, the development framework of the embedded EPICS application program is a development framework based on equipment support, and the equipment support comprises 11 standard equipment supports including reference waveform control, analog input, analog output, quench protection, adjustment parameter reading and writing, current and voltage reading and writing protection, synchronization and triggering, IO reading and writing, state reading and writing, liquid crystal screen reading and writing and module power supply serial-parallel connection.

Further, the modular underlying regulator frame comprises an ADC module for receiving a feedback current or voltage signal, a filtering module, a protection module, an algorithm module, and a pulse modulation module; the filtering module is used for filtering the current or voltage signal received by the ADC module and sending the current or voltage signal to the protection module and the algorithm module; the protection module and the algorithm module process the filtered signals and then send the processed signals to the pulse modulation module; the pulse modulation module generates a PWM signal and outputs the PWM signal to a main circuit of an accelerator power supply.

Further, the daughter board comprises at least one of a low-speed AD daughter board, a high-speed DA daughter board, an IO daughter board, a PWM daughter board and a WR daughter board; the low-speed AD sub-board and the high-speed AD sub-board are used for collecting feedback current and voltage signals inside the accelerator power supply with different sampling speeds, converting the feedback current and voltage signals into digital signals and sending the digital signals to the main control board; the high-speed DA sub-board is used for converting data generated inside the main control board into analog signals to be output, and the analog signals are used for observing or serving as a given reference of a quick-response analog power supply; the IO daughter board is used for monitoring various state signals and switching signals in the accelerator power supply; the PWM sub-board is used for converting the PWM signal sent by the main control board into a required signal and then sending the required signal to a driving circuit of the accelerator power supply main circuit; the WR sub-board supports a white rabbit time service system and is used for time synchronization of the power supply controller.

Further, the communication interfaces comprise 1 gigabit Ethernet electrical interface, 1 gigabit Ethernet SFP interface, 2 WR board SFP interfaces, 2 gigabit SFP + interfaces, 2 USB interfaces, 1 CAN interface, 1 485 interface, 1 serial port, 1 main control board debugging interface, 1 WR board debugging interface, 2 light receiving ports, 2 light output interfaces, 1 debugging JTAG interface, system clock/reset interface, 1 LCD interface and 2 SMA interfaces, and each communication interface is used for connecting power supply internal and external equipment;

the standardized custom interfaces comprise 3 40-pin interfaces, 2 60-pin interfaces and 1 power supply interface; 3 40-pin interfaces for connecting and combining daughter boards with different functions through 40-pin connectors; 2 60-pin interfaces are used for connecting the WR daughter card; the power interface is used for being connected with the power module through the power connector.

Furthermore, the case comprises a front panel, a rear panel and a top cover plate, wherein the front panel and the top cover plate are detachably arranged on the rear panel;

the front panel is used for providing a maintenance interface, and comprises: at least one of a reset hole, 4 power status lamps, 2 USB external interfaces, 2 Type _ C debugging external interfaces, 1 kilomega Ethernet external interface and an LCD external interface; the reset hole, the USB external interface, the Type _ C debugging external interface, the gigabit Ethernet electric external interface and the LCD external interface are respectively used as a reset interface, a USB interface, a main control board debugging interface, a WR board debugging interface, a gigabit Ethernet electric interface and a leading-out port of an LCD interface on the main board;

the back panel is used for the power supply operation work interface, includes: 24 PWM optical IO external interfaces in an SMA form, 1 24-pin J30J electric external interface, 1 CAN external interface, 1 RS485/422 external interface, 1 RS232/IIC external interface, 6 SMA electric signal external interfaces, 2 WR board SFP external interfaces, 4 SMA optical signal external interfaces, 1 gigabit Ethernet SFP external interface, 2 gigabit SFP + external interfaces, 1 220V power supply interface with a switch and at least one of 1 grounding terminal; the 24 PWM optical IO external interfaces in the SMA form are used as leading-out interfaces of the 2 PWM sub-boards; the 1 24-pin J30J electric external interface is used as an outlet of the IO daughter board; the 1 CAN external interface is used as an outlet of the CAN interface and is used for managing a power supply formed by connecting module power supplies in series and parallel; the RS485/422 external interface is used as an outlet of the 485 interface and is used for communicating with an independent state control panel in the power supply; the RS232/IIC external interface is used as a leading-out port of a serial port and is used for communicating with an independent liquid crystal display inside the power supply; any 2 of the 6 SMA electrical signal external interfaces are used as leading-out ports of the 2 SMA interfaces on the mainboard and are used for receiving an electrical trigger signal and an external clock signal, and the remaining 4 electrical signal external interfaces are used as two analog signal leading-out ports of the high-speed AD sub-board and the high-speed DA sub-board and are used for receiving high-speed ADC and high-speed DAC signals; the 2 WR board SFP external interfaces are used as leading-out interfaces of the WR board SFP interfaces; the 4 SMA optical signal ports are used as leading-out ports of 2 optical output interfaces and 2 optical receiving interfaces on the mainboard and are used for optical port communication of 100 Mbps; the 1 gigabit Ethernet SFP external interface and the 2 gigabit Ethernet SFP + external interface are respectively used as leading-out interfaces of the 1 gigabit Ethernet SFP interface and the 2 gigabit SFP + interface on the mainboard.

Further, the power module is used for providing a direct current power supply required by the mainboard, the direct current power supply provides at least one output voltage of +/-12V, + 5V and +/-3.3V, and 220V alternating current is adopted for supplying power for different types of accelerator power supplies.

In a second aspect, the present invention provides a method for dynamically and locally reconfiguring a normalized power supply controller of an ion accelerator, comprising the steps of:

configuring a standardized power controller of an ion accelerator, and respectively configuring an embedded EPICS application program and a modular bottom-layer regulator framework in an ARM processor and an FPGA of a main control board;

according to the actual functional requirements, carrying out dynamic local reconfiguration on corresponding modules in a modularized bottom layer regulator frame of the FPGA, and simultaneously carrying out corresponding combination adjustment on daughter boards connected with a mainboard;

when the system runs or starts, the embedded EPICS application program in the ARM processor reads and writes the FPGA, and after relevant variables in the main control board are issued into PV variables supported by standard EPICS, the FPGA communicates with an upper computer to realize monitoring and control of different types of accelerator power supply main circuits.

Further, the workflow of the embedded EPICS application program comprises the following steps:

guiding a Linux system in an ARM processor to start and initializing;

starting an IOC main program in the embedded EPICS application program to finish the running of the self-starting script;

after the IOC main program is started, calling an hpu _16.Db file to issue all PV variables in the file, calling equipment support programs related to all PV variables to set a scanning period to run, and controlling corresponding data, parameters and states in the FPGA;

and the ARM processor reads or writes PV variable data from the FPGA and synchronizes with the upper computer.

Further, the method for dynamically and partially reconfiguring the corresponding modules in the framework of the modular underlying regulator in the FPGA processor according to the actual functional requirements includes:

2.1 Bit file full. Bit of the framework of the modular bottom-layer regulator and partial bit file partial. Bit corresponding to each reconfiguration module are generated under the reconfiguration mode;

2.2 Based on full.bit and each partial.bit file, generating corresponding bin files full.bin and partial.bin, and transferring the obtained two bin files to a User _ Application User space of the embedded Linux;

2.3 Writing a first script file for downloading full.bin files to the reconfigurable area in the FPGA _ PL terminal, wherein the first script file comprises all the steps of downloading the contents in the full.bin files to the reconfigurable area in the FPGA _ PL terminal through a PCAP mechanism;

2.4 Power-up power supply controller;

2.5 Enter Linux and run the first script file, look over the performance index of power under the default configuration;

2.6 Compiling a second script file for downloading a part.bin file of the specified reconfigurable module to the reconfiguration region of the FPGA _ PL terminal according to the dynamic reconfiguration requirement;

2.7 Running a second script file to check the power performance index of the second script file;

2.8 ) repeating the steps 2.6) -2.7) to realize the dynamic replacement of other modules.

Due to the adoption of the technical scheme, the invention has the following advantages: the invention solves the problems caused by multiple types and multiple software versions of controllers in the power supply of the accelerator by arranging various standardized interfaces on the main board, connecting different daughter boards in a combined way and reconfiguring the dynamic layout of corresponding modules in the bottom layer regulator frame in the main control board, realizes the universality and unification of the software and hardware of the power supply controller of the ion accelerator, and provides a power supply controller standardization method in the field of accelerators. For an accelerator power supply controller, the invention can effectively simplify the design, shorten the development period, improve the debugging, maintenance and upgrading efficiency and ensure the quality and reliability of the power supply controller. The invention can be widely applied to the fields of linear accelerators, annular accelerators and cyclotron plasma accelerators; but also can be widely applied to accelerator application devices such as medical devices, isotope production devices, space irradiation devices, material irradiation devices, nuclear waste treatment devices, accelerator research devices and the like; the method can also be applied to future new generation superconducting accelerators and new generation high-power strong-current accelerator devices. Therefore, the invention can be widely applied to the field of ion accelerators.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Like reference numerals refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a diagram of a standardized power controller hardware architecture provided by an embodiment of the present invention;

fig. 2 is a structure diagram of a main control board of a standardized power controller provided in an embodiment of the present invention;

fig. 3a to fig. 3f are structural diagrams of a standardized power controller electronic board according to an embodiment of the present invention, where fig. 3a is a PWM1 board, fig. 3b is a PWM2 board, fig. 3c is an IO board, fig. 3d is a low-speed AD board, fig. 3e is a high-speed AD board, and fig. 3f is a high-speed DA board;

fig. 4a to fig. 4c are structural diagrams of a chassis of a standardized power controller according to an embodiment of the present invention, where fig. 4a is a front panel of the chassis, fig. 4b is a top view of the chassis, and fig. 4c is a rear panel of the chassis;

FIG. 5 is a flowchart of the embedded EPICS software of the standardized power controller provided by the embodiment of the invention;

FIG. 6 is a block diagram of a standardized power reconfiguration regulator provided by an embodiment of the present invention;

the labels in the figure are as follows:

1-4, a connector; 5. a handle; 6. a reset hole; 7. a power status light; 8. a USB external interface; 9. debugging an external interface by Type _ C; 10. kilomega power Ethernet external interface; 11. an LCD external interface; 12. mounting holes; 13. 24 PWM optical IO external interfaces in the form of SMA; 14. a 24-pin J30J electrical external interface; 15. a CAN external interface; 16. RS485/422 external interface; 17. an RS232/IIC external interface; 18. an electrical signal external interface in the form of SMA; 19. WR board SFP external interface; 20. an SMA optical signal external interface; 21. gigabit Ethernet SFP external interface; 22. ten thousand SFP + external interface; 23. a 220V power supply port with a switch; 24. and a ground terminal.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the description of the embodiments of the invention given above, are within the scope of protection of the invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

Due to the universality, uniformity, flexibility and expandability of the hardware and software design of the power supply controller of the ion accelerator, a standardized and dynamically partially reconfigured power supply controller of the ion accelerator is formed, and related contents are introduced below, so that the contents of the invention can be more clearly understood by those skilled in the art.

Accelerator magnet power supplies typically include hundreds or thousands of power supplies, which are numerous in variety and specification. The hardware, software and communication protocols of these kinds of power controllers lack generality and uniformity, so that special manpower and energy are required to be invested in design, debugging, maintenance and upgrading of different power supplies, the efficiency is low, and the personnel cost is high. In order to achieve the uniformity and flexibility of the accelerator power controller and achieve the purpose of standardization, the power controller needs to consider from two aspects of hardware and software.

In terms of hardware, the required hardware functions are counted and summarized aiming at all current types of power supplies of the ion accelerator, and the flexibility and the expansibility of the hardware of the accelerator power supply controller are improved by adding various standardized interfaces with verified reliability on a high-performance hardware platform. The standardized interface is utilized to divide the original integrated hardware design into different daughter boards, and the requirements of the accelerator power supply on different hardware functions and interfaces are met by replacing or adding the daughter boards with the standardized interface, so that the recombination and the upgrade of the hardware functions are facilitated. The standardized interface is designed to meet the requirements of extension of functions of the daughter board, and particularly, the type of power supply, the number of input and output ports and the bandwidth are enough.

In terms of software, because various types and versions of control programs exist in the accelerator power supply controller, the communication interface and the control protocol have large difference, and even a multi-level protocol conversion condition exists, the communication reliability is low, and the modification and upgrading workload of the programs is large. In order to unify communication protocols and improve the flexibility and expansibility of software, the invention adopts embedded EPICS (experimental physics and industrial control system) as standard application layer software of an accelerator power supply internal controller. EPICS is based on the powerful programming environment of embedded Linux, the communication layer of the EPICS is packaged and unified through a Channel Access (CA) mechanism, the response speed of communication is also suitable for monitoring an accelerator power supply, and the programming structure is unified and convenient. The rich programming resources and the programming ecology of the system are utilized to program an embedded IOC (input output controller), and the software functions are added and upgraded in a mode of PV (process variable) variables and equipment support. Meanwhile, the required control quantity can be directly issued to be a PV variable of the accelerator field standard, and flexible and reliable monitoring of a plurality of terminals is facilitated. Therefore, the universality and the unification of the application layer programs of the internal controller of the power supply are realized.

The design of a regulator on the power supply controller of the accelerator at present comprises the design based on a function module of FPGA codes, different PWM (pulse width modulation) strategies are adopted for the topologies of different circuits, and links such as filtering, a current regulation strategy, a current output mode and the like are possibly different. In addition, some modules have dispersed functions, and some modules have no power supply. For example, the functions of synchronization and triggering, the serial-parallel management function of module power supplies, and the like, change, increase, decrease, and recombination of these functional code modules need to be modified at the code level, and also need to be compiled and debugged integrally, which is time-consuming, error-prone, low in efficiency, and easy to introduce new problems. In order to solve the problems, the invention uses an internal Processor Configuration Access Port (PCAP) and EPICS application layer software supported by a platform to start the process of realizing the dynamic local reconfiguration of the FPGA functional module. The regulator in the FPGA can be subjected to modular split design, wherein the regulator comprises an ADC driving module, an algorithm, a filter, PWM, synchronization, triggering and other modules with frequently changed requirements, the modules and interfaces thereof are standardized so as to be convenient for replacement and recombination and generate regulators and control strategies aiming at different power supplies, and therefore dynamic local reconfiguration of the internal controller of the power supply is realized. The dynamic local reconfiguration method is introduced, so that the flexibility of the internal logic design of the FPGA is increased, the compiling time is saved, the repeated use of the existing functional module is facilitated, and the efficiency is improved. The technical breakthrough that one power supply controller can be immediately changed into another power supply controller through software setting is realized, and the unification and the universality of the power supply controllers of the accelerators are also thoroughly realized.

Example 1

As shown in fig. 1, the present embodiment provides an ion accelerator standardized power supply controller, which includes: the main control board is arranged in the case, and the main control board is arranged in the case. The main board integrates and interconnects the main control board, the sub-boards and the power module, so that reliable interaction of high-speed data between the main control board and the sub-boards is ensured, and the key of the integrity of power supply of each interface is ensured. Specifically, various standardized interfaces are arranged on the main board, including a communication interface, a standardized custom interface and a main control board interface; the communication interface is used for realizing communication between the controller and other equipment inside and outside the power supply; the standardized custom interface is used for realizing the connection between the main board and the daughter boards with different functions and providing a power interface for connecting a power module; the main control board interface is used for realizing the connection between a main control board arranged on the main board and various standardized interfaces on the main board and simultaneously collecting all controllable signals of the main board to the main control board; an ARM processor and an FPGA are arranged in the main control board; an embedded EPICS application program is configured in the ARM processor and used for reading and writing the FPGA, directly publishing the quantity to be controlled by a network in the main control board into a standard PV variable supported by the EPICS, and then communicating with an upper computer; and a modularized bottom-layer regulator frame is configured in the FPGA, and monitoring and control of the accelerator power supply main circuits of different types are realized by dynamically and locally reconfiguring corresponding modules in the modularized bottom-layer regulator frame.

Preferably, the mainboard adopts ZYNQ series FPGA of Xilinx company as a main control chip.

Preferably, the communication interface includes 1 gigabit ethernet electrical interface (RJ-45 interface in the figure), 1 gigabit ethernet SFP interface (SFP interface 1 in the figure), 2 WR board SFP interfaces supporting the high-precision white rabbit timing system, 2 gigabit SFP + interfaces (SFP +1 and SFP +2 in the figure), 2 USB interfaces (UART-MUSB and PS _ USB3.0 in the figure), 1 CAN interface (PS _ CAN2.0 in the figure), 1 485 (or 422) interface (PS-UART-485 in the figure), 1 serial port (RS 232 or IIC) (PS-IIC/RS 232 in the figure), 1 main control board debugging interface (UART 1 in the figure), 1 WR board debugging interface (WR 2 in the figure), 2-way optical receiving interface (2 × HFBR2406 in the figure), 2-way optical output interface (1 × br in the figure), 1 debugging interface, JTAG clock/reset interface, 1 SMA interface, and 2-way optical line interface (HFBR) in the figure.

Preferably, the standardized custom interface comprises 3 40 pin interfaces, 2 60 pin interfaces and 1 power interface. The 3 40-pin interfaces are used for connecting and combining different daughter boards through 40-pin connectors so as to improve the flexibility and expansibility of the control board; 2 60-pin interfaces are used for connecting a WR daughter board supporting a high-precision white rabbit timing system; the power interface is used for connecting the power module through the power connector. The 40-pin interface connector comprises a plurality of high-speed parallel signal wires, 32 IO high-speed digital signals and 8 power supply ends, the requirements of the port are relatively low, but the interface design and the connector selection at least meet the bandwidth of 100MHz and the long-term reliable connection requirement. The standardized interface on the mainboard comprises a large number of high-speed parallel signal lines and high-speed differential lines, and is designed according to the high-speed PCB design specification.

Due to the fact that the types and specifications of accelerator power supplies are various, indexes and control functions of current are also diversified, and if a unified controller hardware platform is adopted, a plurality of universal standard interfaces need to be supported. In addition, there are some functional daughter boards, and usually, the functions of the daughter boards are very many, and there are often upgrades and changes, and in order to ensure the uniformity and versatility of the daughter boards, standardized definitions are also usually required.

Preferably, as shown in fig. 2, the main control board constitutes a minimum microprocessor system, and at the same time, all standard interfaces of the backplane are supported, and the software and soft core programmability are provided at the same time; the functions of high-speed data transmission, digital signal processing, control algorithm, data storage, operation and integration of the management daughter board and the like are realized.

Specifically, the main control board is a control center of the whole controller, and is used for receiving and transmitting all standardized interface data, and simultaneously receiving and transmitting data of all sub-boards in real time. Wherein, the communication interface of the standard communication protocol comprises: SFP Ethernet interface (except SPF of WR board), gigabit Ethernet electrical interface, CAN interface, RS485/422 interface, RS232/IIC interface, USB interface and SD card are all controlled by standard peripheral of ARM; and for some customized communication ports, including an SFP + interface, an optical output interface, an optical receiving interface, an LED, CLK and TRIG signals, a 40-pin interface and a 60-pin interface are all realized by an FPGA (PL) part. The FPGA processes signals which are high in real-time performance and relevant to user definition.

Preferably, the embedded EPICS application program configured in the ARM processor is a general embedded architecture software for controlling various types of accelerator magnet power supplies and issuing required control quantity as PV variable. The software system is a set of application software based on embedded EPICS. The software is based on an embedded Linux system, supports multi-language programming, and has rich programming resources and programming ecology; meanwhile, the dynamic local reconfiguration function is supported, and the FPGA bottom-layer regulator can be flexibly and quickly replaced or recombined through EPICS software, wherein different regulation control strategies are generated by replacing and recombining an ADC driving module, an algorithm, a filter, PWM and other modules; the software is convenient to upgrade and maintain, short in development period and high in universality, required control quantity can be directly issued to be a standard PV variable in the field of accelerators, and a plurality of terminals can conveniently monitor flexibly and reliably. The application program starts from the angle of universality, unification and flexibility of the accelerator power supply, provides the standard control function of the accelerator power supply, and realizes a new technology of controlling almost all types of accelerator magnet power supplies by a set of software.

The development framework of the embedded EPICS application program configured in the ARM processor is a development framework based on equipment support, and is adapted to different accelerator power supply types by adding or modifying the mode of the equipment support, wherein the equipment support comprises 11 standard equipment supports of reference waveform control, analog input, analog output, quench protection, adjustment parameter reading and writing, current and voltage reading and writing protection, synchronization and triggering, IO reading and writing, state reading and writing, liquid crystal display reading and writing and module power supply.

The modular bottom-layer regulator framework configured in the FPGA comprises an ADC module, a filtering module, a protection module, an algorithm module and a pulse modulation module, wherein the ADC module is used for receiving a feedback current or voltage signal; the filtering module is used for filtering the signals received by the ADC module and sending the signals to the protection module and the algorithm module; the protection module and the algorithm module process the filtered signals and send the processed signals to the pulse modulation module; the pulse modulation module generates a PWM signal and outputs the PWM signal to a main circuit of a power supply. By updating and replacing the specific implementation of some or all of the modules within the modular underlying regulator frame,

preferably, the main control board is communicated with the main board through 4 main control board connectors and 4 120-pin connectors, so that the communication and distribution of high-speed digital signals and power supplies are mainly realized, and the interface can be determined as a standardized main control board interface. The main control board is also a sub-board, and the sub-board connection mode is convenient for changing and upgrading the main control board on the premise that the main board is not changed. The design of the main board is compatible with the commercial main control board as much as possible, so that early verification is facilitated, meanwhile, the commercial main control board with higher cost performance can be directly purchased on the premise that conditions allow, and the project development period is shortened. In addition, the main control board generates heat greatly, and a passive heat dissipation scheme is adopted, and a fan can be installed on the main control board for heat dissipation.

Preferably, the daughter board is designed independently according to the actual requirement of the accelerator power supply, the hardware function that needs to be changed frequently is changed, and the daughter boards in this embodiment all support standardized 40-pin interfaces.

As shown in fig. 3a to 3f, in this embodiment, the daughter boards mainly include a low-speed AD daughter board, a high-speed DA daughter board, an IO daughter board, a PWM daughter board, and the like, where the low-speed AD daughter board and the high-speed AD daughter board are mainly used to collect feedback current and voltage signals of accelerator power supplies with different sampling speeds, convert the feedback current and voltage signals into digital signals, and send the digital signals to the main control board; the high-speed DA sub-board is mainly used for converting data generated inside the main control board into analog signals to be output, and is used for observing or serving as a given reference of a quick-response analog power supply; the IO daughter board is mainly used for monitoring various state signals and control of switch signals in the accelerator power supply; the PWM sub-board is mainly used for converting PWM signals sent by the main control board into required signals and then sending the signals to a driving circuit of the main circuit.

Preferably, the AD is used as a single daughter board because different power supplies have different functional performance requirements for the AD, and the cost and price of the AD are different, and the AD is designed as a daughter board to adapt to different accelerator power supply requirements. The low-speed AD daughter board is mainly used for collecting the feedback current and voltage of the accelerator power supply, is a key link for ensuring the performance index of the power supply, and is designed to meet the requirements of higher collection precision and stability. In high precision, temperature stability needs to be considered so as to meet the requirement of the precision index of the accelerator power supply.

Specifically, as shown in fig. 3d, the low-speed AD daughter board includes a 40-pin standard daughter board interface, a level conversion circuit, a low-speed AD acquisition chip, a reference source, and a front-end conditioning circuit. The low-speed AD acquisition chip is used for carrying out high-precision sampling on current and voltage under a reference source signal, and 1Msps can be adopted for being compatible with most power supply sampling rates; the level conversion circuit is used for carrying out digital signal isolation on the sampling signal of the low-speed AD acquisition chip so as to protect the main control panel; the front-end conditioning circuit is used for low-pass filtering to improve the acquisition precision, and can adopt passive two-stage filtering or an overcurrent protection circuit.

More preferably, because the current and voltage to be collected in the accelerator power supply are more, 8 paths of 18bit high-precision ADCs can be generally adopted in the low-speed AD collection chip, and correspondingly, 8 paths of conditioning circuits are adopted in the front-end conditioning circuit. For more high-precision acquisition requirements, a plurality of low-speed AD daughter boards can be inserted into the mainboard for realization.

Preferably, the high speed AD daughter board is used as a separate daughter board because a portion of the accelerator power supply requires fast analog signal acquisition, analysis, and processing. The high-speed AD daughter board is mainly used for collecting feedback current and voltage of an accelerator power supply with a higher speed, is a key link for power supply performance index analysis and equipment protection, and is designed to meet requirements of bandwidth, reliability and the like. In high-speed occasions, the distribution parameters of the circuit also need to be considered so as to meet the requirements of rapidity and synchronism of the accelerator for acquiring the analog signals.

Specifically, as shown in fig. 3e, the high-speed AD daughter board is similar to the low-speed AD daughter board, and unlike the low-speed AD daughter board, the fast current and voltage that needs to be collected in one accelerator power supply is usually less, so a 2-way 14-bit high-speed ADC can be generally used in the high-speed AD daughter board, and 65Msps can be used for compatibility with most power supply sampling rates. Accordingly, the front-end conditioning circuit employs 2-way circuit conditioning. In a similar way, for more high-speed acquisition demands, a plurality of high-speed AD daughter boards can be inserted into the bottom plate to realize the acquisition.

The high speed DA daughter board is preferably used as a separate daughter board because the accelerator power supply has a need for internal data observation, as well as the need to control the output current of some fast response linear power supplies by outputting analog signals. The high-speed DA sub-board is a key element for debugging the performance of the digital power supply, is also used as a given generation unit of the accelerator fast response analog power supply, and is mainly used for converting data inside the accelerator power supply controller into signals and then observing or serving as a given reference of the fast response analog power supply. The design of the high-speed DA daughter board usually needs to meet higher sampling rate and stability, and in a high-speed situation, the distribution parameters of the circuit also need to be considered so as to meet the requirements of the accelerator power supply for rapidity and synchronism of the analog signal output.

As shown in fig. 3f, in this embodiment, the high-speed DA daughter board includes a 40-pin standardized daughter board interface, a DAC chip, a level conversion circuit, a reference source, and a front-end conditioning circuit. Two paths of DAC signals are usually needed in one power supply, so a 2-path 14-bit high-speed DAC can be adopted by a DAC chip, and 125Msps can be adopted for being compatible with most power supply sampling rates. In addition, a level conversion circuit is also adopted to isolate digital signals, meanwhile, the conditioning of the 2-path circuit mainly plays a role in amplitude limiting, and an overcurrent protection circuit can also be adopted. For more high-speed acquisition requirements, a plurality of high-speed DA daughter boards can be inserted into the mainboard for realization.

Preferably, the IO board is used as a separate daughter board because a portion of the low power accelerator power supply has a demand for the path state controller. The IO daughter board is mainly used for monitoring internal state signals and switching signals of the accelerator power supply. The IO board is a main unit for performing independent digital power on/off, reset and internal fault detection. The low-speed IO daughter board generally needs to meet requirements of reliability and interference resistance. Wherein interference between changes in circuit state at high voltage is also taken into account to meet the reliability control requirements of the accelerator power supply for state signal output and input.

As shown in fig. 3c, the IO daughter board specifically includes a 40-pin standardized daughter board interface, a relay circuit, and a level shift circuit. Wherein, 20 input signals are needed in one power supply, 4 relay switches are needed to output, and 5V can be generally adopted as a higher voltage threshold to improve the anti-interference capability. In addition, level shifting circuits are also used for digital signal isolation. For power supplies with poor EMC, the internal state board of the power supply can be controlled in a data signal bus mode through an RS485/422 port.

Preferably, the PWM daughter board is used as a single daughter board because different accelerator power supplies have different numbers of paths and electrical requirements for PWM. The PWM sub-board is mainly used for converting a PWM signal sent from the inside of the accelerator power supply controller into a required signal and then sending the signal to a driving circuit of the main circuit. The PWM daughter board is a key component for performing feedback control of the digital power supply, and is usually driven by an optical signal inside the power supply with large interference. The PWM daughter board is generally required to meet the requirements of reliability and interference resistance. The PWM requirements of most power supplies of the accelerator are obtained by combining the PWM sub-boards. In the case of strict timing requirements, the output state of the PWM needs to have a strict state before the controller is started, and therefore, an interlock mechanism is needed to ensure the initial state of the PWM.

As shown in fig. 3a and 3b, in the present embodiment, the PWM sub-board includes a first PWM sub-board and a second PWM sub-board, the first PWM sub-board outputs 12 PWM (as shown in fig. 3 a), and the second PWM sub-board outputs 8 PWM and inputs 4 PWM (as shown in fig. 3 b). This is also to accommodate the input signal requirements of most power supplies. Multiple PWM signals are usually required in one power supply, and this can be done by using a 5MDB HFBR. For more PWM channel number requirements, the PWM channel number can be led out from the pin interface lead of the bottom plate 40. In addition, the WR board is a MINI board which purchases credit and time service system supporting a white rabbit, and the power supply module is a standard module power supply which is commercially purchased and meets the requirements through EMC detection.

Further, the WR sub-board is used for the controller to support high precision time synchronization. From the viewpoint of whether or not time is supported, there are generally two types of accelerator power supplies, one is a power supply that supports time synchronization, and the other is a power supply that does not require time synchronization. The function of supporting time synchronization is therefore used as a daughter board. The WR daughter board is provided with two JMDSS interfaces which are different from each other, namely a male interface and a female interface, and are connected with the mainboard, so that reverse check is prevented. The area of WR daughter board is less, has two matchboxes so big, in order to guarantee its reliable steady operation, can take the fin certainly on this daughter board to can fasten to the bottom plate with the screw. As a standard WR daughter board, the interface meets the requirements of time service and synchronization, and unnecessary power supplies can be removed, so that waste is avoided.

Furthermore, the power module is used for providing a direct current power supply required by the circuit board, 4 paths of output voltages of the direct current power supply are +/-12V, + 5V and +/-3.3V respectively, and 220V alternating current is adopted for supplying power; these voltages belong to standard voltages for supplying different circuit units. The advantage of the separated power supply is that the separated power supply can play the roles of isolation and local protection, and simultaneously, because the circuit has different requirements on the indexes of the circuit due to the stability of the circuit to the voltage, the separated power supply is favorable for high cost performance. In addition, due to the different types of accelerator power supplies, the demands on the types of power supply voltages are different, and the voltages can be flexibly distributed. Unnecessary voltage can be removed, and waste is avoided.

Preferably, as shown in fig. 4a to 4c, the structure of the chassis provided in this embodiment is shown. The case is a container installed on a circuit board of the power supply controller of the accelerator, and the circuit board is installed in the case in a strong magnetic and strong electric environment inside the power supply of the ion accelerator and has a good shielding effect. The standard size of 1U in height and 19 inches in width is adopted, so that the installation is convenient. The chassis depth is not limited, but should be between 230cm and 300cm, considering the application to different cabinets. The case is divided into a front panel and a rear panel, and the front panel and the top cover plate can be detached to facilitate the installation of the internal circuit board. In order to facilitate the heat dissipation of the internal circuit, the two side surfaces of the case can be opened for heat dissipation control and shielded by an electromagnetic shielding net.

As shown in fig. 4a, the front panel of the chassis is mainly used for providing a maintenance interface, including a reset hole corresponding to a corresponding interface on the motherboard, 4 power status lamps, 2 USB external interfaces, 2 Type _ C debug interfaces, a gigabit ethernet external interface (RJ 45), an LCD external interface, and the reset hole, the USB external interface, the Type _ C debug external interface, the gigabit ethernet external interface, the LCD external interface is respectively used as the reset interface on the motherboard, the USB interface, the main control board debug interface, the WR board debug interface, the gigabit ethernet electrical interface, the leading-out port of the LCD interface. The LCD external interface is also used for installing an OLED liquid crystal screen about 1.3 inches and displaying information such as IP addresses and power states. In addition, the front panel of the case is also provided with a handle and a mounting hole for connecting the rear panel of the case.

As shown in fig. 4c, the rear panel of the chassis is mainly used for a working interface when the power supply operates, and includes: 24 PWM optical IO external interfaces of SMA form, 1 electric external interface of 24 needle J30J, 1 CAN external interface, 1 RS485/422 external interface, 1 RS232/IIC external interface, 6 electric signal external interfaces of SMA form, 2 WR board SFP external interfaces, 4 SMA optical signal external interfaces, 1 gigabit Ethernet SFP external interface, 2 gigabit SFP + external interfaces, 1 power supply interface of 220V with switch and 1 ground terminal. Specifically, 24 PWM optical IO external interfaces in the form of SMA are used as leading-out interfaces of 2 PWM sub-boards; a 24-pin J31J electric external interface is used as an outlet of the IO daughter board; the CAN external interface is used as an outlet of the CAN interface on the mainboard and is used for managing a power supply formed by connecting module power supplies (including standardized hot plug module power supplies) in series and parallel; the RS485/422 external interface is used as an outlet of a serial port on the mainboard and is used for communicating with an independent state control board in the power supply; the RS232/IIC is used for communicating with an independent liquid crystal screen in the power supply; any 2 of the 6 SMA electrical signal external interfaces are used as leading-out ports of the 2 SMA interfaces on the mainboard and are used for receiving an electrical trigger signal and an external clock signal; the rest 4 analog signal leading-out ports are used as two analog signal leading-out ports of the high-speed AD sub-board and the high-speed DA sub-board and are used for receiving signals of the high-speed ADC and the high-speed DAC; 2 WR board SFP ports are used as leading-out ports of the WR boards and are used as leading-out ports of the WR board SFP ports; 4 SMA optical signal ports are used as leading-out ports of 2 optical output interfaces and 2 optical receiving interfaces on the mainboard and are used for 100Mbps optical port communication; and the 1 gigabit Ethernet SFP external interface and the 2 gigabit SFP + external interface are respectively used as leading-out interfaces of the 1 gigabit Ethernet SFP interface and the 2 gigabit SFP + interface on the mainboard.

Example 2

Based on the ion accelerator standardized power supply controller, the invention also provides a dynamic local reconfigurable method of the particle accelerator standardized power supply controller, which comprises the following steps:

1) Configuring a standardized power controller of an ion accelerator, and respectively configuring an embedded EPICS application program and a modular bottom-layer regulator framework in an ARM processor and an FPGA of a main control board;

2) According to actual functional requirements, carrying out dynamic local reconfiguration on corresponding modules in a modularized bottom layer regulator frame in the FPGA, and simultaneously carrying out corresponding combination adjustment on daughter boards connected with a mainboard;

3) When the system runs or starts, the embedded EPICS application program in the ARM processor reads and writes the FPGA, and directly issues related variables needing to be controlled through a network in the main control board into standard PV variables supported by EPICS, and then the PV variables are communicated with an upper computer to realize monitoring and control of different types of accelerator power supply main circuits.

Preferably, in the step 1), the embedded EPICS application program is configured in the main control board, and the power controller application layer software adopts the embedded EPICS software as standard software, and directly issues the PV variable to monitor and control the power supply, thereby realizing unification and standardization of the communication layer.

The embedded EPICS software is based on a Linux environment, and utilizes EPICS base (version 3.15.6) to develop an embedded EPICS IOC (refer to EPICS reference manual) program of a power supply standard in a cross compiling mode, wherein the embedded IOC program runs in an onboard hardmac ARM. The communication between the upper computer and the FPGA is executed through the PV quantity of the EPICS, and the EPICS IOC can directly access register resources in the FPGA chip through an external driving program in the onboard ARM to finish the read-write operation of register parameters in the FPGA, and can also access waveform data and local bus data through the external driving program in the onboard ARM. The information such as power supply current, voltage, state and the like collected in the FPGA can be displayed on a CSS monitoring interface of the upper computer through the PV quantity of the EPICS, and the updating rate is 0.5-1Hz; the regulator, the module power management, the waveform data and the like in the power controller can be set on a CSS monitoring interface of the upper computer through the PV variable of EPICS; the DAC output signals in the power supply controller can be set through the CSS monitoring interface of the upper computer, and the maximum frequency is 125MHz; in a power supply controller FPGA, each high-speed ADC acquisition channel needs to have the storage capacity of historical acquisition data of more than 100Kbytes, and historical data of 200ms time length, 1us sampling interval and 20000 points are cached in each ADC acquisition channel in a rolling mode through a DDR3/4 memory; parameters such as preceding stage voltage, the number of power supply modules, running time, working current, running state, starting time, last fault and the like can be displayed on a CSS monitoring interface of the upper computer; the method needs to have the self-checking of basic functions after power-on, such as power states, current, voltage, current states, temperature states, interface connection states, communication states and the like of all paths; the monitoring device has the advantages that the monitoring device has the capability of monitoring necessary state signals in the operation process, alarms are needed for the abnormal states of over-temperature, voltage and current and the abnormal state of interface connection, and fault alarms are carried out by using the modes of state indicator lamps, data packets and the like.

As shown in fig. 5, the workflow of embedded EPICS configured in the main control board includes the following steps:

1.1 Boot the Linux system in the ARM processor to start and initialize;

1.2 Starting an IOC main program, finishing the running of a self-starting script, and maintaining the process to run in a background by a procServ program; the procServ program is a program for maintaining the progress of the IOC main program, ensures the IOC main program to be self-started, and maintains the progress to be always in a running state;

1.3 The IOC main program is started, then the hpu _16.Db file is called to issue all PV variables in the file, and a device support program connected with each PV variable is called to set a scanning period to run, namely corresponding data, parameters or states in the FPGA processor are controlled through a network; the hpu _16.db file is used for the ARM processor to access data of the FPGA processor, and comprises a data structure of a PV variable, a scanning period, a calling definition of an equipment support program and the like;

1.4 Read the save.sav file (the file is a setting file supported by an autosave device provided by the official, the file internally specifies the value of the PV variable to be saved), and write the PV value saved therein into the corresponding PV variable, that is, the ARM processor reads data from the save.sav file and uploads the data to the upper computer.

Preferably, in the step 1.1), the method for booting the Linux system and initializing includes:

1.1.1 Loading a u-boot program to boot the Linux system;

1.1.2 B) running a self-starting script in the/etc/rc.locl after the Linux system is started, and loading a top.bin file to configure a full bit stream;

1.1.3 Loading a device tree of pl.dtbo file configuration, including DMA, RS485 and the like; the pl.dtbo file is a self-defined equipment tree starting file and is used for describing hardware information related to the part of the bottom layer adjuster of the FPGA processor;

1.1.4 Loading drivers including a DMA device driver, an RS485 device driver, an IIC device driver, an equally-spaced access device and the like;

1.1.5 Configure the serial baud rate and start-stop check bit of/dev/ttyPS 1.

Preferably, in the step 2), in the FPGA layer, before the dynamic reconfiguration technology is not adopted, the FPGA module needs to be recompiled, debugged, and program is downloaded every time the FPGA module changes, so that the development cycle is long, and the efficiency is low. Accordingly, there are several power supply topologies that make it possible to produce several FPGA regulators. This makes the design version of FPGA regulator in the controller many, lacks flexibility, adaptability. For this reason, a set of regulators or some functional units cannot be applied to various power supply types.

The invention adopts the dynamic partial reconfiguration technology to carry out the algorithm design of the bottom layer regulator and other variable functional units and carries out the splitting of the variable functional units. As shown in fig. 6, this structure provides a regulator programming framework comprising: the device comprises an ADC module, a filtering module, a protection module, an algorithm module and a pulse modulation module. By adopting the PCAP technology of the FPGA, the specific implementation of some or all modules can be dynamically replaced when the system runs or is started, so that the modules can be dynamically replaced and upgraded, the recombination of the modules in the regulator is finally completed, a new regulator is formed, and the flexibility, the adaptability and the expansibility of the regulator design are increased. For the power supply, by utilizing dynamic local reconfiguration, the purpose of quickly switching one set of power supply FPGA regulator program to another power supply FPGA regulator program can be realized, and the purpose of controlling the main circuits of various accelerator power supplies by one set of controller is realized. Therefore, the universality and the uniformity of the power supply controller are realized, and the power supply controller can be used as a standardized design. Meanwhile, after the program is compiled, the method does not need to compile and download again, and can quickly finish the replacement of different power supply programs only by setting, thereby greatly improving the efficiency.

Specifically, as shown in fig. 6, the power supply controller dynamic partially reconfigurable method includes the following steps:

2.1 FPGA IDE (Vivado) generates bit file full of the complete regulator and partial bit file partial of each reconfiguration module under the reconfiguration mode;

2.2 Adopting FPGA IDE to generate corresponding bin files full.bin and partial.bin from full.bit and each partial.bit, and transferring the above two bin files to a User _ Application User space of embedded Linux by an SSh protocol/card reader (SD card);

2.3 Compile a script file rc1 for downloading full.bin files to the PL terminal reconfiguration region, the script file comprises all the steps of downloading the content in the bin files to the FPGA _ PL reconfiguration region through a PCAP mechanism, and different script files only need to change the file names;

2.4 Power-on starting the power supply controller, entering a Linux system, running a script file rc1, and checking a power supply performance index under default configuration;

2.5 Compiling a script file rc2 for downloading a part.bin file of a specified reconfigurable module to a PL (provider) terminal reconfiguration region according to a dynamic reconfiguration requirement, and only changing the bin file name of different modules in the script file rc1 compared with the script file rc 1;

2.6 ) running the script file rc2 and checking the power performance index of the script file rc 2;

2.7 ) repeating steps 2.5) -2.6), the dynamic replacement of other modules can be dynamically realized.

In summary, the invention provides a standardized power supply controller inside an ion accelerator magnet power supply and a dynamic local reconfigurable method thereof.A unified set of controller is utilized in the power supply controller, codes are not compiled, and the universality, the unification and the standardization of the controller inside the power supply are realized only by setting the main circuit structure of controllable almost all known types of power supplies (including a series-parallel module power supply, a superconducting power supply, a sine wave scanning power supply, a point scanning power supply, a two-pole iron power supply, a four-pole iron power supply, a solenoid power supply, a correction power supply, an injection-drawing convex rail power supply, a switch iron power supply, a fast four-pole iron power supply, a triangular wave scanning power supply and the like); the embedded EPICS application program is an embedded IOC, and directly issues the quantity required to be controlled by a network in a power supply into a PV variable of an EPICS standard, so that the unification and standardization of external communication of different types of power supplies are realized; the embedded EPICS program develops and expands the functions of the power supply by adding or modifying the mode supported by the equipment, and supports the time service function of the white rabbits; when the system runs or is started, local modules of the digital regulator in the FPGA can be dynamically replaced or recombined, so that a new regulator is quickly formed to adapt to the requirements of new main circuit topology or various function control in the power supply; the invention can be widely applied to the field of new-generation high-requirement ion accelerators.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. An ion accelerator normalized power supply controller, comprising:

the main board, the main control board and the sub-boards are arranged in the case;

various standardized interfaces are arranged on the main board, and comprise a communication interface, a standardized user-defined interface and a main control board interface;

the communication interface is used for realizing communication between the power supply controller and the inside and outside equipment of the accelerator power supply;

the standardized custom interface is used for realizing the connection between the main board and the daughter boards with different functions and providing a power interface for connecting a power module;

the main control board interface is used for realizing the connection between the main control board and the main board and collecting all controllable signals received by the main board to the main control board;

an ARM processor and an FPGA are arranged in the main control board;

an embedded EPICS application program is configured in the ARM processor and used for reading and writing the FPGA, issuing related variables in the main control board into standard PV variables supported by EPICS, and then communicating with an upper computer;

and a modularized bottom layer regulator frame is configured in the FPGA, and monitoring and control of main circuits of different types of accelerator power supplies are realized by carrying out dynamic local reconfiguration on corresponding modules in the modularized bottom layer regulator frame.

2. The ion accelerator standardized power supply controller as claimed in claim 1, wherein the development framework of the embedded EPICS application is a development framework based on device support, and the device support comprises 11 standard device supports including reference waveform control, analog input, analog output, quench protection, adjustment parameter reading and writing, current and voltage reading and writing protection, synchronization and triggering, IO reading and writing, state reading and writing, liquid crystal screen reading and writing, and module power supply serial-parallel connection.

3. The ion accelerator normalized power source controller of claim 1, wherein the modular underlying regulator frame comprises an ADC module for receiving a feedback current or voltage signal, a filtering module, a protection module, an algorithm module, and a pulse modulation module; the filtering module is used for filtering the current or voltage signal received by the ADC module and sending the current or voltage signal to the protection module and the algorithm module; the protection module and the algorithm module process the filtered signals and send the processed signals to the pulse modulation module; the pulse modulation module generates a PWM signal and outputs the PWM signal to a main circuit of an accelerator power supply.

4. The ion accelerator standardized power supply controller according to claim 2, wherein the sub-board comprises at least one of a low speed AD sub-board, a high speed DA sub-board, an IO sub-board, a PWM sub-board, and a WR sub-board; the low-speed AD sub-board and the high-speed AD sub-board are used for collecting feedback current and voltage signals inside the accelerator power supply with different sampling speeds, converting the feedback current and voltage signals into digital signals and sending the digital signals to the main control board; the high-speed DA sub-board is used for converting data generated inside the main control board into analog signals to be output, and the analog signals are used for observing or serving as a given reference of a quick-response analog power supply; the IO daughter board is used for monitoring various state signals and switching signals in the accelerator power supply; the PWM sub-board is used for converting the PWM signal sent by the main control board into a required signal and then sending the required signal to a driving circuit of the accelerator power supply main circuit; the WR sub-board supports a white rabbit time service system and is used for time synchronization of the power supply controller.

5. The ion accelerator standardized power supply controller of claim 4, wherein the communication interfaces comprise 1 gigabit Ethernet electrical interface, 1 gigabit Ethernet SFP interface, 2 WR board SFP interfaces, 2 gigabit SFP + interfaces, 2 USB interfaces, 1 CAN interface, 1 485 interface, 1 serial port, 1 main control board debugging interface, 1 WR board debugging interface, 2 optical receiving ports, 2 optical output interfaces, 1 debugging interface, system clock/reset interface, 1 LCD interface, 2 SMA interfaces, and each communication interface is used for connecting internal and external devices of the power supply;

the standardized custom interface comprises 3 40 pin interfaces, 2 60 pin interfaces and 1 power supply interface; 3 40-pin interfaces for connecting and combining daughter boards with different functions through 40-pin connectors; 2 60-pin interfaces are used for connecting the WR daughter card; the power interface is used for being connected with the power module through the power connector.

6. An ion accelerator normalised power supply controller as claimed in claim 5, wherein said cabinet includes a front panel, a rear panel and a top cover, said front panel and top cover being removably mounted on said rear panel;

the front panel is used for providing a maintenance interface, and comprises: at least one of a reset hole, 4 power state lamps, 2 USB external interfaces, 2 Type _ C debugging external interfaces, 1 kilomega Ethernet external interface and an LCD external interface; the reset hole, the USB external interface, the Type _ C debugging external interface, the gigabit Ethernet electric external interface and the LCD external interface are respectively used as a reset interface, a USB interface, a main control board debugging interface, a WR board debugging interface, a gigabit Ethernet electric interface and a leading-out port of an LCD interface on the main board;

the rear panel is used for the power supply operation work interface, includes: 24 PWM optical IO external interfaces in an SMA form, 1 24-pin J30J electric external interface, 1 CAN external interface, 1 RS485/422 external interface, 1 RS232/IIC external interface, 6 SMA electric signal external interfaces, 2 WR board SFP external interfaces, 4 SMA optical signal external interfaces, 1 gigabit Ethernet SFP external interface, 2 gigabit SFP + external interfaces, 1 220V power supply interface with a switch and 1 grounding terminal;

the 24 PWM optical IO external interfaces in the SMA form are used as leading-out interfaces of the 2 PWM sub-boards; the 1 24-pin J30J electric external interface is used as an outlet of the IO daughter board; the 1 CAN external interface is used as an outlet of a CAN interface on the mainboard and is used for managing a power supply formed by connecting module power supplies in series and parallel; the RS485/422 external interface is used as a leading-out port of the 485 interface and is used for communicating with an independent state control board in the power supply; the RS232/IIC external interface is used as a leading-out port of a serial port on the mainboard and is used for communicating with an independent liquid crystal display inside the power supply; any 2 of the 6 SMA electrical signal external interfaces are used as leading-out ports of the 2 SMA interfaces on the mainboard for receiving an electrical trigger signal and an external clock signal, and the remaining 4 are used as two analog signal leading-out ports of the high-speed AD sub-board and the high-speed DA sub-board for receiving high-speed ADC and high-speed DAC signals; the 2 WR board SFP external interfaces are used as leading-out interfaces of the WR board SFP interfaces; the 4 SMA optical signal ports are used as leading-out ports of 2 optical output interfaces and 2 optical receiving interfaces on the mainboard and are used for 100Mbps optical port communication; the 1 gigabit Ethernet SFP external interface and the 2 gigabit SFP + external interface are respectively used as leading-out interfaces of the 1 gigabit Ethernet SFP interface and the 2 gigabit SFP + interface on the mainboard.

7. The controller as claimed in claim 1, wherein the power module is configured to provide a dc power required by the motherboard, the dc power provides at least one of ± 12V, + 5V, + 3.3V, and is powered by 220V ac for powering a board card in the controller.

8. A dynamically locally reconfigurable method of normalising power supply controllers using an ion accelerator according to any of claims 1 to 7, including the steps of:

configuring a standardized power controller of an ion accelerator, and respectively configuring an embedded EPICS application program and a modular bottom-layer regulator framework in an ARM processor and an FPGA of a main control board;

according to actual functional requirements, carrying out dynamic local reconfiguration on corresponding modules in a modularized bottom layer regulator frame of the FPGA, and simultaneously carrying out corresponding combination adjustment on a daughter board connected with a mainboard;

when the system runs or starts, the embedded EPICS application program in the ARM processor reads and writes the FPGA, and after relevant variables in the main control board are issued into PV variables supported by standard EPICS, the FPGA communicates with an upper computer to realize monitoring and control of different types of accelerator power supply main circuits.

9. The method of claim 8, wherein the workflow of the embedded EPICS application comprises the steps of:

guiding a Linux system in an ARM processor to start and initializing;

starting an IOC main program in the embedded EPICS application program to finish the running of the self-starting script;

after the IOC main program is started, calling the hpu _16.Db file to release all PV variables in the file, calling equipment support programs related to all PV variables to set a scanning period to run, and controlling corresponding data, parameters and states in the FPGA;

and the ARM processor reads or writes PV variable data from the FPGA and synchronizes with the upper computer.

10. The method of claim 8, wherein the method of dynamically partially reconfiguring respective modules within a modular underlying regulator framework within an FPGA, in accordance with actual functional requirements, comprises:

2.1 Generating a full bit file of the framework of the modular bottom-layer regulator and a partial bit file of a part corresponding to each reconfiguration module in the reconfiguration mode;

2.2 Based on full.bit and each partial.bit file, generating corresponding bin files full.bin and partial.bin, and transferring the obtained two bin files to a User _ Application User space of the embedded Linux;

2.3 Writing a first script file for downloading full.bin files to the reconfigurable area in the FPGA _ PL terminal, wherein the first script file comprises all the steps of downloading the contents in the full.bin files to the reconfigurable area in the FPGA _ PL terminal through a PCAP mechanism;

2.4 Power-up power supply controller;

2.5 Enter Linux and run the first script file, look over the performance index of power under the default configuration;

2.6 Compiling a second script file for downloading a part.bin file of the specified reconfigurable module to a reconfiguration region of an FPGA _ PL terminal according to the dynamic reconfiguration requirement;

2.7 Running a second script file to check the power performance index of the second script file;

2.8 ) repeating the steps 2.6) -2.7) to realize the dynamic replacement of other modules.

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