CN115527937A - 半导体装置及其形成方法 - Google Patents
半导体装置及其形成方法 Download PDFInfo
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- CN115527937A CN115527937A CN202210220319.XA CN202210220319A CN115527937A CN 115527937 A CN115527937 A CN 115527937A CN 202210220319 A CN202210220319 A CN 202210220319A CN 115527937 A CN115527937 A CN 115527937A
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Abstract
一种半导体装置及其形成方法,形成半导体装置的方法包括在第一半导体区域上方沉积第一高介电常数介电层,在第一高介电常数介电层上执行第一退火制程,在第一高介电常数介电层上方沉积第二高介电常数介电层;以及在第一高介电常数介电层及第二高介电常数介电层上执行第二退火制程。
Description
技术领域
本揭露关于一种半导体装置及其形成方法。
背景技术
半导体装置用于多种电子应用,诸如举例而言,个人计算机、手机、数字相机、及其他电子设备。半导体装置通常是通过在半导体基板上方依序沉积绝缘层或介电层、导电层、及半导体材料层,且使用微影术图案化各种材料层以在其上形成电路组件及元件来制造的。
半导体行业通过不断减小最小特征尺寸来不断提高各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,从而允许更多组件整合至给定面积中。
发明内容
本揭露的一些实施例中,一种形成半导体装置的方法,该方法包含以下步骤:在一第一半导体区域上方沉积一第一高介电常数介电层;在该第一高介电常数介电层上执行一第一退火制程;在该第一高介电常数介电层上方沉积一第二高介电常数介电层;及在该第一高介电常数介电层及该第二高介电常数介电层上执行一第二退火制程。
本揭露的一些实施例中,一种形成半导体装置的方法,该方法包含以下步骤:在一第一半导体区域上方沉积一第一高介电常数介电层;在该第一高介电常数介电层上执行一第一退火制程;在该第一高介电常数介电层上方沉积一第二高介电常数介电层;在该第一高介电常数介电层及该第二高介电常数介电层上执行一第二退火制程,其中在该第二退火制程之后,该第一高介电常数介电层与该第二高介电常数介电层的组合结晶度高于70%。
本揭露的一些实施例中,一种半导体装置包含一第一栅电极及一第二栅电极。该第一栅电极包含一第一高介电常数介电层;与该第一高介电常数介电层接触的一第一p型功函数调谐金属;及在该第一p型功函数调谐金属上方的一第一导电材料。第二栅电极包含一第二高介电常数介电层;与该第二高介电常数介电层接触的一第一n型功函数调谐金属;与该第一n型功函数调谐金属接触的一第二p型功函数调谐金属;及该第二p型功函数调谐金属上方的一第二导电材料,其中该第一高介电常数介电层及该第二高介电常数介电层的结晶度高于70%。
附图说明
本揭露的态样在与随附附图一起研读时自以下详细描述内容来最佳地理解。应注意,根据行业中的标准规范,各种特征未按比例绘制。实际上,各种特征的尺寸可为了论述清楚经任意地增大或减小。
图1是根据一些实施例的三维视图中的鳍式场效晶体管(fin Field-EffectTransistor,finFET)的实例;
图2、图3、图4A、图4B、图5A、图5B、图6A、图6B、图6C、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19、图20、图21、图22、图23、图24、图25、图26A、图26B、及26C是根据一些实施例的制造FinFET的中间阶段的横截面图。
【符号说明】
70:基板
72:鳍片
74:隔离区
76:STI区、虚设栅极介电层
78:虚设栅极
80:遮罩
82:栅极间隔物
84:源极/漏极区
86:源极/漏极区
88:蚀刻终止层
90:ILD、第一ILD
91:介面介电层
92:栅极介电层
92A~92D:栅极介电材料
120:栅电极
120A~120D:栅电极
124:ILD、第二ILD
128:栅极遮罩
130:源极/漏极触点
132:栅极触点
136:硅化物
200:第一区域
202:第一高介电常数介电层
203:第一退火制程
204:第一覆盖层
206:蚀刻遮罩
206A:底部抗反射涂布层
206B:光阻剂
210:退火制程
212:第二高介电常数介电层
214:第二退火制程
216:第二覆盖层
218:退火制程
228:第一功函数调谐层、第一功函数调谐金属
230:遮罩
232:第二功函数调谐层、第二功函数调谐金属
234:遮罩
236:第三功函数调谐层、第三功函数调谐金属
238:遮罩
240:第四功函数调谐层、第四功函数调谐金属
241:附着层
242:导电材料
300:第二区域
400:第三区域
500:第四区域
A-A:横截面
B-B:横截面
C-C:横截面
T1~T3:厚度
具体实施方式
以下揭示内容提供用于实施所提供标的物的不同特征的许多不同实施例、或实例。下文描述组件及配置的特定实例以简化本揭露。当然,这些仅为实例且非意欲为限制性的。举例而言,在以下描述中第一特征于第二特征上方或上的形成可包括第一特征与第二特征直接接触地形成的实施例,且亦可包括额外特征可形成于第一特征与第二特征之间使得第一特征与第二特征可不直接接触的实施例。此外,本揭露在各种实例中可重复参考数字及/或字母。此重复是出于简单及清楚的目的,且本身且不指明所论述的各种实施例及/或组态之间的关系。
此外,为了便于描述,在本文中可使用空间相对术语,诸如“在……下面”、“在……之下”、“下部”、“在……之上”、“上部”及类似者,来描述诸图中图示的一个元件或特征与另一(多个)元件或特征的关系。空间相对术语意欲涵盖除了诸图中所描绘的定向以外的装置在使用或操作时的不同定向。装置可另外定向(旋转90度或处于其他定向),且本文中所使用的空间相对描述符可类似地加以相应解释。
各种实施例包括应用于但不限于沿鳍片的侧壁及在鳍片的顶表面上方沉积栅极介电层、且在栅极介电层上执行退火制程的方法。退火制程可在约1000℃至约1150℃范围内的温度下执行。因此,栅极介电层高度结晶且因此经加强,在随后的金属栅极图案化制程期间导致较少的栅极介电层损耗。此外,使用微秒退火制程可减少接合面处的掺杂剂扩散,且允许使用更高的退火尖峰温度,同时降低漏极引起的阻障降低效应。
图1图示根据一些实施例的三维视图中的FinFET实例。FinFET包含基板70(例如,半导体基板)上的鳍片72。隔离区74设置于基板70中,且鳍片72突出于相邻隔离区74之上及之间。尽管隔离区74经描述/图示为与基板70分离,但如本文所使用的术语“基板”可仅指半导体基板或包括隔离区的半导体基板。此外,尽管鳍片72经图示为如基板70的单一、连续材料,但鳍片72及/或基板70可包括单一材料或多个材料。在这个上下文中,鳍片72指在相邻隔离区74之间延伸的部分。
栅极介电层92沿鳍片72的侧壁且在鳍片72的顶表面上方,且栅电极120在栅极介电层92上方。源极/漏极区84或86相对于栅极介电层92及栅电极120设置于鳍片72的相对侧上。图1进一步图示在后面的图中使用的参考横截面。横截面A-A沿栅电极120的纵轴且在例如垂直于FinFET的源极/漏极区84/86之间电流流动方向的方向上。横截面B-B垂直于横截面A-A且沿鳍片72的纵轴并在例如FinFET的源极/漏极区84/86之间电流方向的方向上。横截面C-C平行于横截面A-A,且延伸穿过FinFET的源极/漏极区。为清楚起见,后续图参考这些参考横截面。
本文讨论的一些实施例在使用后栅极制程形成的FinFET的上下文中讨论。在其他实施例中,可使用前栅极制程。此外,一些实施例考虑在平面装置中使用的态样,诸如平面FET、纳米结构(例如,纳米片、纳米线、全环绕栅极、或类似者)场效晶体管(nanostructurefield effect transistor,NSFET)、或类似者。
图2至图26C是根据例示性实施例制造finFET的中间阶段的横截面图。图2、图3、图4A、图5A、及图26A图示图1中所示的参考横截面A-A,但多个鳍片除外。图4B、图5B、图6A、图7至图25、及图26B图示图1中所示的参考横截面B-B,但多个finFET除外。图6B、图6C、及图26C图示图1中所示的参考横截面C-C,但多个finFET除外。
图2图示基板70。基板70可是半导体基板,诸如体半导体基板、绝缘体上半导体(semiconductor-on-insulator,SOI)基板、多层或梯度基板、或类似者。基板70可包括半导体材料,诸如包括Si及Ge的元素半导体;包括SiC、SiGe、GaAs、GaAs、GaAsP、AlGaAs、GaInAs、InAs、GaInP、InP、InSb、及/或GaInAsP的化合物或合金半导体;或其组合物。基板70可经掺杂或无掺杂。在特定实例中,基板70是体硅基板。
图3图示鳍片72及相邻鳍片72之间隔离区74的形成。在图3中,鳍片72形成于基板70中。在一些实施例中,可通过在基板70中蚀刻沟槽在基板70中形成鳍片72。蚀刻可是任何可接受的蚀刻制程,诸如反应离子蚀刻(reactive ion etching,RIE)、中性束蚀刻(neutral beam etching,NBE)、类似者、或其组合。蚀刻可是各向异性的。
进一步地在图3中,在相邻鳍片72之间形成绝缘材料,以形成隔离区74。绝缘材料可是氧化物,诸如氧化硅、氮化物、类似者、或其组合物,且可通过高密度电浆化学气相沉积(high density plasma chemical vapor deposition,HDP-CVD)、可流动CVD(flowableCVD,FCVD)(例如,远端电浆系统中基于CVD的材料沉积及后固化,以使其转化成另一材料,诸如氧化物)、类似者、或其组合来形成。可使用通过任何可接受制程形成的其他绝缘材料。在所示实施例中,绝缘材料为通过FCVD制程形成的氧化硅。一旦形成绝缘材料,则可执行退火制程。进一步地在图3中,诸如化学机械研磨(chemical mechanical polish,CMP)的平坦化制程可移除任何多余的绝缘材料且形成共面的隔离区74的顶表面与鳍片72的顶表面。
尽管未具体图示,但可在鳍片72及/或基板70中形成适当的井。举例而言,n井可形成于基板70的第一区域200、第三区域400、及第四区域500(如图4B及后续图中所示)中,其中待形成诸如p型finFET的p型装置,且p井可形成于基板70的第二区域300(如图4B及后续图所示)中,其中待形成诸如n型finFET的n型装置。
举例而言,为了在第一区域200、第三区域400、及第四区域500中形成n井,可在基板70的第二区域300中鳍片72及隔离区74上方形成光阻剂。光阻剂可经图案化以曝光基板70的第一区域200、第三区域400、及第四区域500。光阻剂可通过使用旋装技术形成,且可使用可接受的光学微影术来图案化。一旦光阻剂经图案化,则可在第一区域200、第三区域400、及第四区域500中执行n型杂质布植,且光阻剂可充当遮罩以基本防止n型杂质布植至第二区域300中。n型杂质可是布植至第一区域200、第三区域400、及第四区域500中的磷、砷、或类似物,其浓度等于或小于1018cm-3,诸如在约1017cm-3与约1018cm-3之间。在布植之后,可移除光阻剂,诸如通过可接受的灰化制程。
此外,为了在第二区域300中形成p井,可在基板的第一区域200、第三区域400、及第四区域500中鳍片72及隔离区74上方形成光阻剂。光阻剂可经图案化以曝光基板70的第二区域300。光阻剂可通过使用旋装技术形成,且可使用可接受的光学微影术来图案化。一旦光阻剂经图案化,则可在第二区域300中执行p型杂质布植,且光阻剂可充当遮罩以基本防止p型杂质布植至第一区域200、第三区域400、及第四区域500中。p型杂质可是布植至第二区域300中的硼、BF2、或类似物,其浓度等于或小于1018cm-3,诸如在约1017cm-3与约1018cm-3之间。在布植之后,可移除光阻剂,诸如通过可接受的灰化制程。在布植之后,可执行退火以活化经布植的p型及n型杂质。布植可在第一区域200、第三区域400、及第四区域400中形成n井,且在第二区域300中形成p井。在一些实施例中,基板的第一区域200、第二区域300、第三区域400、及第四区域500中的各者中的布植不限于以上描述,且可形成p井或n井,使得n型finFET或p型finFET可形成于基板70的这些区域中的各者中。
在图4A及图4B中,隔离区74凹陷,诸如形成浅沟槽隔离(Shallow TrenchIsolation,STI)区。隔离区74凹陷,使得鳍片72自相邻隔离区74之间突出。隔离区74可使用可接受的蚀刻制程(诸如对隔离区74的材料具有选择性的蚀刻制程)而凹陷。举例而言,可使用蚀刻或Applied Materials SICONI工具或稀氢氟(dilutehydrofluoric,dHF)酸的化学氧化物移除。
一般技艺人士将很容易理解,关于图2、图3、图4A、及图4B所描述的制程仅是如何形成鳍片的一实例。在其他实施例中,可在基板70的顶表面上方形成介电层;沟槽可蚀刻穿过介电层;磊晶鳍片可在沟槽中磊晶生长;且可使介电层凹陷,使得同质磊晶及/或异质磊晶结构自介电层突出,从而形成磊晶鳍片。对于n型finFET,磊晶生长不同于p型finFET的材料或磊晶鳍片结构的材料或磊晶鳍片结构可是有利的。
在图5A及图5B中,在鳍片72上形成虚设介电层。虚设介电层可是例如氧化硅、氮化硅、其组合物、或类似物,且可根据可接受的技术(诸如化学气相沉积(chemical vapordeposition,CVD)、热氧化、或类似者)沉积或热生长。在虚设介电层上方形成虚设栅极层,且在虚设栅极层上方形成遮罩层。虚设栅极层可诸如通过使用CVD或类似者沉积于虚设介电层上方,接着诸如通过CMP来平坦化。遮罩层可诸如通过使用CVD或类似者沉积于虚设栅极层上方。虚设栅极层可包含例如多晶硅,尽管亦可使用具有高蚀刻选择性的其他材料。遮罩层可包含例如氮化硅、氧氮化硅、碳氮化硅、或类似物。
此外,在图5A及图5B中,可使用可接受的光学微影术及蚀刻技术来图案化遮罩层,从而形成遮罩80。接着,可通过可接受的蚀刻技术将遮罩80的图案转移至虚设栅极层及虚设介电层,以分别自虚设栅极层及虚设介电层形成虚设栅极78及虚设栅极介电层76。蚀刻可包含可接受的各向异性蚀刻,诸如RIE、NBE、或类似者。虚设栅极78覆盖鳍片72的个别通道区。虚设栅极78亦可具有基本垂直于个别鳍片72的纵向方向的纵向方向。
尽管未具体图示,但可执行用于轻掺杂源极/漏极(lightly doped source/drain,LDD)区的布植。与以上讨论的布植物类似,可在第二区域300(例如,用于n型装置)上方形成诸如光阻剂的遮罩,同时曝光第一区域200、第三区域400、及第四区域500(例如,用于p型装置),且p型杂质可布植至第一区域200、第三区域400、及第四区域500中经曝光鳍片72中。接着可移除遮罩。随后,诸如光阻剂的遮罩可形成于第一区域200、第三区域400、及第四区域500上方,同时曝光第二区域300,且n型杂质可布植至第二区域300中经曝光鳍片72中。接着可移除遮罩。n型杂质可是前面讨论的任何n型杂质,且p型杂质可是前面讨论的任何p型杂质。轻掺杂源极/漏极区可具有约1015cm-3至约1016cm-3的杂质浓度。退火可用于活化经布植的杂质。
进一步地在图5A及图5B中,沿虚设栅极78及虚设栅极介电层76的侧壁形成栅极间隔物82。栅极间隔物82可通过共形沉积(诸如通过CVD或类似者)材料且随后各向异性蚀刻(诸如RIE、NBE、或类似者)材料而形成。栅极间隔物82的材料可是氮化硅、碳氮化硅、其组合物、或类似物。
在图6A、图6B、及图6C中,磊晶源极/漏极区84及86形成于鳍片72的源极/漏极区中。在第一区域200、第三区域400、及第四区域500中,磊晶源极/漏极区84形成于鳍片72的源极/漏极区中,使得各个虚设栅极78设置于各个鳍片72中个别对的磊晶源极/漏极区84中的各者之间。在第二区域300中,磊晶源极/漏极区86形成于鳍片72中源极/漏极区中,使得各个虚设栅极78设置于各个鳍片72中个别对的磊晶源极/漏极区86中的各者之间。
第一区域200、第三区域400、及第四区域500(例如,用于p型装置)中磊晶源极/漏极区84可通过遮蔽(诸如用硬遮罩)第二区域300(例如,用于n型装置)形成。接着,蚀刻第一区域200、第三区域400、及第四区域500中鳍片72的源极/漏极区以形成凹槽。蚀刻可是对鳍片72具有选择性的任何适当蚀刻,且可是各向异性的。接着在凹槽中磊晶生长第一区域200、第三区域400、及第四区域500中的磊晶源极/漏极区84。磊晶生长可是通过使用金属有机CVD(Metal-Organic CVD,MOCVD)、分子束磊晶(Molecular Beam Epitaxy,MBE)、液相磊晶(Liquid Phase Epitaxy,LPE)、气相磊晶(Vapor Phase Epitaxy,VPE)、类似者、或其组合。磊晶源极/漏极区84可包含任何可接受的材料,诸如适用于p型finFET的材料。举例而言,磊晶源极/漏极区84可包含SiGe、SiGeB、Ge、GeSn、或类似物。在一些实施例中,磊晶源极/漏极区84可在鳍片72的通道区上施加压缩应变,从而改善p型装置性能。磊晶源极/漏极区84可具有自鳍片72的个别外表面凸起的表面,且可具有小平面。接着可移除遮罩,诸如通过使用对遮罩材料具有选择性的蚀刻。
第二区域300中磊晶源极/漏极区86可通过遮蔽(诸如使用硬遮罩)第一区域200、第三区域400、及第四区域500来形成。接着,蚀刻第二区域300中鳍片72的源极/漏极区以形成凹槽。蚀刻可是对鳍片72具有选择性的任何适当蚀刻,且可是各向异性的。接着在凹槽中磊晶生长第二区域300中的磊晶源极/漏极区86。磊晶生长可是通过使用MOCVD、MBE、LPE、VPE、类似者、或其组合。磊晶源极/漏极区86可包含任何可接受的材料,诸如适用于n型finFET的材料。举例而言,磊晶源极/漏极区86可包含硅、SiC、SiCP、SiP、或类似物。在一些实施例中,磊晶源极/漏极区86可在鳍片72的通道区上施加拉伸应变,从而改善n型装置性能。磊晶源极/漏极区86可具有自鳍片72的个别外表面凸起的表面,且可具有小平面。接着可移除遮罩,诸如通过使用对遮罩材料具有选择性的蚀刻。
磊晶源极/漏极区84及86及/或鳍片72的源极/漏极区可布植有掺杂剂,类似于先前讨论的用于形成轻掺杂源极/漏极区的制程,接着进行退火。源极/漏极区可具有约1019cm-3至约1021cm-3之间的杂质浓度。第一区域200、第三区域400、及第四区域500(例如,用于p型装置)中源极/漏极区的p型杂质可是前面讨论的任何p型杂质,且第二区域300(例如,用于n型装置)中源极/漏极区的n型杂质可是前面讨论的任何n型杂质。在其他实施例中,磊晶源极/漏极区84及86可在生长期间经原位掺杂。
作为用于形成磊晶源极/漏极区84及86的磊晶制程的结果,磊晶源极/漏极区84/86的上表面具有侧向向外扩展超出鳍片72侧壁的小平面。在一些实施例中,如由图6B所示,这些小平面导致同一FinFET的相邻源极/漏极区84/86合并。在其他实施例中,如由图6C所示,在磊晶制程完成之后,相邻源极/漏极区84/86保持分离。在图6B及图6C中所示的实施例中,形成栅极间隔物82,覆盖延伸至STI区76之上的鳍片72的侧壁的一部分,从而阻挡磊晶生长。在一些其他实施例中,可调整用于形成栅极间隔物82的间隔物蚀刻,以移除间隔物材料,从而允许磊晶生长区延伸至STI区76的表面。
此外,在图6A、图6B、及图6C中,在磊晶源极/漏极区84及86、栅极间隔物82、遮罩80、及隔离区74上共形地形成蚀刻终止层(etch stop layer,ESL)88。在一些实施例中,ESL88可包含使用ALD、CVD、类似者、或其组合形成的氮化硅、碳氮化硅、或类似物。层间介电层(inter-layer dielectric,ILD)90底部沉积在ESL 88上方。ILD 90可包含磷硅玻璃(PSG)、硼硅玻璃(BSG)、硼磷硅玻璃(BPSG)、无掺杂硅玻璃(USG)、或类似物,且可通过任何适合方法沉积,诸如CVD、电浆增强CVD(plasma-enhanced CVD,PECVD)、FCVD、类似者、或其组合。
在图7中,执行诸如CMP的平坦化制程,以使ILD 90的顶表面与虚设栅极78的顶表面平齐。CMP亦可自虚设栅极78上方移除遮罩80及ESL 88。因此,虚设栅极78的顶表面经由ILD 90曝光。在蚀刻步骤(多个)中移除虚设栅极78及虚设栅极介电层76,以便穿过ILD 90且由栅极间隔物82界定的开口形成至鳍片72。各个开口曝光个别鳍片72的通道区。各个通道区设置于相邻对的磊晶源极/漏极区84及86之间。蚀刻步骤(多个)可对虚设栅极78及虚设栅极介电层76的材料具有选择性,其蚀刻可为干式蚀刻或湿式蚀刻。在蚀刻期间,当蚀刻虚设栅极78时,虚设栅极介电层76可用作蚀刻终止层。接着,可在移除虚设栅极78之后蚀刻虚设栅极介电层76。尽管未具体图示,但取决于用于ILD 90与虚设栅极介电层76的材料的相似性,当移除虚设栅极介电层76时,可使ILD 90凹陷,且这个凹陷可导致ESL 88及/或栅极间隔物82的部分突出于ILD 90的顶表面之上。
介面介电层91形成于各个开口中及鳍片72上。介面介电层91可是例如通过热氧化、化学氧化、ALD、或类似者形成的氧化物或类似物。介面介电层91的厚度可在约0.7nm至约2nm的范围内。在一些实施例中,虚设栅极介电层76未自一或多个开口中完全移除,且无需在此类开口中沉积分离的介面介电层91。举例而言,虚设栅极介电层76的剩余部分可是介面介电层91。
在图8中,第一高介电常数介电层202沉积于图7中所示的结构上方。第一高介电常数介电层202可由高介电常数介电材料形成,诸如氧化铪(HfO2)、氧化锆(ZrO2)、氧化钛(TiO2)、或类似物、或其组合物,诸如HfZrO、HfTiO、或类似物。第一高介电常数介电层202可是纯的(诸如包含纯HfO2、纯ZrO2、或纯TiO2)或基本纯的(举例而言,具有大于约90%或95%的原子百分数)。第一高介电常数介电层202的介电常数(k值)高于3.9,且可高于约7.0。第一高介电常数介电层202上覆介面介电层91,且可实体接触介面介电层91。第一高介电常数介电层202形成为共形层,且在鳍片72的侧壁及栅极间隔物82的顶表面及侧壁上延伸。根据本揭露的一些实施例,使用ALD或CVD形成第一高介电常数介电层202。沉积温度可在约200℃与约400℃之间的范围内。第一高介电常数介电层202的厚度T1可在约1nm与约4nm之间的范围内。
进一步参考图8,执行第一退火制程203。在一些实施例中,第一退火制程203是微秒退火(microsecond anneal,μssA),其使用二极管激光或CO激光来达成温度的快速上升。在一些实施例中,温度上升速度在约1,000,000℃/秒至约100,000,000℃/秒范围内。第一退火制程203包括在第一温度Tp 1下的预热,Tp 1可在约400℃至约750℃范围内。接着,温度上升至尖峰退火温度Tp 2,Tp 2可在约1000℃至约1150℃范围内,退火持续时间可在约1毫秒(ms)至约30毫秒(ms)范围内。在第一退火制程203之后,保持一后热温度Tp3,Tp3在约500℃至约700℃范围内。退火制程可在包含诸如N2、Ar或其混合物的气体的周边环境中执行。第一退火制程203可增加第一高介电常数介电层202的结晶度百分数。
在图9中,第一覆盖层204沉积于图8中所示的结构上方。第一覆盖层204经由共形沉积制程(诸如ALD制程、CVD制程、或类似者)形成。第一覆盖层204可包括掺杂剂,诸如镧、铝、钇、钛、镁、铌、镓、铟或类似物。
第一覆盖层204可是掺杂剂的氧化物及/或氮化物。举例而言,第一覆盖层204可包含氧化镧(La2O3)、氮化镧(LaN)、氧化铝(Al2O3)、氮化铝(AlN)、或类似物、或其组合物。第一覆盖层204的厚度T2可在约0.5nm与约2nm的范围内。
在图10中,蚀刻遮罩206形成于图9中所示的结构上方且经图案化。蚀刻遮罩206可经图案化以曝光基板70的第一区域200及第二区域300。根据一些实施例,蚀刻遮罩206包括底部抗反射涂布层(Bottom Anti-Reflective Coating,BARC)206A、及BARC 206A上方的光阻剂206B。硬遮罩(未显示)亦可下伏BARC 206A添加,以辅助蚀刻制程。硬遮罩可形成诸如氧化钛的金属氧化物或氮化硼、诸如氮化钛的金属氮化物,或可包括金属氧化物层上方的金属氮化物层。在一些实施例中,蚀刻遮罩206可经图案化以曝光基板的任何区域(例如,第一区域200、第二区域300、第三区域400、及第四区域500),且经曝光区域不限于上述描述。
在图11中,执行蚀刻制程,其中使用蚀刻遮罩206移除第一区域200及第二区域300中的第一覆盖层204。结果,在第一区域200及第二区域300中显现第一高介电常数介电层202。根据本揭露的一些实施例,经由湿式蚀刻、或类似者执行蚀刻制程。
在图12中,接着移除蚀刻遮罩206,导致第一覆盖层204保留在第三区域400及第四区域500中第一高介电常数介电层202上方,而在第一区域200及第二区域300中第一高介电常数介电层202上方没有第一覆盖层204。在一些实施例中,蚀刻遮罩206(如以上图10中所述)可经图案化以曝光基板的任何区域(例如,第一区域200、第二区域300、第三区域400、及第四区域500中的任意者)以及由蚀刻制程(如以上图11中所述)移除的这些区域中的第一覆盖层204。此外,可执行一或多个退火制程210。退火制程中的各者的退火持续时间可在约0.5秒至约5分钟范围内,且退火制程中的各者的退火温度可在约500℃至约950℃范围内。
在图13中,在蚀刻制程中移除第一覆盖层204。蚀刻制程可选自候选制程的同一群组,且使用候选蚀刻化学品的同一群组,如图11中所示的蚀刻制程。因此,这里不再重复细节。
图14图示根据一些实施例的第二高介电常数介电层212的沉积及第二退火制程214。应了解,一些材料及制程细节可与图8中所示的先前制程相同。这些细节不再重复,可参考先前制程的描述找到。
参考图14,沉积第二高介电常数介电层212。第二高介电常数介电层212的材料可选自用于形成第一高介电常数介电层202(图8)的候选材料的同一群组,且可包括HfO2、ZrO2、TiO2、或类似物、或其组合物,诸如HfZrO、HfTiO、或类似物。第二高介电常数介电层212上覆、且可接触下伏第一高介电常数介电层202。根据本揭露的一些实施例,使用ALD或CVD形成第一高介电常数介电层202及第二高介电常数介电层212。沉积温度可在约200℃与约400℃之间的范围内。第二高介电常数介电层212的厚度T3可等于或小于下伏第一高介电常数介电层202的厚度T1。举例而言,厚度T3可在约1nm与约2nm之间的范围内。第一高介电常数介电层202与第二高介电常数介电层212的组合在下文中可称为栅极介电层92。
进一步参考图14,执行第二退火制程214。第二退火制程214类似于图8中的第一退火制程203,因此在此不再重复细节。第二退火制程214用于增加第一高介电常数介电层202及第二高介电常数介电层212的结晶度百分数。举例而言,第二退火制程214可进一步结晶第一高介电常数介电层202。
在图15中,第二覆盖层216可共形地沉积于第二高介电常数介电层212上方。第二覆盖层216可包含通过ALD、CVD、PECVD、物理气相沉积(physical vapor deposition,PVD)、或类似者沉积的单一层或多个层。第二覆盖层216可包含氮化钛硅(TSN)、氮化钛(TiN)、非晶硅、或类似物。沉积之后,可在约600℃至约1000℃范围内的温度下执行一或多个退火制程218。
在图16中,使用适当的方法移除第二覆盖层216。可使用干式蚀刻制程、湿式蚀刻制程、或类似者移除第二覆盖层216。
由于沿鳍片的侧壁及在鳍片顶表面上方沉积栅极介电层92的第一部分、且接着执行第一退火制程203、接着在栅极介电层92的第一部分上方沉积栅极介电层92的第二部分、且随后执行第二退火制程214,因此可达成优点。这些优点可包括使栅极介电层92结晶,使得栅极介电层92的结晶度百分数(例如,第一高介电常数介电层202及第二高介电常数介电层212的整体组合及/或单独结晶度)高于70%。栅极介电层92的结晶导致栅极介电层92的致密化以及因此而增强。举例而言,高于70%的栅极介电层92的结晶导致更强的栅极介电层92,当栅极介电层92用作蚀刻终止时,其能够在随后的金属栅极图案化制程期间抵抗栅极介电损耗。这样,在随后的金属栅极图案化制程期间,栅极介电层92的损耗可减少多达0.2nm。此外,使用第一退火制程203及第二退火制程214可导致接合面处减少的掺杂剂扩散,且允许使用约1000℃至约1150℃范围内的较高退火尖峰温度,同时具有降低的漏极引起的阻障降低效应。因此,性能退化的风险降低。
在图17中,接着在栅极介电层92上共形地形成第一功函数调谐层228。第一功函数调谐层228可是任何可接受的材料,以将装置的功函数调谐至给定待形成的装置的应用的所需量,且可使用任何可接受的沉积制程来沉积。在一些实施例中,第一功函数调谐层228是n型功函数金属,且可包含通过ALD、CVD、PVD、或类似者沉积的氮化铝钛(TiAlN)、碳化铝钛(TiAlC、TiAl)、或类似物。
在图18中,接着在第一功函数调谐层228上方沉积遮罩230且经图案化。遮罩230可覆盖第二区域300中的第一功函数调谐层228,同时在第一区域200、第三区域400、及第五区域500中曝光第一功函数调谐层228。在一些实施例中,遮罩230是通过使用旋装技术形成的光阻剂,且可使用可接受的光学微影技术来图案化。
在图19中,在遮罩230经图案化之后,执行对第一功函数调谐层228具有选择性的蚀刻,以自第一区域200、第三区域400、及第四区域500移除第一功函数调谐层228。第一区域200、第三区域400、及第四区域500中栅极介电层92可在这个蚀刻期间充当蚀刻终止。作为第一退火制程203(先前在图8中描述)及第二退火制程214(先前在图14中描述)的结果,当执行对第一功函数调谐层228具有选择性的蚀刻时,栅极介电层92经加强且能够更佳地抵抗栅极介电损耗。
接着移除遮罩230,诸如,若遮罩230是光阻剂,则使用适当的湿式剥离及/或灰化制程。接下来,接着在第一区域200、第三区域400、及第五区域500中栅极介电层92上、以及第二区域300中第一功函数调谐层228上共形地形成第二功函数调谐层232。第二功函数调谐层232可是任何可接受的材料,以将装置的功函数调谐至给定待形成的装置的应用的所需量,且可使用任何可接受的沉积制程来沉积。在一些实施例中,第二功函数调谐层232是p型功函数金属,且可包含通过ALD、CVD、PVD、或类似者沉积的氮化钛(TiN、TaN)或类似物。
在图20中,接着在第二功函数调谐层232上方沉积遮罩234且经图案化。遮罩234可覆盖第四区域500中的第二功函数调谐层232,同时在第一区域200、第二区域300、及第三区域400中曝光第二功函数调谐层232。在一些实施例中,遮罩234是通过使用旋装技术形成的光阻剂,且可使用可接受的光学微影技术来图案化。
在图21中,在遮罩234经图案化之后,执行对第二功函数调谐层232具有选择性的蚀刻,以自第一区域200、第二区域300、及第三区域400移除第二功函数调谐层232。在一些实施例中,可执行定时及/或选择性蚀刻制程,使得在第一区域200、第二区域300、及第三区域400中仅基本移除第二功函数调谐层232,而不在这些区域中显著移除下伏层(例如,栅极介电层92及第一功函数调谐层228)。作为第一退火制程203(先前在图8中描述)及第二退火制程214(先前在图14中描述)的结果,当执行对第二功函数调谐层232具有选择性的蚀刻时,栅极介电层92经加强且能够更佳地抵抗栅极介电损耗。接着移除遮罩234,诸如,若遮罩234是光阻剂,则通过使用适当的湿式剥离及/或灰化制程来移除遮罩234。接下来,接着在第一区域200及第三区域400中的栅极介电层92、以及第二区域300中第一功函数调谐层228及第四区域500中第二功函数调谐层232上共形地形成第三功函数调谐层236。第三功函数调谐层236可是任何可接受的材料,以将装置的功函数调谐至给定待形成的装置的应用的所需量,且可使用任何可接受的沉积制程来沉积。在一些实施例中,第三功函数调谐层236是p型功函数金属,且可包含通过ALD、CVD、PVD、或类似者沉积的氮化钛(TiN)或类似物。
在图22中,接着在第三功函数调谐层236上方沉积遮罩238且经图案化。遮罩238可覆盖第三区域400及第四区域500中的第三功函数调谐层236,同时在第一区域200及第二区域300中曝光第三功函数调谐层236。在一些实施例中,遮罩238是通过使用旋装技术形成的光阻剂,且可使用可接受的光学微影技术来图案化。
在图23中,在遮罩238经图案化之后,执行对第三功函数调谐层236具有选择性的蚀刻以自第一区域200及第二区域300移除第三功函数调谐层236。在一些实施例中,可执行定时及/或选择性蚀刻制程,以便在第一区域200及第二区域300中仅基本移除第三功函数调谐层236,而不在这些区域中显著移除下伏层(例如,栅极介电层92及第一功函数调谐层228)。作为第一退火制程203(先前在图8中描述)及第二退火制程214(先前在图14中描述)的结果,当执行对第三功函数调谐层236具有选择性的蚀刻时,栅极介电层92经加强且能够更佳地抵抗栅极介电损耗。接着移除遮罩238,例如,若遮罩238是光阻剂,则通过使用适当的湿式剥离及/或灰化制程来移除遮罩238。接着,在第一区域200中栅极介电层92、第二区域300中第一功函数调谐层228、以及第三区域400及第四区域500中第三功函数调谐层236上共形地形成第四功函数调谐层240。第四功函数调谐层240可是任何可接受的材料,以将装置的功函数调谐至给定待形成的装置的应用的所需量,且可使用任何可接受的沉积制程来沉积。在一些实施例中,第四功函数调谐层240是p型功函数金属,且可包含通过ALD、CVD、PVD、或类似者沉积的氮化钛(TiN)或类似物。
通过使用图19至图23中所述的制程,可在第一~四区域200、300、400、及500中的各者中形成一或多个p型功函数调谐层,以达到所需的累积厚度(例如,各个开口中第二功函数调谐层232、第三功函数调谐层236及/或第四功函数调谐层240的厚度),且具有不同临限电压的晶体管可形成于第一~四区域200、300、400、及500中的各者中。
在图24中,可在第一区域200、第二区域300、第三区域400、及第四区域500中第四功函数调谐层240上共形地形成黏附层或附着层241。附着层241可包含由ALD或类似者沉积的氮化钛(TiN)或类似物。附着层的厚度可在约2nm至约4nm范围内。附着层241未在后续图中显示。
亦在图24中,导电材料242沉积于附着层241上。导电材料242可包括金属,诸如钨(W)、铝(Al)、钴(Co)、钌(Ru)、其组合物或类似物。可使用CVD、PVD、类似者、或其组合来沉积导电材料242。导电材料242至少填充开口的剩余部分,例如,未由栅极介电层92、第一功函数调谐层228、第二功函数调谐层232、第三功函数调谐层236、第四功函数调谐层240、及附着层241填充的部分。
在图25中,可执行诸如CMP的平坦化制程,以移除栅极介电层92、第一功函数调谐层228、第二功函数调谐层232、第三功函数调谐层236、第四功函数调谐层240、附着层241、及导电材料242的多余部分(这些多余部分在ILD 90的顶表面上方),以形成栅极介电材料92A、92B、92C、及92D(例如,自栅极介电层92的剩余部分)及栅电极120A、120B、120C、及120D(包含第一功函数调谐层228、第二功函数调谐层232、第三功函数调谐层236、第四功函数调谐层240、附着层241、及导电材料242的剩余部分)。具体地,第一区域200中第一栅电极120A包含第四功函数调谐金属240、附着层241、及导电材料242。第二区域300中第二栅电极120B包含第一功函数调谐金属228、第四功函数调谐金属240、附着层241、及导电材料242。第三区域400中第三栅电极120C包含第三功函数调谐金属236、第四功函数调谐金属240、附着层241、及导电材料242。第四区域500中第四栅电极120D包含第二功函数调谐金属232、第三功函数调谐金属236、第四功函数调谐金属240、附着层241、及导电材料242。为便于参考,以下可将栅极120A、120B、120C、及120D称为栅极120。
在图26A、图26B、及图26C中,在各个栅极堆叠(包括栅极介电层92及相应的栅电极120)上方形成栅极遮罩128,且栅极遮罩128可设置于栅极间隔物82的相对部分之间。在一些实施例中,形成栅极遮罩128包括使栅极堆叠凹陷,以便直接在栅极堆叠上方及栅极间隔物82的相对部分之间形成凹槽。栅极遮罩128包含一或多层介电材料,诸如氮化硅、氧氮化硅、或类似物,填充于凹槽中,随后通过平坦化制程以移除在第一ILD 90上方延伸的介电材料的多余部分。
如图26A、图26B、及图26C中所示,第二ILD 124沉积于ILD 90上方。在一些实施例中,第二ILD 124是通过可流动CVD方法形成的可流动膜。在一些实施例中,第二ILD 124由诸如PSG、BSG、BPSG、USG、或类似物的介电材料形成,且可通过任何适合的方法沉积,诸如CVD及PECVD。
根据一些实施例,栅极触点132及源极/漏极触点130穿过ILD 124及ILD 90形成。用于源极/漏极触点130的开口穿过ILD 90及124形成,且用于栅极触点132的开口穿过ILD124及栅极遮罩128形成。可使用可接受的光学微影术及蚀刻技术形成开口。诸如扩散阻障层、黏附层、或类似者的衬里(未显示)及导电材料可形成于开口中。衬里可包括钛、氮化钛、钽、氮化钽、或类似物。导电材料可是铜、铜合金、银、金、钨、钴、铝、镍、或类似物。可执行诸如CMP的平坦化制程以自ILD 124的表面移除多余材料。剩余的衬里及导电材料在开口中形成源极/漏极触点130及栅极触点132。可执行退火制程以在磊晶源极/漏极区84/86与源极/漏极触点130之间的界面处形成硅化物136。源极/漏极触点130实体耦合且电耦合至磊晶源极/漏极区84/86,而栅极触点132实体耦合且电耦合至栅电极120。源极/漏极触点130及栅极触点132可在不同的制程中形成,或可在相同的制程中形成。尽管显示为形成于相同的横截面中,但应理解,源极/漏极触点130及栅极触点132中的各者可形成于不同的横截面中,这可避免触点短路。
各种实施例包括应用于但不限于沿鳍片的侧壁及在鳍片顶表面上方沉积栅极介电层且在栅极介电层上执行一或多个退火制程的方法。退火制程可在约1000℃至约1150℃范围内的温度下执行。因此,当栅极介电层用作蚀刻终止时,栅极介电层高度结晶且因此经加强,从而在随后的金属栅极图案化制程期间减少栅极介电损耗。此外,使用微秒退火制程可减少接合面处的掺杂剂扩散,且允许使用更高的退火尖峰温度,同时降低漏极引起的阻障降低效应。因此,性能退化的风险降低。
根据一实施例,用于形成半导体装置的方法包括在第一半导体区域上方沉积第一高介电常数介电层;在第一高介电常数介电层上执行第一退火制程;在第一高介电常数介电层上方沉积第二高介电常数介电层;以及在第一高介电常数介电层及第二高介电常数介电层上执行第二退火制程。在一实施例中,第一高介电常数介电层的第一厚度大于第二高介电常数介电层的第二厚度。在一实施例中,第一退火制程与第二退火制程相同。在一实施例中,在执行第一退火制程及第二退火制程期间,温度上升至1000℃至1150℃范围内的第一温度。在一实施例中,在执行第一退火制程及第二退火制程期间,第一温度保持1毫秒(ms)至30毫秒(ms)的持续时间。在一实施例中,在执行第一退火制程及第二退火制程之后,第一高介电常数介电层及第二高介电常数介电层具有高于70%的组合结晶度。在一实施例中,第一退火制程及第二退火制程在包括氮、氩、或其混合物的周边环境中执行。在一实施例中,该方法进一步包括在第二高介电常数介电层上方沉积第一功函数调谐层;自第一半导体区域的第一、第三、及第四部分上方选择性地移除第一功函数调谐层;在第一功函数调谐层及第二高介电常数介电层上方沉积第二功函数调谐层;自第一半导体区域的第一、第二、及第三部分上方选择性地移除第二功函数调谐层;在第一功函数调谐层、第二功函数调谐层、及第二高介电常数介电层上方沉积第三功函数调谐层;自第一半导体区域的第一及第二部分上方选择性地移除第三功函数调谐层;及在第一功函数调谐层、第三功函数调谐层、及第二高介电常数介电层上方沉积第四功函数调谐层。在一实施例中,第一功函数调谐层包括n型层及第二功函数调谐层,第三功函数调谐层及第四功函数调谐层包括p型层。
根据一实施例,形成半导体装置的方法包括在第一半导体区域上方沉积第一高介电常数介电层;在第一高介电常数介电层上执行第一退火制程;在第一高介电常数介电层上方沉积第二高介电常数介电层;在第一高介电常数介电层及第二高介电常数介电层上执行第二退火制程,其中在第二退火制程之后,第一高介电常数介电层与第二高介电常数介电层的组合结晶度高于70%。在一实施例中,第一退火制程及第二退火制程中的各者包括在400℃至750℃范围内的温度下的预热。在一实施例中,第一退火制程及第二退火制程是微秒退火(microsecond anneal,μSSA)。在一实施例中,在第一退火制程及第二退火制程期间,温度上升至约1000℃至约1150℃范围内的最高温度。在一实施例中,在第一退火制程及第二退火制程期间,最高温度保持1毫秒(ms)至30毫秒(ms)范围内的持续时间。在一实施例中,在第一退火制程及第二退火制程中的各者之后,保持500℃至700℃范围内的后热温度。
根据一实施例,一种半导体装置包括第一栅电极,第一栅电极包括第一高介电常数介电层;与第一高介电常数介电层接触的第一p型功函数调谐金属;及第一p型功函数调谐金属上方的第一导电材料;及第二栅电极,第二栅极包括第二高介电常数介电层;与第二高介电常数介电层接触的第一n型功函数调谐金属;与第一n型功函数调谐金属接触的第二p型功函数调谐金属;及在第二p型功函数调谐金属上方的第二导电材料,其中第一高介电常数介电层及第二高介电常数介电层的结晶度高于70%。在一实施例中,该半导体装置进一步包括第三栅电极,第三栅极包括第三高介电常数介电层;与第三高介电常数介电层接触的第三p型功函数调谐金属;与第三p型功函数调谐金属接触的第四p型功函数调谐金属;及第四p型功函数调谐金属上方的第三导电材料。在一实施例中,第一、第二、第三、及第四p型功函数调谐金属包括相同的材料。在一实施例中,第一、第二、第三、及第四p型功函数调谐金属包括氮化钛,且第一n型功函数调谐金属包括氮化铝钛。在一实施例中,第三p型功函数调谐金属与第四p型功函数调谐金属的组合厚度大于第一p型功函数调谐金属的厚度。
前述内容概述若干实施例的特征,使得熟悉此项技术者可更佳地理解本揭露的态样。熟悉此项技术者应了解,其可易于使用本揭露作为用于设计或修改用于实施本文中引入的实施例的相同目的及/或达成相同优势的其他制程及结构的基础。熟悉此项技术者亦应认识到,此类等效构造并不偏离本揭露的精神及范畴,且此类等效构造可在本文中进行各种改变、取代、及替代而不偏离本揭露的精神及范畴。
Claims (10)
1.一种形成半导体装置的方法,其特征在于,该方法包含以下步骤:
在一第一半导体区域上方沉积一第一高介电常数介电层;
在该第一高介电常数介电层上执行一第一退火制程;
在该第一高介电常数介电层上方沉积一第二高介电常数介电层;及
在该第一高介电常数介电层及该第二高介电常数介电层上执行一第二退火制程。
2.如权利要求1所述的方法,其特征在于,该第一高介电常数介电层的一第一厚度大于该第二高介电常数介电层的一第二厚度。
3.如权利要求1所述的方法,其特征在于,该第一退火制程与该第二退火制程相同。
4.如权利要求3所述的方法,其特征在于,在执行该第一退火制程及该第二退火制程期间,温度上升至1000℃至1150℃的一范围内的一第一温度。
5.如权利要求4所述的方法,其特征在于,在执行该第一退火制程及该第二退火制程期间,该第一温度保持1毫秒至30毫秒的一持续时间。
6.如权利要求1所述的方法,其特征在于,在执行该第一退火制程及该第二退火制程之后,该第一高介电常数介电层与该第二高介电常数介电层具有高于70%的一组合结晶度。
7.如权利要求1所述的方法,其特征在于,该第一退火制程及该第二退火制程在包含氮、氩、或其混合物的一周边环境中执行。
8.如权利要求1所述的方法,其特征在于,进一步包含以下步骤:
在该第二高介电常数介电层上方沉积一第一功函数调谐层;
自该第一半导体区域的一第一部分、一第三部分、及一第四部分上方选择性地移除该第一功函数调谐层;
在该第一功函数调谐层及该第二高介电常数介电层上方沉积一第二功函数调谐层;
自该第一半导体区域的该第一部分、一第二部分、及该第三部分上方选择性地移除该第二功函数调谐层;
在该第一功函数调谐层、该第二功函数调谐层、及该第二高介电常数介电层上方沉积一第三功函数调谐层;
自该第一半导体区域的该第一部分及该第二部分上方选择性地移除该第三功函数调谐层;及
在该第一功函数调谐层、该第三功函数调谐层、及该第二高介电常数介电层上方沉积一第四功函数调谐层。
9.一种形成半导体装置的方法,其特征在于,该方法包含以下步骤:
在一第一半导体区域上方沉积一第一高介电常数介电层;
在该第一高介电常数介电层上执行一第一退火制程;
在该第一高介电常数介电层上方沉积一第二高介电常数介电层;
在该第一高介电常数介电层及该第二高介电常数介电层上执行一第二退火制程,其中在该第二退火制程之后,该第一高介电常数介电层与该第二高介电常数介电层的组合结晶度高于70%。
10.一种半导体装置,其特征在于,其包含:
一第一栅电极,该第一栅电极包含:
一第一高介电常数介电层;
与该第一高介电常数介电层接触的一第一p型功函数调谐金属;及
在该第一p型功函数调谐金属上方的一第一导电材料;及
一第二栅电极,该第二栅电极包含:
一第二高介电常数介电层;
与该第二高介电常数介电层接触的一第一n型功函数调谐金属;
与该第一n型功函数调谐金属接触的一第二p型功函数调谐金属;及
该第二p型功函数调谐金属上方的一第二导电材料,其中该第一高介电常数介电层及该第二高介电常数介电层的结晶度高于70%。
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