CN115527855A - 改善igbt器件铝穿通缺陷的方法 - Google Patents

改善igbt器件铝穿通缺陷的方法 Download PDF

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CN115527855A
CN115527855A CN202211314707.0A CN202211314707A CN115527855A CN 115527855 A CN115527855 A CN 115527855A CN 202211314707 A CN202211314707 A CN 202211314707A CN 115527855 A CN115527855 A CN 115527855A
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aluminum
layer
punch
defect
improving
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郭东旭
冯超
马栋
陆聪
程洁
李魁
孙泽阳
朱金妹
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Hua Hong Semiconductor Wuxi Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

本发明提供一种改善IGBT器件铝穿通缺陷的方法,所述方法包括:提供一半导体结构,所述半导体结构包括硅衬底,且所述硅衬底的上方形成有接触孔;于所述半导体结构的表面形成金属阻挡层;于所述金属阻挡层的表面形成钨层;于所述钨层的表面形成铝层或铝合金层;刻蚀所述接触孔以外区域预设范围内的所述金属阻挡层、所述钨层及所述铝层/所述铝合金层。通过本发明解决了现有的钨回刻及铝刻蚀的工艺流程中较大关键尺寸的接触孔易发生铝穿通的问题。

Description

改善IGBT器件铝穿通缺陷的方法
技术领域
本发明涉及半导体技术领域,特别是涉及一种改善IGBT器件铝穿通缺陷的方法。
背景技术
在当前12英寸绝缘栅双极型晶体管(IGBT)制造领域,接触孔(CT)通常使用金属钨进行填充。然而,由于不同产品的设计差异,同一颗芯片内存在不同关键尺寸(CD)的接触孔,因此,在后续钨回刻的过程中,具有较小CD的接触孔,金属钨可以将接触孔沟槽完全填充,而具有较大CD的接触孔,金属钨只保留在接触孔沟槽的侧壁上,接触孔沟槽的底部只留下很薄的金属阻挡层(比如氮化硅膜层),而随着后续金属铝的淀积,12英寸的硅片受应力影响较大,翘曲度发生较大改变,金属阻挡层薄膜随硅片翘曲产生破裂,因此,金属铝在沉积时会直接穿通CT底部的硅,形成铝穿通的缺陷,从而造成铝硅互溶,进而导致器件失效。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种改善IGBT器件铝穿通缺陷的方法,用于解决现有的钨回刻及铝刻蚀的工艺流程中较大关键尺寸的接触孔易发生铝穿通的问题。
为实现上述目的及其他相关目的,本发明提供一种改善IGBT器件铝穿通缺陷的方法,所述方法包括:
提供一半导体结构,所述半导体结构包括硅衬底,且所述硅衬底的上方形成有接触孔;
于所述半导体结构的表面形成金属阻挡层;
于所述金属阻挡层的表面形成钨层;
于所述钨层的表面形成铝层或铝合金层;
刻蚀所述接触孔以外区域预设范围内的所述金属阻挡层、所述钨层及所述铝层/所述铝合金层。
可选地,所述接触孔的关键尺寸大于1.5μm。
可选地,所述金属阻挡层的材质包括氮化钛或氮化钽。
可选地,所述钨层的厚度范围为2000埃~4000埃。
可选地,所述铝合金层包括铝-硅合金层或铝-硅-铜合金层。
可选地,所述铝-硅合金层中硅的重量百分比为1%~2%;所述铝-硅-铜合金中硅的重量百分比为1%~2%,铜的重量百分比为2%~4%。
可选地,于所述衬底的上方形成所述接触孔的方法包括:于所述硅衬底的表面形成介质层,刻蚀所述介质层形成所述接触孔。
可选地,所述介质层的材质包括氧化硅。
可选地,刻蚀所述接触孔以外区域预设范围内的所述金属阻挡层、所述钨层及所述铝层/所述铝合金层的方法包括:先刻蚀去除所述铝层/所述铝合金层,再刻蚀去除所述钨层及所述金属阻挡层。
可选地,刻蚀去除所述铝层/所述铝合金层、所述钨层及所述金属阻挡层的方法包括干法刻蚀或湿法刻蚀。
如上所述,本发明的改善IGBT器件铝穿通缺陷的方法,通过在金属钨沉积后直接沉积金属铝或铝合金,防止铝与衬底硅之间接触,从而能够防止产生铝穿通,有效改善铝穿通缺陷带来的铝硅互溶问题;而且,对铝或铝合金层刻蚀后再刻蚀金属钨及金属阻挡层以去除不需要的金属膜层,可避免因金属互联造成的短路问题,且分步刻蚀可改善因晶圆翘曲导致的金属阻挡层断裂的问题。
附图说明
图1显示为本发明的改善IGBT器件铝穿通缺陷的方法流程图。
图2显示为本发明的于半导体结构表面形成金属阻挡层后的剖面结构示意图。
图3显示为本发明的于金属阻挡层表面形成钨层后的剖面结构示意图。
图4显示为本发明的于钨层表面形成铝层/铝合金层后的剖面结构示意图。
图5显示为本发明的对金属阻挡层、钨层及铝层/铝合金层刻蚀后的剖面结构示意图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图5。需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的形态、数量及比例可为一种随意的改变,且其组件布局形态也可能更为复杂。
如图1所示,本实施例提供一种改善IGBT器件铝穿通缺陷的方法,所述方法包括:
提供一半导体结构,所述半导体结构包括硅衬底,且所述硅衬底的上方形成有接触孔;
于所述半导体结构的表面形成金属阻挡层;
于所述金属阻挡层的表面形成钨层;
于所述钨层的表面形成铝层或铝合金层;
刻蚀所述接触孔以外区域预设范围内的所述金属阻挡层、所述钨层及所述铝层/所述铝合金层。
如图2~图4所示,本实施例中,通过沉积工艺形成所述金属阻挡层、所述钨层、所述铝层/所述铝合金层。
具体的,所述接触孔的关键尺寸大于1.5μm。
具体的,所述金属阻挡层的材质包括氮化钛或氮化钽。本实施例中,所述金属阻挡层用于抑制衬底硅扩散。
具体的,所述钨层的厚度范围为2000埃~4000埃。
具体的,所述铝合金层包括铝-硅合金层或铝-硅-铜合金层。
作为示例,所述铝-硅合金层中硅的重量百分比为1%~2%;所述铝-硅-铜合金中硅的重量百分比为1%~2%,铜的重量百分比为2%~4%。
具体的,所述硅衬底的上方形成所述接触孔的方法包括:于所述硅衬底的表面形成介质层,刻蚀所述介质层形成所述接触孔。
作为示例,所述介质层的材质包括氧化硅。
具体的,刻蚀所述接触孔以外区域预设范围内的所述金属阻挡层、所述钨层及所述铝层/所述铝合金层的方法包括:先刻蚀去除所述铝层/所述铝合金层,再刻蚀去除所述钨层及所述金属阻挡层。
如图5所示,本实施例中,分步刻蚀所述铝层/所述铝合金层、所述钨层及所述金属阻挡层,可改善因晶圆翘曲导致的所述金属阻挡层断裂的问题。
作为示例,刻蚀去除所述铝层/所述铝合金层、所述钨层及所述金属阻挡层的方法包括干法刻蚀或湿法刻蚀。可选地,本实施例中,采用干法刻蚀实现对所述铝层/所述铝合金层、所述钨层及所述金属阻挡层的刻蚀。
综上所述,本发明的改善IGBT器件铝穿通缺陷的方法,通过在金属钨沉积后直接沉积金属铝或铝合金,防止铝与衬底硅之间接触,从而能够防止产生铝穿通,有效改善铝穿通缺陷带来的铝硅互溶问题;而且,对铝或铝合金层刻蚀后再刻蚀金属钨及金属阻挡层以去除不需要的金属膜层,可避免因金属互联造成的短路问题,且分步刻蚀可改善因晶圆翘曲导致的金属阻挡层断裂的问题。所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。

Claims (10)

1.一种改善IGBT器件铝穿通缺陷的方法,其特征在于,所述方法包括:
提供一半导体结构,所述半导体结构包括硅衬底,且所述硅衬底的上方形成有接触孔;
于所述半导体结构的表面形成金属阻挡层;
于所述金属阻挡层的表面形成钨层;
于所述钨层的表面形成铝层或铝合金层;
刻蚀所述接触孔以外区域预设范围内的所述金属阻挡层、所述钨层及所述铝层/所述铝合金层。
2.根据权利要求1所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,所述接触孔的关键尺寸大于1.5μm。
3.根据权利要求1所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,所述金属阻挡层的材质包括氮化钛或氮化钽。
4.根据权利要求1所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,所述钨层的厚度范围为2000埃~4000埃。
5.根据权利要求1所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,所述铝合金层包括铝-硅合金层或铝-硅-铜合金层。
6.根据权利要求5所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,所述铝-硅合金层中硅的重量百分比为1%~2%;所述铝-硅-铜合金中硅的重量百分比为1%~2%,铜的重量百分比为2%~4%。
7.根据权利要求1所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,于所述硅衬底的上方形成所述接触孔的方法包括:于所述硅衬底的表面形成介质层,刻蚀所述介质层形成所述接触孔。
8.根据权利要求7所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,所述介质层的材质包括氧化硅。
9.根据权利要求1所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,刻蚀所述接触孔以外区域预设范围内的所述金属阻挡层、所述钨层及所述铝层/所述铝合金层的方法包括:先刻蚀去除所述铝层/所述铝合金层,再刻蚀去除所述钨层及所述金属阻挡层。
10.根据权利要求9所述的改善IGBT器件铝穿通缺陷的方法,其特征在于,刻蚀去除所述铝层/所述铝合金层、所述钨层及所述金属阻挡层的方法包括干法刻蚀或湿法刻蚀。
CN202211314707.0A 2022-10-25 2022-10-25 改善igbt器件铝穿通缺陷的方法 Pending CN115527855A (zh)

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