CN115498993A - Circuit capable of reducing static power consumption of load switch chip and on-load power of switch tube - Google Patents
Circuit capable of reducing static power consumption of load switch chip and on-load power of switch tube Download PDFInfo
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- CN115498993A CN115498993A CN202110678528.4A CN202110678528A CN115498993A CN 115498993 A CN115498993 A CN 115498993A CN 202110678528 A CN202110678528 A CN 202110678528A CN 115498993 A CN115498993 A CN 115498993A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The circuit can reduce the static power consumption of the load switch chip and the on-load power of the switch tube, and can reduce the static power consumption of the chip after the drain-source voltage difference of the switch tube is small. Meanwhile, as a load switch chip, the invention can limit the loading capacity of the switch tube when the drain-source pressure difference is larger, thereby reducing the power of the switch tube and realizing the function of protecting the switch tube. Under the condition of realizing the same function, the number of required devices is less, and the area is saved; when the chip does not generate the need of frequency reduction, the branch circuit where the zeroth NMOS transistor Mn0 and the first NMOS transistor Mn1 are located does not consume current, and it is not necessary to provide current for each branch circuit to ensure normal function as in the conventional comparator. And when the need of frequency reduction occurs, the power consumption of the whole structure is limited by the zeroth resistor R0 and the first resistor R1, and the requirement of low power consumption of the chip can be met compared with the traditional comparison structure.
Description
Technical Field
The invention relates to a microelectronic integrated circuit technology, in particular to a circuit capable of reducing static power consumption of a load switch chip and on-load power of a switch tube.
Background
Fig. 1 shows an internal driving and current limiting protection structure of a conventional load switch. When the voltage difference between the IN and OUT of the switch tube is large or the IN and OUT are nearly equal, the Oscillator (OSC) drives the driver (driver) at a fixed frequency and then drives the gate (gate) of the switch tube. However, the chip is subject to OUT start-up time requirements, resulting in higher OSC frequencies being generally designed. When the gate of the switch is driven to a high level to make IN and OUT approximately equal, the OSC has a small meaning if the OSC maintains a high frequency, and the high frequency of the OSC introduces extra static power consumption, so that the chip is not suitable for a scenario with low static power consumption requirement.
When the overcurrent protection function is integrated in the chip, when the current of the load end exceeds the overcurrent protection threshold value, the EA output end pulls down the gate to realize the protection effect. However, IN the on-load starting process of the switching tube, when the voltage difference between IN and OUT is large, if the current-limiting threshold is still maintained unchanged, the switching tube will bear high power, and the risk of damage is extremely high, as illustrated IN the following: assuming IN =5V and an overcurrent protection threshold of 7A, if the chip strip 5A load is started, the power of the switching tube is about 25W, which is fatal to the switching tube itself.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a circuit capable of reducing the static power consumption of a load switch chip and the on-load power of a switch tube.
The invention adopts the following technical scheme:
can reduce the circuit of load switch chip static power consumption and switch tube on-load power, including inside drive and current-limiting protection structure and can reduce the circuit of load switch chip static power consumption and switch tube on-load power, its characterized in that:
the internal driving and current-limiting protection structure comprises an oscillator, a driver, an input voltage end IN, a main current end Iset, a power NMOS tube Mnpwr, a detection resistor Rsns, a main resistor Rset, a load circuit current Iload, a detection NMOS tube Mnsns and a circuit operational amplifier EA of an original chip;
the circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube comprises a first PMOS tube Mp1, a secondary current source Iset1, a zeroth PMOS tube Mp0, a zeroth resistor R0, a first resistor R1, a zeroth NMOS tube Mn0, a bias current Ib, an operational amplifier 2, a first sink node A, a second sink node B and a first NMOS tube Mn1;
the input voltage end IN is connected to the first PMOS tube Mp1, and is connected to the grid electrode of the zeroth PMOS tube Mp0 and the bias current Ib.
The drain electrode of the first PMOS tube Mp1 is connected with a secondary current source Iset1, and the grid electrode of the first PMOS tube Mp1 and the output of the operational amplifier 2 are converged at a second convergence node B.
The secondary current source Iset1 is connected to the primary current source Iset.
The second sink node B is connected to the oscillator.
The source electrode of the zeroth PMOS tube Mp0 is connected to a zeroth resistor R0, the other end of the zeroth resistor R0 is connected to the gate of the switching tube of the chip, and the drain electrode of the zeroth PMOS tube Mp0 is connected to a zeroth NMOS tube Mn0.
The drain electrode of the zeroth NMOS tube Mn0 is grounded, and the grid electrode is connected with the source electrode.
The bias current Ib and the input of the operational amplifier 2 are converged at a first convergence node A; the first sink node A is connected with the drain electrode of the first NMOS tube Mn1, the source electrode of the first NMOS tube Mn1 is connected to the first resistor R1, and the other end of the first resistor R1 is grounded; the grid electrode of the first NMOS transistor Mn1 is connected with the grid electrode of the zeroth NMOS transistor Mn0.
The grid electrode of the first NMOS tube Mn1 is connected with the grid electrode of the zeroth NMOS tube Mn0.
When the output of the second sink node B point is high level, the overcurrent protection threshold is shown by the following formula:
wherein Ilim is the overcurrent protection threshold value when the output of the second sink node B point is high level, R SNS Is a sense resistor in the chip, R MnSNS Is the resistance, R, of a sense NMOS transistor in a chip MnPWR Is the resistance of the power NMOS tube Mnpwr in the chip.
When the output of the second sink node B point is low, the overcurrent protection threshold is as follows:
wherein Ilim' is an overcurrent protection threshold value when the output of the second sink node B is low level.
Compared with the prior art, the invention has the beneficial effect that for the load switch type chip with low power consumption requirement, the static power consumption of the chip can be reduced after the drain-source voltage difference of the switch tube is smaller. Meanwhile, as a load switch chip, the invention can limit the loading capacity of the switch tube when the drain-source pressure difference is larger, thereby reducing the power of the switch tube and realizing the function of protecting the switch tube. Under the condition of realizing the same function, the number of required devices is less, and the area is saved; when the chip does not generate the need of frequency reduction, the branches in which Mn0 and Mn1 are located consume no current, and it is not necessary to provide current for each branch to ensure normal function, as in the conventional comparator. And when the need of frequency reduction occurs, the power consumption of the whole structure is limited by R0 and R1, and the structure can better adapt to the requirement of low power consumption of a chip compared with the traditional comparison structure.
Drawings
FIG. 1 illustrates a prior art internal drive and current limiting protection architecture for a load switch;
FIG. 2 is a circuit diagram of the present invention for reducing the static power consumption of the load switch chip and the on-load power of the switch tube.
The reference numbers are listed below:
IN-input voltage terminal;
OUT-output voltage terminal;
gate-switching tube grid;
mnpwr-power NMOS tube;
iload-load circuit current;
rsns-sense resistance;
mnsns-detecting NMOS tube;
EA-circuit operational amplifier;
rset — main resistance;
iset — main current source;
mp 1-first PMOS tube;
iset 1-secondary current source;
r0-zeroth resistance;
mp 0-zeroth PMOS tube;
mn 0-zeroth NMOS tube;
ib-bias current;
mn 1-first NMOS tube;
r1-a first resistance;
2-an operational amplifier;
a-a first sink node;
b-a second sink node;
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.
Fig. 2 is a schematic circuit diagram of a circuit for reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to the present invention, which includes an internal driving and current-limiting protection structure of the chip and a circuit for reducing the static power consumption of the load switch chip and the on-load power of the switch tube. The internal driving and current-limiting protection structure comprises an oscillator, a driver, an input voltage end IN, a main current end Iset, a power NMOS tube Mnpwr, a detection resistor Rsns, a main resistor Rset, a load circuit current Iload, a detection NMOS tube Mnsns and a circuit operational amplifier EA of an original chip.
The concrete connection mode is as follows: a voltage end IN is connected with a Mnpwr drain electrode of a power NMOS tube, a detection resistor Rsns and a main resistor Rset; the detection resistor Rsns is connected with a drain electrode of the detection NMOS tube Mnsns, the main resistor Rset is connected with a negative electrode of the operational amplifier EA of the circuit and a main current end Iset, and the other end of the main current end Iset is grounded; the source electrode of the power NMOS tube Mnpwr and the source electrode of the detection NMOS tube Mnsns are connected with a load circuit current Iload, and the other end of the load circuit current Iload is grounded; the drain electrode of the detection NMOS tube Mnsns is connected with the anode of the operational amplifier EA of the circuit; the grid electrode of the power NMOS tube Mnpwr, the grid electrode of the detection NMOS tube Mnsns and the output of the circuit operational amplifier EA are converged at the grid electrode gate of the switching tube.
The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube comprises circuit elements of a first PMOS tube Mp1, a secondary current source Iset1, a zeroth PMOS tube Mp0, a zeroth resistor R0, a first resistor R1, a zeroth NMOS tube Mn0, a bias current Ib, an operational amplifier 2 and a first NMOS tube Mn 1.
The specific connection method comprises the following steps: a first PMOS tube Mp1 is connected to an input voltage end IN; the drain electrode of the first PMOS tube Mp1 is connected with a secondary current source Iset1, and the grid electrode and the output of the operational amplifier 2 are converged at a second convergence node B; the secondary current source Iset1 is connected with Iset; the second sink node B is connected with the oscillator;
the grid electrode of a zeroth PMOS tube Mp0 is connected to the input voltage end IN, the source electrode of the zeroth PMOS tube Mp0 is connected to a zeroth resistor R0, the other end of the zeroth resistor R0 is connected to the grid electrode gate of a switch tube of the chip, and the drain electrode of the zeroth PMOS tube Mp0 is connected to a zeroth NMOS tube Mn0; the drain electrode of the zeroth NMOS tube Mn0 is grounded, and the grid electrode is connected with the source electrode;
the input voltage end IN is simultaneously connected with a bias current Ib, and the bias current Ib and the input of the operational amplifier 2 are converged at a first convergence node A; the first sink node A is connected with the drain electrode of the first NMOS tube Mn1, the source electrode of the first NMOS tube Mn1 is connected to the first resistor R1, and the other end of the first resistor R1 is grounded; the grid electrode of the first NMOS transistor Mn1 is connected with the grid electrode of the zeroth NMOS transistor Mn0.
When the switch tube is started, V is gate -V IN -V gsp0 When the voltage of the point A of the first sink node is pulled up to be close to the potential of IN, B outputs low level, the high frequency initially set by the oscillator cannot be influenced, and if the voltage of the point B of the second sink node is high level, the frequency of the oscillator can be reduced. V gate Denotes the voltage at gate, V IN Representing the input voltage, V gsp0 The voltage between the source and the gate of the zeroth PMOS tube Mp0 is shown. Because the point B of the second sink node outputs low level, the first PMOS tube Mp1 is conducted, and the current on the main resistor Rset is reduced from the original Iset to Iset-Iset1. When the output of the second sink node B is at a high level, the overcurrent protection threshold is as follows:
wherein Ilim is the overcurrent protection threshold value when the output of the second sink node (B) point is high level, R SNS Is a sense resistor in the chip, R MnSNS Is the resistance, R, of the NMOS tube in the chip MnPWR Is in a chipThe resistance of a power NMOS tube Mnpwr;
when the output of the second sink node B point is low, the overcurrent protection threshold is as follows:
wherein Ilim' is the overcurrent protection threshold when the second sink node (B) point output is low.
Let Iset1=50% Iset, it can be seen from the above two equations that Ilim is reduced to the previous 50% during the switching tube start-up, and the limiting power at the switching tube start-up is reduced by 50%, which serves as a protection for the switching tube.
Under the driving action of the driver, V gate Gradually increasing when the gate voltage and the IN voltage of the switching tube satisfy the following formula: v gate -V IN -V gsp0 Greater than 0 or V gate ＞V IN +V gsp0 Voltage drop is generated at two ends of R0, and current flows through Mn0 to conduct the voltage drop; at this time, the voltage V at OUT can be known OUT Comprises the following steps: v OUT ＝V gate -V gs_Mnpwr ＞V IN +V gsp0 -V gs_Mnpwr ，V gs_Mnpwr The gate-source voltage difference of the power NMOS tube is shown. From this formula, V can be known OUT And V IN The voltages are already very close. With gate voltage V gate Continuously rising, the grid-source voltage difference V of the zeroth NMOS tube Mn0 gsn0 And the voltage gradually increases, and finally the first NMOS transistor Mn1 is switched on, and a current flows through the first resistor R1, wherein the current is equal to
V gsn1 The gate-source voltage difference of the first NMOS transistor Mn 1. When the current is larger than the bias current Ib, the voltage at the point A of the first sink node is pulled down to a low level (approximately equal to 0), and the voltage at the point B of the second sink node is overturned to be close to the voltage V of the IN node IN High level of (c). The second sink node B can convert the clock frequency generated by the oscillator from high frequency to low frequency after being overturned, so that the static power consumption consumed by the oscillator and the driver is reduced, and finally the OUT connection is realizedThe effect of reducing the static power consumption of the chip after approaching IN. Moreover, the overcurrent protection threshold of the switching tube is restored to the following formula:
the present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are merely preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for limiting the scope of the present invention, and on the contrary, any improvement or modification made based on the spirit of the present invention should fall within the scope of the present invention.
Claims (10)
1. Can reduce load switch chip static power consumption and switch tube power-on-load's circuit, including inside drive and current-limiting protection structure and can reduce load switch chip static power consumption and switch tube power-on-load's circuit, its characterized in that:
the internal driving and current-limiting protection structure comprises an oscillator, a driver, an input voltage end (IN), a main current end (Iset), a power NMOS (Mnpwr), a detection resistor (Rsns), a main resistor (Rset), a load circuit current (Iload), a detection NMOS (Mnsns) and a circuit operational amplifier (EA) of an original chip;
the circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube comprises a first PMOS tube (MP 1), a secondary current source (Iset 1), a zeroth PMOS tube (MP 0), a zeroth resistor (R0), a first resistor (R1), a zeroth NMOS tube (Mn 0), a bias current (Ib), an operational amplifier (2), a first aggregation node (A), a second aggregation node (B) and a first NMOS tube (Mn 1);
the input voltage end (IN) is connected to the first PMOS tube (Mp 1) and the grid electrode of the zeroth PMOS tube (Mp 0) at the same time, and the bias current (Ib) is connected to the input voltage end (IN).
2. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 1, wherein:
the drain electrode of the first PMOS tube (Mp 1) is connected with a secondary current source (Iset 1), and the grid electrode of the first PMOS tube and the output of the operational amplifier (2) are converged at a second convergence node (B).
3. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 2, wherein:
the secondary current source (Iset 1) is connected to the primary current source (Iset).
4. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 2 or 3, wherein:
the second sink node (B) is connected to an oscillator.
5. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 4, wherein:
the source electrode of the zeroth PMOS tube (Mp 0) is connected to a zeroth resistor (R0), the other end of the zeroth resistor (R0) is connected to the gate (gate) of the switch tube of the chip, and the drain electrode of the zeroth PMOS tube (Mp 0) is connected to the zeroth NMOS tube (Mn 0).
6. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 5, wherein:
and the drain electrode of the zeroth NMOS tube (Mn 0) is grounded, and the grid electrode of the zeroth NMOS tube is connected with the source electrode.
7. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 1 or 6, wherein:
the bias current (Ib) and the input of the operational amplifier (2) are converged at a first convergence node (A); the first sink node (A) is connected with the drain electrode of the first NMOS tube (Mn 1), the source electrode of the first NMOS tube (Mn 1) is connected to the first resistor (R1), and the other end of the first resistor (R1) is grounded; the grid electrode of the first NMOS tube (Mn 1) is connected with the grid electrode of the zeroth NMOS tube (Mn 0).
8. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 7, wherein:
the grid electrode of the first NMOS tube (Mn 1) is connected with the grid electrode of the zeroth NMOS tube (Mn 0).
9. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 1 or 8, wherein:
when the output of the second sink node (B) is at a high level, the overcurrent protection threshold is as follows:
wherein Ilim is the overcurrent protection threshold value when the output of the second sink node (B) point is high level, R SNS Is a sense resistor in the chip, R MnSNS Is the resistance, R, of a sense NMOS transistor in a chip MnPWR Is the resistance of the power NMOS tube Mnpwr in the chip.
10. The circuit capable of reducing the static power consumption of the load switch chip and the on-load power of the switch tube according to claim 9, wherein:
when the output of the second sink node (B) is low, the overcurrent protection threshold is as follows:
wherein Ilim' is the overcurrent protection threshold when the output of the second sink node (B) point is at a low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110678528.4A CN115498993A (en) | 2021-06-18 | 2021-06-18 | Circuit capable of reducing static power consumption of load switch chip and on-load power of switch tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110678528.4A CN115498993A (en) | 2021-06-18 | 2021-06-18 | Circuit capable of reducing static power consumption of load switch chip and on-load power of switch tube |
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| Publication Number | Publication Date |
|---|---|
| CN115498993A true CN115498993A (en) | 2022-12-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110678528.4A Pending CN115498993A (en) | 2021-06-18 | 2021-06-18 | Circuit capable of reducing static power consumption of load switch chip and on-load power of switch tube |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116346113A (en) * | 2023-05-23 | 2023-06-27 | 晶艺半导体有限公司 | High-precision current-controlled load switch circuit and trimming method thereof |
-
2021
- 2021-06-18 CN CN202110678528.4A patent/CN115498993A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116346113A (en) * | 2023-05-23 | 2023-06-27 | 晶艺半导体有限公司 | High-precision current-controlled load switch circuit and trimming method thereof |
| CN116346113B (en) * | 2023-05-23 | 2023-08-11 | 晶艺半导体有限公司 | High-precision current-controlled load switch circuit and trimming method thereof |
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