CN115498859A - Power supply control circuit based on peak current mode - Google Patents

Power supply control circuit based on peak current mode Download PDF

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Publication number
CN115498859A
CN115498859A CN202211160507.4A CN202211160507A CN115498859A CN 115498859 A CN115498859 A CN 115498859A CN 202211160507 A CN202211160507 A CN 202211160507A CN 115498859 A CN115498859 A CN 115498859A
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CN
China
Prior art keywords
mos switch
circuit
control circuit
output
comparator
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Pending
Application number
CN202211160507.4A
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Chinese (zh)
Inventor
解建章
赵波
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Shanghai Southchip Semiconductor Technology Co Ltd
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Shanghai Southchip Semiconductor Technology Co Ltd
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Priority to CN202211160507.4A priority Critical patent/CN115498859A/en
Publication of CN115498859A publication Critical patent/CN115498859A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a power supply control circuit based on a peak current mode, which comprises: the circuit comprises a power level circuit, a first comparator, a second comparator, a differential amplifier, a current control delay circuit, a logic control circuit, a V/I conversion circuit, a Timer circuit, an output resistor and an output capacitor. The invention can realize the linear regulation of the output signal T1 of the Timer circuit along with the load change, and the lighter the load is, the shorter the interval time is. Since the charge to VOUT decreases with decreasing load for a single cycle, the voltage ripple at VOUT and VC nodes no longer need to be reduced by large capacitors, and the loop response speed increases accordingly.

Description

Power supply control circuit based on peak current mode
Technical Field
The invention relates to the technical field of power management, in particular to a power control circuit based on a peak current mode.
Background
BUCK-BOOST is a short for inductance type switch BUCK-BOOST DCDC voltage stabilizer. The basic principle is shown in fig. 1. The switch ABCD and the inductor IND constitute a power stage circuit. The Control Circuit (Control Circuit) makes the ABCD work alternately according to a certain time sequence, and utilizes the inductance of the energy storage element to move the energy from the input VIN to output VOUT. The voltage regulator can keep VOUT constant no matter VIN is larger than, equal to or smaller than VOUT.
When VIN > VOUT, the switch D is always conducted, C is always turned off, the switch AB is alternately conducted and turned off, and the power supply control circuit works in a voltage reduction mode (BUCK mode); when VIN < < VOUT, the switch A is always conducted, the switch B is always turned off, the switch CD is alternately conducted and turned off, and the power supply control circuit works in a boosting mode (BOOST mode). When VIN is close to VOUT, the switch ABCD is required to be turned on alternately according to a specific timing sequence, and the power control circuit operates in a BUCK-BOOST mode (BUCK-BOOST mode). Voltage regulators in BUCK mode (BUCK mode) and BOOST mode (BOOST mode) are technically mature, and the technical difficulty of BUCK-BOOST is how to implement BUCK-BOOST mode (BUCK-BOOST mode).
In order to improve the efficiency under light load, the DCDC needs a specially designed light load operation mode. When the load is heavy, the power supply control circuit works in a Continuous Conduction (CCM) mode; when the load is low to a certain degree, the power control circuit can automatically enter a light load mode. In a CCM mode, the DCDC keeps the working frequency unchanged, the voltage stabilization of VOUT is realized by adjusting the duty ratio of a power switch, and the inductive current linearly changes along with the load; in the light load mode, the inductor current in each switching period is not reduced any more, and the power level circuit keeps the voltage stabilization of VOUT through intermittent operation.
Under the condition that VIN is greater than VOUT and light load is carried out, excessive charges which are not controlled by a loop circuit are charged to VOUT in the T1 stage in a single working period, large ripples are introduced into the VOUT end to cause the VC end to generate large ripples, and a stable working point is difficult to find by a single-pulse control loop, so that the loop circuit is unstable; in order to suppress the instability, a large capacitor must be added to the nodes VOUT and VC to reduce the effect of ripple. Due to the large capacitance introduced in the feedback loop, the loop response speed may be slow and the application cost may be increased.
Disclosure of Invention
In order to solve the above problems, the present invention provides a power control circuit based on a peak current mode.
In order to achieve the purpose, the invention provides the following scheme:
a peak current mode based power control circuit comprising: the circuit comprises a power level circuit, a first comparator, a second comparator, a differential amplifier, a current control delay circuit, a logic control circuit, a V/I conversion circuit, a Timer circuit, an output resistor and an output capacitor;
the input end of the power level circuit is connected with an input voltage, and the output end of the power level circuit is respectively connected with one end of the output resistor, one end of the output capacitor, the input end of the second comparator and the reverse input end of the differential amplifier; the other end of the output resistor and the other end of the output capacitor are both grounded; the output end of the second comparator is connected with the input end of the logic control circuit; the inverting input end of the differential amplifier is connected with a reference voltage, and the output end of the differential amplifier is connected with the input end of the V/I conversion circuit; the output end of the V/I conversion circuit is respectively connected with the reverse input end of the first comparator and the input end of the current control delay circuit; the output end of the current control delay circuit is connected with the input end of the logic control circuit; the positive input end of the first comparator is connected with the power level circuit, and the output end of the first comparator is connected with the input end of the logic control circuit; the input end of the logic control circuit is also connected with the output end of the Timer circuit, and the output end of the logic control circuit is connected with the power level circuit; the input of the Timer circuit is connected with the input voltage and the output voltage.
Optionally, the power stage circuit includes a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch, and an energy storage inductor;
the source electrode of the first MOS switch is the input end of the power stage circuit, and the drain electrode of the first MOS switch is respectively connected with the drain electrode of the second MOS switch, one end of the inductor and the positive input end of the first comparator; the source electrode of the second MOS switch is grounded; the other end of the inductor is connected with the drain electrode of the third MOS switch, the drain electrode of the fourth MOS switch and the reverse input end of the second comparator respectively; the source electrode of the third MOS switch is grounded; the source electrode of the fourth MOS switch is connected with the positive input end of the second comparator; and the grid electrode of the first MOS switch, the grid electrode of the second MOS switch, the grid electrode of the third MOS switch and the grid electrode of the fourth MOS switch are all connected with the output end of the logic control circuit.
Optionally, in a heavy load condition, the power control circuit operates in a CCM mode; as the load becomes lower, the power control circuit operates in DCM; under the condition of light load, the power supply control circuit works in a single-pulse light load mode.
Optionally, when the power control circuit operates in a CCM mode, the logic control circuit controls the on-times of the first MOS switch, the second MOS switch, the third MOS switch, and the fourth MOS switch according to the output of the first comparator and the output of the Timer circuit;
when the power supply control circuit is in a DCM mode, the logic control circuit controls the conduction time of the first MOS switch, the second MOS switch, the third MOS switch and the fourth MOS switch according to the output of the second comparator and the output of the Timer circuit;
when the power supply control circuit works in a single-pulse light-load mode, the logic control circuit controls the conduction time of the first MOS switch, the second MOS switch, the third MOS switch and the fourth MOS switch according to the output of the current control delay circuit.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a power supply control circuit based on a peak current mode, which comprises: the circuit comprises a power level circuit, a first comparator, a second comparator, a differential amplifier, a current control delay circuit, a logic control circuit, a V/I conversion circuit, a Timer circuit, an output resistor and an output capacitor. The invention can realize the linear adjustment of the output signal T1 of the Timer circuit along with the load change, and the lighter the load is, the shorter the interval time is. Since the charge to VOUT decreases with decreasing load for a single cycle, the voltage ripple at VOUT and VC nodes no longer need to be reduced by large capacitors, and the loop response speed increases accordingly.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of BUCK-BOOST;
FIG. 2 is a schematic diagram of a peak current mode-based power control circuit provided by the present invention;
FIG. 3 is a timing diagram of CCM mode at heavy load;
FIG. 4 is a timing diagram for DCM mode with a light load;
FIG. 5 is a timing diagram for the single pulse mode with very light loads.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 2, the power control circuit based on the peak current mode provided in this embodiment includes: the circuit comprises a power stage circuit (in a dashed line frame), a first comparator COMP1, a second comparator COMP2, a differential amplifier Gm, a current control delay circuit TPFM, a Logic control circuit Logic, a V/I conversion circuit, a Timer circuit, an output resistor Rout and an output capacitor Cout.
The input end of the power stage circuit is connected with the input voltage VIN, and the output end of the power stage circuit is respectively connected with one end of the output resistor Rout, one end of the output capacitor Cout, the input end of the second comparator COMP2 and the reverse input end of the differential amplifier Gm; the other end of the output resistor Rout and the other end of the output capacitor Cou are grounded; the output end of the second comparator COMP2 is connected with the input end of the Logic control circuit Logic; the reverse input end of the differential amplifier Gm is connected with the reference voltage VREF, and the output end of the differential amplifier Gm is connected with the input end of the V/I conversion circuit; the output end of the V/I conversion circuit is respectively connected with the reverse input end of the first comparator COMP1 and the input end of the current control delay circuit TPFM; the output end of the current control delay circuit TPFM is connected with the input end of the Logic control circuit Logic; the positive input end of the first comparator COMP1 is connected with the power stage circuit, and the output end of the first comparator COMP1 is connected with the input end of the Logic control circuit Logic; the input end of the Logic control circuit Logic is also connected with the output end of the Timer circuit, and the output end of the Logic control circuit Logic is connected with the power level circuit; the Timer circuit has inputs connected to an input voltage VIN and an output voltage VOUT.
As shown in fig. 2, the power stage circuit provided in this embodiment includes a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch, and an energy storage inductor;
the source electrode of the first MOS switch is the input end of the power stage circuit, and the drain electrode of the first MOS switch is respectively connected with the drain electrode of the second MOS switch, one end of the inductor and the positive input end of the first comparator; the source electrode of the second MOS switch is grounded; the other end of the inductor is connected with the drain electrode of the third MOS switch, the drain electrode of the fourth MOS switch and the reverse input end of the second comparator respectively; the source electrode of the third MOS switch is grounded; the source electrode of the fourth MOS switch is connected with the positive input end of the second comparator; the grid electrode of the first MOS switch, the grid electrode of the second MOS switch, the grid electrode of the third MOS switch and the grid electrode of the fourth MOS switch are all connected with the output end of the logic control circuit.
In the embodiment, a delay circuit is added in the TPFM circuit, the delay time is reduced along with the reduction of the IPFM, and the signal pulse T1_2 is generated after the delay is finished. The shortest time of the delay is set to T1_ MIN. In the Logic control circuit Logic, the working time of the stage T1 is determined by the timing of the first arrival of T1 and T1_2.
Under heavy load, the Vc voltage is relatively high, so that both IPFM and IC are relatively large. The interval time T1_2 generated by the TPFM is larger than the T1 generated by the Timer circuit, and the interval time T3 generated by the TPFM is smaller than the switching period set by the T1 and the T2. PWM, T1 and T2 together control the conduction time of switch ABCD to achieve the voltage stabilization of VOUT. The power control circuit operates in CCM mode, the timing for which is shown in fig. 3.
As the load becomes lower, the Vc voltage gradually decreases until the inductor current does not decrease for each switching cycle after the IC is clamped at the minimum current value. IPFM continues to decrease as Vc decreases, and the interval T1_2 of TPFM generation gradually decreases. When T1_2 is smaller than T1, the working time of the T1 stage starts to decrease. At this time, T3 is still less than the switching period set by T1 and T2. PWM, T1, T2 and ZCD jointly control a switch ABCD to realize the voltage stabilization of VOUT. The power control circuit operates in DCM, the timing for this case being shown in fig. 4.
As the load goes further low, the Vc voltage decreases until T1_2 is clamped at T1_ MIN, and the operating time of the T1 phase does not decrease. IPFM continues to decrease as Vc decreases and the interval between TPFM generation gradually increases. When the interval time is longer than the switching period set by T1 and T2, the working period of the switching action is determined by the T3 signal. The power control circuit automatically enters the single pulse light load mode, and the timing sequence in this case is shown in fig. 5.
Under the light load condition, the holding time of the T1 stage is reduced along with the reduction of the load, the charge of VOUT in a single period is linearly reduced, and the ripple voltage at the VOUT end is always small. And when the T1 is reduced to the set minimum value, the T3 is extended again, so that the pause time is gradually prolonged.
In the power control circuit provided by this embodiment, the feedback control Vc signal is used to modulate the interval time of T1, so as to realize linear adjustment of T1 with load variation. The lighter the load, the shorter the interval time.
Because the charge to VOUT decreases as the load decreases for a single cycle, the voltage ripple at VOUT and VC nodes no longer need to be reduced by large capacitors, and the loop response speed increases accordingly.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (4)

1. A peak current mode based power control circuit, comprising: the circuit comprises a power level circuit, a first comparator, a second comparator, a differential amplifier, a current control delay circuit, a logic control circuit, a V/I conversion circuit, a Timer circuit, an output resistor and an output capacitor;
the input end of the power level circuit is connected with an input voltage, and the output end of the power level circuit is respectively connected with one end of the output resistor, one end of the output capacitor, the input end of the second comparator and the reverse input end of the differential amplifier; the other end of the output resistor and the other end of the output capacitor are both grounded; the output end of the second comparator is connected with the input end of the logic control circuit; the inverting input end of the differential amplifier is connected with a reference voltage, and the output end of the differential amplifier is connected with the input end of the V/I conversion circuit; the output end of the V/I conversion circuit is respectively connected with the reverse input end of the first comparator and the input end of the current control delay circuit; the output end of the current control delay circuit is connected with the input end of the logic control circuit; the positive input end of the first comparator is connected with the power level circuit, and the output end of the first comparator is connected with the input end of the logic control circuit; the input end of the logic control circuit is also connected with the output end of the Timer circuit, and the output end of the logic control circuit is connected with the power level circuit; the input of the Timer circuit is connected with the input voltage and the output voltage.
2. The peak-current-mode-based power control circuit of claim 1, wherein the power stage circuit comprises a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch, and an energy storage inductor;
the source electrode of the first MOS switch is the input end of the power stage circuit, and the drain electrode of the first MOS switch is respectively connected with the drain electrode of the second MOS switch, one end of the inductor and the positive input end of the first comparator; the source electrode of the second MOS switch is grounded; the other end of the inductor is connected with the drain electrode of the third MOS switch, the drain electrode of the fourth MOS switch and the reverse input end of the second comparator respectively; the source electrode of the third MOS switch is grounded; the source electrode of the fourth MOS switch is connected with the positive input end of the second comparator; and the grid electrode of the first MOS switch, the grid electrode of the second MOS switch, the grid electrode of the third MOS switch and the grid electrode of the fourth MOS switch are all connected with the output end of the logic control circuit.
3. The peak-current-mode-based power control circuit of claim 2, wherein under heavy load conditions, the power control circuit operates in CCM mode; when the heavy load condition is converted into the light load condition, the power supply control circuit works in a DCM (discontinuous conduction mode); under the condition of light load, the power supply control circuit works in a single-pulse light load mode.
4. The peak-current-mode-based power control circuit according to claim 3, wherein when the power control circuit operates in CCM mode, the logic control circuit controls the conduction time of the first MOS switch, the second MOS switch, the third MOS switch and the fourth MOS switch according to the output of the first comparator and the output of the Timer circuit;
when the power supply control circuit is in a DCM mode, the logic control circuit controls the conduction time of the first MOS switch, the second MOS switch, the third MOS switch and the fourth MOS switch according to the output of the second comparator and the output of the Timer circuit;
when the power supply control circuit works in a single-pulse light-load mode, the logic control circuit controls the conduction time of the first MOS switch, the second MOS switch, the third MOS switch and the fourth MOS switch according to the output of the current control delay circuit.
CN202211160507.4A 2022-09-22 2022-09-22 Power supply control circuit based on peak current mode Pending CN115498859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211160507.4A CN115498859A (en) 2022-09-22 2022-09-22 Power supply control circuit based on peak current mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211160507.4A CN115498859A (en) 2022-09-22 2022-09-22 Power supply control circuit based on peak current mode

Publications (1)

Publication Number Publication Date
CN115498859A true CN115498859A (en) 2022-12-20

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211160507.4A Pending CN115498859A (en) 2022-09-22 2022-09-22 Power supply control circuit based on peak current mode

Country Status (1)

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CN (1) CN115498859A (en)

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