CN115498861A - Power supply control circuit based on peak-valley current mode - Google Patents

Power supply control circuit based on peak-valley current mode Download PDF

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Publication number
CN115498861A
CN115498861A CN202211160067.2A CN202211160067A CN115498861A CN 115498861 A CN115498861 A CN 115498861A CN 202211160067 A CN202211160067 A CN 202211160067A CN 115498861 A CN115498861 A CN 115498861A
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CN
China
Prior art keywords
comparator
mos switch
control circuit
output
input end
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Pending
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CN202211160067.2A
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Chinese (zh)
Inventor
解建章
张�杰
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Shanghai Southchip Semiconductor Technology Co Ltd
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Shanghai Southchip Semiconductor Technology Co Ltd
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Priority to CN202211160067.2A priority Critical patent/CN115498861A/en
Publication of CN115498861A publication Critical patent/CN115498861A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters

Abstract

The invention discloses a power supply control circuit based on a peak-valley current mode, which comprises: the circuit comprises a power level circuit, a differential amplifier, a first comparator, a Timer circuit, a logic control circuit, an output resistor, an output capacitor and a sampling resistor; the input end of the power level circuit is connected with the input voltage, and the output end of the power level circuit is respectively connected with one end of the output resistor, one end of the output capacitor, one end of the sampling resistor and the reverse input end of the differential amplifier; one end of the sampling resistor is also connected with the positive input end of the first comparator; the input of the positive input end of the differential amplifier is a reference voltage, and the output end of the differential amplifier is connected with the reverse input end of the first comparator; the output end of the first comparator is connected with the input end of the logic control circuit; the input end of the logic control circuit is also connected with the output end of the Timer circuit, and the output end of the logic control circuit is connected with the power level circuit; the input end of the Timer circuit is connected with the input voltage and the output voltage. The invention can avoid the problems of output voltage undershoot and overshoot caused by mode switching.

Description

Power supply control circuit based on peak-valley current mode
Technical Field
The invention relates to the technical field of power management, in particular to a power control circuit based on a peak-valley current mode.
Background
BUCK-BOOST is a short for inductance type switch BUCK-BOOST DCDC voltage stabilizer. The basic principle of the power amplifier is as shown in fig. 1, a power stage Circuit is composed of an MOS switch ABCD and an inductor, the switch ABCD is made to alternately operate according to a certain time sequence by a Control Circuit (Control Circuit), and energy is transferred from an input VIN to an output VOUT by using an energy storage element inductor while an output voltage VOUT is kept constant; compared with other types of DCDC voltage regulators, the output voltage of the BUCK-BOOST can be larger than, smaller than or equal to the input voltage. The technology is widely applied in the application scene of battery power supply.
When VIN > VOUT, D keeps long conduction, C keeps long off, A and B are conducted alternately, and BUCK-BOOST works in a simple voltage reduction mode (BUCK mode); when VIN < < VOUT, A keeps long conduction, B keeps long off, C and D are alternately conducted, and BUCK-BOOST works in a simple boosting mode (BOOST mode). The voltage reduction mode and the voltage boosting mode can normally work only within a certain VOUT/VIN proportion range, and when VIN is close to VOUT, a special voltage reduction mode (BUCK-BOOST mode) needs to be designed to ensure that ABCD works in a matched mode, so that the constant of VOUT can be realized.
The existing scheme is that near the switching point of a BUCK mode and a BUCK-BOOST mode, when the BUCK mode is adopted, the average value of current output to VOUT is smaller than the peak current actually controlled by a loop; in BUCK-BOOST mode, the average value of the current output to VOUT is larger than the peak current actually controlled by the loop. When the mode is switched, the working point of the loop cannot change suddenly, so that the voltage overshoot appears at the VOUT end when the BUCK mode is switched to the BUCK-BOOST mode; a voltage undershoot occurs at the VOUT terminal when the BUCK-BOOST mode is switched to the BUCK mode.
Disclosure of Invention
In order to solve the above problems, the present invention provides a power control circuit based on a peak-to-valley current mode.
In order to achieve the purpose, the invention provides the following scheme:
a power supply control circuit based on a peak-to-valley current mode, comprising: the circuit comprises a power level circuit, a differential amplifier, a first comparator, a Timer circuit, a logic control circuit, an output resistor, an output capacitor and a sampling resistor;
the input end of the power level circuit is connected with an input voltage, and the output end of the power level circuit is respectively connected with one end of the output resistor, one end of the output capacitor, one end of the sampling resistor and the reverse input end of the differential amplifier; the other end of the output resistor and the other end of the output capacitor are grounded; one end of the sampling resistor is also connected with the positive input end of the first comparator, and the other end of the sampling resistor is grounded; the input of the positive input end of the differential amplifier is a reference voltage, and the output end of the differential amplifier is connected with the reverse input end of the first comparator; the output end of the first comparator is connected with the input end of the logic control circuit; the input end of the logic control circuit is also connected with the output end of the Timer circuit, and the output end of the logic control circuit is connected with the power level circuit; the input end of the Timer circuit is connected with the input voltage and the output voltage.
Optionally, the power stage circuit includes a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch, and an energy storage inductor;
the source electrode of the first MOS switch is the input end of the power stage circuit, and the drain electrode of the first MOS switch is respectively connected with the drain electrode of the second MOS switch and one end of the energy storage inductor; the source electrode of the second MOS switch is grounded; the other end of the energy storage inductor is connected with the drain electrode of the third MOS switch and the drain electrode of the fourth MOS switch respectively; the source electrode of the third MOS switch is grounded; the source electrode of the fourth MOS switch is the output end of the power level circuit; the drain electrode of the second MOS switch and the drain electrode of the third MOS switch are also connected with one end of the sampling resistor; and the grid electrode of the first MOS switch, the grid electrode of the second MOS switch, the grid electrode of the third MOS switch and the grid electrode of the fourth MOS switch are all connected with the output end of the logic control circuit.
Optionally, the Timer circuit includes a second comparator, a third comparator, a fourth comparator, and an and gate;
the positive direction input end of the second comparator is connected with the output voltage, the reverse direction input end of the second comparator is connected with the input voltage, and the output end of the second comparator is connected with the input end of the logic control circuit; the positive direction input end of the third comparator is connected with the output voltage, the reverse direction input end of the third comparator is connected with the input voltage, and the output end of the third comparator is connected with the first input end of the AND gate; the positive input end of the fourth comparator is connected with the input voltage, the reverse input end of the fourth comparator is connected with the output voltage, and the output end of the fourth comparator is connected with the second input end of the AND gate; and the output end of the AND gate is connected with the input end of the logic control circuit.
Optionally, when VIN > > VOUT, the power control circuit operates in a BUCK mode, and the sampling resistor, the first comparator and the differential amplifier form a valley current mode loop;
when VIN < < VOUT, the power supply control circuit works in a BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop;
when the difference value of VIN and VOUT is within the threshold range, the power supply control circuit works in a BUCK-BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop;
where VIN is the input voltage and VOUT is the output voltage.
Optionally, when the power control circuit operates in a BUCK mode, the third comparator calculates a time for the first MOS switch and the fourth MOS switch to be turned on together, and the valley current mode loop determines the time for the second MOS switch and the fourth MOS switch to be turned on together;
when the power supply control circuit works in a BOOST mode, the fourth comparator calculates the time for the first MOS switch and the fourth MOS switch to be conducted together; determining, by the peak current mode loop, a time for the first MOS switch and the third MOS switch to be turned on together;
when the power supply control circuit works in a BUCK-BOOST mode, the first comparator calculates the time for the second MOS switch and the fourth MOS switch to be conducted together; calculating, by the third comparator and the fourth comparator, a time for which the first MOS switch and the fourth MOS switch are turned on in common; the time for which the first and third MOS switches are turned on together is determined by the peak current mode loop.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the power supply control circuit provided by the invention adopts self-adaptive on-time valley current mode control in the BUCK mode, and adopts self-adaptive off-time peak current mode control in the BUCK-BOOST and the BOOST, so that the problems of undershoot and overshoot of output voltage caused by the fact that the working point of a loop cannot change suddenly in the mode switching process are solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of BUCK-BOOST;
FIG. 2 is a schematic diagram of a peak-to-valley current mode based power control circuit provided in the present invention;
fig. 3 is a schematic diagram of a Timer circuit provided in the present invention;
FIG. 4 is a timing diagram of the switching signal and the inductor current signal in the BUCK mode of operation;
FIG. 5 is a timing diagram of the switch signal and the inductor current signal in the BUCK-BOOST mode of operation;
FIG. 6 is a timing diagram of the switch signal and the inductor current signal in the BOOST operating mode;
FIG. 7 is a waveform diagram when BUCK mode and BUCK-BOOST mode are switched.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 2, the power control circuit based on the peak-to-valley current mode provided in this embodiment includes: the circuit comprises a power stage circuit (a dotted line frame part), a differential amplifier Gm, a first comparator COMP1, a Timer circuit, a Logic control circuit Logic, an output resistor Rout, an output capacitor Cout and a sampling resistor Rsns.
The input end of the power stage circuit is connected with the input voltage VIN, and the output end of the power stage circuit is respectively connected with one end of an output resistor Rout, one end of an output capacitor Cout, one end of a sampling resistor Rsns and the reverse input end of a differential amplifier Gm; the other end of the output resistor Rout and the other end of the output capacitor Cout are grounded; one end of the sampling resistor Rsns is also connected with the positive input end of the first comparator COMP1, and the other end of the sampling resistor Rsns is grounded; the input of the positive input end of the differential amplifier Gm is a reference voltage VREF, and the output end of the differential amplifier Gm is connected with the reverse input end of a first comparator COMP 1; the output end of the first comparator COMP1 is connected with the input end of the Logic control circuit Logic; the input end of the Logic control circuit Logic is also connected with the output end of the Timer circuit, and the output end of the Logic control circuit Logic is connected with the power level circuit; the input end of the Timer circuit is connected with the input voltage VIN and the output voltage VOUT.
As shown in fig. 2, the power stage circuit provided in this embodiment includes a first MOS switch a, a second MOS switch B, a third MOS switch C, a fourth MOS switch D, and an energy storage inductor IND. The source electrode of the first MOS switch A is the input end of the power stage circuit, and the drain electrode of the first MOS switch A is respectively connected with the drain electrode of the second MOS switch B and one end of the energy storage inductor IND; the source electrode of the second MOS switch B is grounded; the other end of the energy storage inductor IND is respectively connected with the drain electrode of the third MOS switch C and the drain electrode of the fourth MOS switch D; the source electrode of the third MOS switch C is grounded; the source electrode of the fourth MOS switch D is the output end of the power level circuit; the drain electrode of the second MOS switch B and the drain electrode of the third MOS switch C are also connected with one end of a sampling resistor Rsns; the grid electrode of the first MOS switch A, the grid electrode of the second MOS switch B, the grid electrode of the third MOS switch C and the grid electrode of the fourth MOS switch D are all connected with the output end of the Logic control circuit Logic.
As shown in fig. 3, the Timer circuit provided in this embodiment includes a second comparator COMPA, a third comparator COMPB, a fourth comparator COMPC, and an and gate.
The positive input end of a second comparator COMPA is connected with the output voltage VOUT, the reverse input end of the second comparator COMPA is connected with the input voltage VIN, and the output end of the second comparator COMPA is connected with the input end of the Logic control circuit Logic; a forward input end of a third comparator COMPB is connected with the output voltage VOUT, a reverse input end of the third comparator COMPB is connected with the input voltage VIN, and an output end of the third comparator COMPB is connected with a first input end of the AND gate; a forward input end of the fourth comparator COMPC is connected with the input voltage VIN, a reverse input end of the fourth comparator COMPC is connected with the output voltage VOUT, and an output end of the fourth comparator COMPC is connected with a second input end of the AND gate; and the output end of the AND gate is connected with the input end of the Logic control circuit Logic.
The working principle of the power control circuit provided by the embodiment is as follows: the internal reference voltage VREF and VOUT voltage feedback signals are subjected to differential amplification to generate a current control signal Vc, inductive current is sampled at switches B and C, and a sampling signal flows through Rsns to generate VSNS; VSNS compares with Vc to generate a pulse width modulation signal PWM; the Timer circuit generates a T1 signal (an output signal of the second comparator COMPA) and a T2 signal (an output signal of the AND gate) by monitoring the VIN and VOUT voltages; PWM, T1 and T2 control switch A, B, C, D together, realize the steady voltage of VOUT.
The generation circuit of T1 and T2 is shown in fig. 3. When VIN > > VOUT, the power control circuit provided in this embodiment works in BUCK mode, and the circuit formed by COMPB calculates the time for switch AD to be turned on together; the valley current mode loop determines the time for the switches BD to conduct together. When VIN < < VOUT, the power control circuit provided in this embodiment works in the BOOST mode, and the circuit formed by comp calculates the time for the switch AD to be turned on together; the time for which the switches AC are commonly turned on is determined by the peak current mode loop. When VIN is close to VOUT, the power control circuit provided in this embodiment operates in a BUCK-BOOST mode, and a circuit formed by COMPA calculates the time for turning on the switches B and D together; the circuit formed by COMPB and COMPC calculates the time for the switch AD to be conducted together; the time for which the switches AC are commonly conducting is determined by the peak current mode loop.
T1 and T2 are both adaptively adjusted with VIN and VOUT, and the power control circuit provided in this embodiment automatically adjusts the common on-time of the switch AC or BD according to the values of T1 and T2, so that the charging and discharging of the energy storage inductor IND are balanced. By means of the adaptive offset circuit, the power control circuit provided by the embodiment can keep the switching frequency almost unchanged in the full voltage range.
The power control circuit provided by the embodiment adopts self-adaptive on-time valley current mode control in the BUCK mode, and adopts self-adaptive off-time peak current mode control in the BUCK-BOOST and the BOOST. The problems of output voltage undershoot and overshoot caused by the fact that the working point of the loop cannot change suddenly during mode switching are avoided.
As shown in fig. 4, when VIN > > VOUT, the power control circuit provided in this embodiment operates in the valley current mode BUCK mode, the switch C is turned off, and the switch D remains on for a long time. The switch a is turned on at the beginning of each switching cycle, the inductor current increases linearly with time, and the Timer circuit starts to count time. When the preset time is reached, the T2 signal turns off the A, turns on the B, and the inductive current linearly decreases along with the time. When the inductive current sampling signal VSNS reaches the valley value set by Vc, the PWM signal turns off B and turns on a, thereby entering the next switching cycle.
Fig. 5 is a timing diagram of the switching signal and the inductor current signal in the BUCK-BOOST operating mode, where fig. 5 (a) is a timing diagram of the switching signal and the inductor current signal when VIN > = VOUT, and fig. 5 (b) is a timing diagram of the switching signal and the inductor current signal when VIN < = VOUT. As shown in fig. 5, when VIN is close to VOUT (i.e., the difference between VIN and VOUT is within the threshold range), whether VIN > = VOUT or VIN < = VOUT, the power control circuit provided in this embodiment operates in the same BUCK-BOOST mode. At the beginning of each switching cycle, switches a and C are turned on and the inductor current increases linearly with time. When the inductive current sampling signal VSNS reaches the peak value set by Vc, the PWM signal turns off the switch C and turns on the switch D. And meanwhile, the Timer2 circuit starts timing, and when the preset time is reached, the T2 signal turns off the switch A and turns on the switch B. Meanwhile, the Timer1 circuit starts to time, when the preset time is reached, the T1 signal turns off the switch BD, and the switch AC is turned on, so that the power control circuit provided by this embodiment enters the next switching period.
As shown in fig. 6, when VIN < < VOUT, the power control circuit provided in this embodiment operates in the peak current mode BOOST mode, switch a remains on for a long time, and switch B remains off for a long time. Switch C is turned on at the beginning of each switching cycle. The inductive current increases linearly with time, and when the inductive current sampling signal VSNS reaches the peak value set by Vc, the PWM signal turns off C and turns on D. And meanwhile, the Timer2 circuit starts timing, and when the preset time is reached, the T2 signal turns off the D and turns on the C, so that the next switching period is started.
Waveforms at the time of switching the BUCK mode and the BUCK-BOOST mode are shown in FIG. 7. Under the same conditions, the change of VOUT is greatly reduced compared with the transient waveform of the prior art.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In summary, this summary should not be construed to limit the present invention.

Claims (5)

1. A power control circuit based on a peak-to-valley current mode, comprising: the circuit comprises a power level circuit, a differential amplifier, a first comparator, a Timer circuit, a logic control circuit, an output resistor, an output capacitor and a sampling resistor;
the input end of the power level circuit is connected with an input voltage, and the output end of the power level circuit is respectively connected with one end of the output resistor, one end of the output capacitor, one end of the sampling resistor and the reverse input end of the differential amplifier; the other end of the output resistor and the other end of the output capacitor are grounded; one end of the sampling resistor is also connected with the positive input end of the first comparator, and the other end of the sampling resistor is grounded; the input of the positive input end of the differential amplifier is a reference voltage, and the output end of the differential amplifier is connected with the reverse input end of the first comparator; the output end of the first comparator is connected with the input end of the logic control circuit; the input end of the logic control circuit is also connected with the output end of the Timer circuit, and the output end of the logic control circuit is connected with the power level circuit; the input end of the Timer circuit is connected with the input voltage and the output voltage.
2. The peak-to-valley current-mode based power control circuit of claim 1, wherein the power stage circuit comprises a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch, and an energy storage inductor;
the source electrode of the first MOS switch is the input end of the power stage circuit, and the drain electrode of the first MOS switch is respectively connected with the drain electrode of the second MOS switch and one end of the inductor; the source electrode of the second MOS switch is grounded; the other end of the inductor is connected with the drain electrode of the third MOS switch and the drain electrode of the fourth MOS switch respectively; the source electrode of the third MOS switch is grounded; the source electrode of the fourth MOS switch is the output end of the power level circuit; the drain electrode of the second MOS switch and the drain electrode of the third MOS switch are also connected with one end of the sampling resistor; and the grid electrode of the first MOS switch, the grid electrode of the second MOS switch, the grid electrode of the third MOS switch and the grid electrode of the fourth MOS switch are all connected with the output end of the logic control circuit.
3. The peak-to-valley current mode based power control circuit of claim 2, wherein the Timer circuit comprises a second comparator, a third comparator, a fourth comparator and an and gate;
the positive direction input end of the second comparator is connected with the output voltage, the reverse direction input end of the second comparator is connected with the input voltage, and the output end of the second comparator is connected with the input end of the logic control circuit; the positive direction input end of the third comparator is connected with the output voltage, the reverse direction input end of the third comparator is connected with the input voltage, and the output end of the third comparator is connected with the first input end of the AND gate; the positive input end of the fourth comparator is connected with the input voltage, the reverse input end of the fourth comparator is connected with the output voltage, and the output end of the fourth comparator is connected with the second input end of the AND gate; and the output end of the AND gate is connected with the input end of the logic control circuit.
4. The peak-to-valley current-mode based power control circuit of claim 3, wherein when VIN > > VOUT, the power control circuit operates in BUCK mode, the sampling resistor, the first comparator and the differential amplifier forming a valley current-mode loop;
when VIN < < VOUT, the power supply control circuit works in a BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop;
when the difference value of VIN and VOUT is within the threshold range, the power supply control circuit works in a BUCK-BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop;
where VIN is the input voltage and VOUT is the output voltage.
5. The peak-to-valley current mode based power control circuit of claim 4, wherein when the power control circuit is operating in BUCK mode, the third comparator calculates a time for the first MOS switch and the fourth MOS switch to be turned on together, and the valley current mode loop determines a time for the second MOS switch and the fourth MOS switch to be turned on together;
when the power supply control circuit works in a BOOST mode, calculating the time for which the first MOS switch and the fourth MOS switch are conducted together by the fourth comparator; determining, by the peak current mode loop, a time for the first MOS switch and the third MOS switch to be turned on together;
when the power supply control circuit works in a BUCK-BOOST mode, the first comparator calculates the time for the second MOS switch and the fourth MOS switch to be conducted together; calculating, by the third comparator and the fourth comparator, a time for which the first MOS switch and the fourth MOS switch are turned on in common; the time for which the first and third MOS switches are turned on together is determined by the peak current mode loop.
CN202211160067.2A 2022-09-22 2022-09-22 Power supply control circuit based on peak-valley current mode Pending CN115498861A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116613990A (en) * 2023-04-14 2023-08-18 江苏帝奥微电子股份有限公司 Power supply control system and method for automatically switching peak-valley current mode along with duty ratio
CN116885943A (en) * 2023-06-26 2023-10-13 江苏帝奥微电子股份有限公司 Power supply control system based on peak current mode frequency-reducing

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116613990A (en) * 2023-04-14 2023-08-18 江苏帝奥微电子股份有限公司 Power supply control system and method for automatically switching peak-valley current mode along with duty ratio
CN116613990B (en) * 2023-04-14 2023-11-03 江苏帝奥微电子股份有限公司 Power supply control system and method for automatically switching peak-valley current mode along with duty ratio
CN116885943A (en) * 2023-06-26 2023-10-13 江苏帝奥微电子股份有限公司 Power supply control system based on peak current mode frequency-reducing
CN116885943B (en) * 2023-06-26 2023-12-15 江苏帝奥微电子股份有限公司 Power supply control system based on peak current mode frequency-reducing

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