CN115514228A - Switch converter and control circuit thereof - Google Patents
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- CN115514228A CN115514228A CN202110631747.7A CN202110631747A CN115514228A CN 115514228 A CN115514228 A CN 115514228A CN 202110631747 A CN202110631747 A CN 202110631747A CN 115514228 A CN115514228 A CN 115514228A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application discloses a switching converter and a control circuit thereof. The control circuit comprises a first conduction time control circuit, a PWM comparator, a logic circuit, a drive circuit and a light load control circuit. The light-load control circuit compares the inductive current of the switch converter with a preset threshold value when the load end of the switch converter is in a light-load state, and prolongs the conduction time of the pulse width modulation signal under the condition that the inductive current is smaller than the preset threshold value until the inductive current reaches the preset threshold value, so that the conduction and turn-off times of a switch tube in the switch converter can be reduced under the light-load state, the switching loss is reduced, and the efficiency of the switch converter under the light load is improved.
Description
Technical Field
The present invention relates to the field of switching power supply technologies, and in particular, to a switching converter and a control circuit thereof.
Background
Switching converters have been widely used in electronic systems for generating the operating voltages and currents required by internal circuit modules or loads. The switching converter adopts a power switch tube to control the transmission of electric energy from an input end to an output end, so that constant output voltage and/or output current can be provided at the output end. In a switching converter, a constant on-time control method based on a ripple has advantages of good light-load efficiency, fast transient response, and easy implementation, and thus has been widely used in recent years.
Fig. 1 shows a schematic circuit diagram of a conventional switching converter. As shown in fig. 1, the switching converter 100 includes a main power circuit including switching transistors MD1 and MD2 connected in series between an input terminal and a ground terminal, an inductor Lx connected between an intermediate node of the switching transistors MD1 and MD2 and the output terminal, and an output capacitor Co connected between the output terminal and the ground terminal, and a control circuit. The switching converter 100 has an input terminal receiving a dc input voltage Vin and an output terminal providing a dc output voltage Vout. The control circuit of the switching converter 100 is used to provide switching control signals to the switching transistors MD1 and MD 2.
In the control circuit of the switching converter 100, the on-time control circuit 110 sets the fixed on-time Ton of the switching period Tsw, thereby generating the reset signal. The minimum off-time control circuit 120 sets a minimum off-time Toff _ min (or a maximum switching frequency) corresponding to a predetermined output voltage and a predetermined load. The error amplifier EA obtains an error signal Vc from the feedback signal FB of the dc output voltage Vout and the reference voltage VREF0, and the PWM comparator 131 compares the error signal Vc with the feedback signal FB to obtain an intermediate signal. The nand gate 132 has two inputs respectively receiving the intermediate signal and the minimum off-time Toff _ min output by the comparator, and an output providing a set signal. The RS flip-flop 140 generates a pulse width modulation signal PWM according to the reset signal and the set signal. The driving circuit 150 converts the pulse width modulation signal PWM into a switching control signal to control the conduction states of the switching tubes MD1 and MD 2.
When the feedback signal FB is less than or equal to the error signal Vc, the on-time control circuit 110 sets a fixed on-time, so that the on-time of the switch control signal is a fixed value. When the feedback signal FB is greater than the error signal Vc, the turn-off signal of the switch control signal is valid, thereby dynamically adjusting the turn-off time according to the dc output voltage Vout, which is greater than the minimum turn-off time Toff _ min.
However, in some applications it is desirable to use a low ESR (Equivalent Series Resistance) capacitor (e.g., a ceramic capacitor) at the output of the switching converter 100 as the output capacitor. Since this type of output filter generates a small output ripple even in the presence of a large amount of noise, and the capacitive ripple has a phase delay compared to the inductive ripple, subharmonic oscillation occurs in the system, which may cause a problem in that the control system is unstable. The use of a capacitor (e.g., an electrolytic capacitor) with a large ESR as an output capacitor at the output end of the switching converter 100 not only increases the circuit area and cost, but also increases the ripple of the output voltage to cause large fluctuation, which affects the normal operation of the subsequent circuit.
In addition, the switching converter 100 of the prior art has a slow transient response, and when a large voltage drop event occurs at the load end, the voltage of the output end changes, which limits the application of the control model in the field requiring fast transient response. Also, due to the on-time limitation of the switch control signal, the switching converter 100 cannot provide stable power supply when the input voltage Vin and the output voltage Vout are close, reducing the overall efficiency of the switching converter.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a switching converter and a control circuit thereof, which can use a capacitor with a low ESR as an output capacitor and can also improve the transient response speed and efficiency of the switching converter at a light load.
According to an aspect of the present invention, there is provided a control circuit of a switching converter, the switching converter controlling power transmission from an input terminal to an output terminal by using at least one switching tube so as to generate a dc output voltage according to a dc input voltage, wherein the control circuit includes: a first on-time control circuit for generating a first on-time based on the DC output voltage and the DC input voltage and a switching cycle of the switching converter; a PWM comparator for comparing a superimposed signal related to an error signal of the DC output voltage with a feedback signal related to the DC output voltage to generate an intermediate signal; the logic circuit is used for generating a set signal and a reset signal according to the intermediate signal and the first on-time respectively, generating a pulse width modulation signal according to the set signal and the reset signal, acquiring the on-time by adopting the reset signal, and acquiring the off-time related to the direct current output voltage by adopting the set signal; the driving circuit is used for converting the pulse width modulation signal into a switch control signal so as to control the conduction state of the at least one switching tube; and the light load control circuit is used for comparing the inductive current of the switching converter with a preset threshold value when the load end of the switching converter is in a light load state, and prolonging the conduction time of the pulse width modulation signal under the condition that the inductive current is smaller than the preset threshold value until the inductive current reaches the preset threshold value.
Optionally, the control circuit further includes: a second on-time control circuit configured to generate a second on-time based on a voltage difference between the dc input voltage and the dc output voltage, wherein the logic circuit adjusts the on-time based on the intermediate signal, the first on-time, and the second on-time.
Optionally, the light-load control circuit includes: the light load detection module is used for providing a light load indicating signal of a logic high level when the load end of the switch converter is in a light load state; the current sampling module is used for obtaining the inductive current; the first comparator is used for comparing the inductive current with a reference voltage representing the preset threshold value to obtain a comparison signal; and a first nand gate for setting a third on-time according to the light-load indication signal and the comparison signal, wherein the logic circuit adjusts the on-time based on the intermediate signal, the first on-time, the second on-time, and the third on-time.
Optionally, the logic circuit includes: the first input end and the second input end of the second NAND gate respectively receive the intermediate signal and the minimum turn-off time, the output end of the second NAND gate provides the setting signal, and the minimum turn-off time is a fixed time period; a third nand gate, wherein the first to third input terminals respectively receive the first on-time, the second on-time and the third on-time, and the output terminal provides the reset signal; and the RS trigger generates the pulse width modulation signal according to the setting signal and the reset signal respectively.
Optionally, the control circuit further includes: a minimum off-time control circuit for generating the minimum off-time, the off-time being greater than the minimum off-time.
Optionally, the control circuit further includes: an error signal generation circuit for comparing the feedback signal with a reference voltage to obtain the error signal.
Optionally, the error signal generating circuit includes: the inverting input end and the non-inverting input end of the error amplifier respectively receive the feedback signal and the reference voltage, and the output end of the error amplifier is used for providing the error signal; and a first end of the first capacitor is connected with the output end of the error amplifier, and a second end of the first capacitor is grounded.
Optionally, the error signal generating circuit further includes: and the compensation resistor and the compensation capacitor are sequentially connected between the output end of the error amplifier and the ground.
Optionally, the control circuit further includes: and the PWM comparator compares a superposed signal of the error signal and the ramp signal with the feedback signal so as to generate the intermediate signal.
Optionally, the slope compensation circuit includes: the ramp signal generating module generates the ramp signal according to the pulse width modulation signal and the direct current output voltage; and the voltage gain module is used for carrying out gain amplification on the ramp signal.
Optionally, the ramp signal generating module includes: the first switch, the first resistor and the second switch are sequentially connected between the direct current output voltage and the ground; and a second capacitor, a first end of which is connected to a middle node between the first resistor and the second switch, and a second end of which is grounded, wherein the first switch and the second switch are respectively controlled by an inverted signal of the pwm signal and the pwm signal, so that the second capacitor is charged with the dc output voltage in a first time period beginning at a falling edge of the pwm signal, and the second capacitor is discharged in a second time period beginning at a rising edge of the pwm signal, so as to obtain the ramp signal.
According to another aspect of the present invention, there is provided a switching converter including: the main power circuit adopts at least one switching tube to control the electric energy transmission from the input end to the output end, so as to generate direct current output voltage according to the direct current input voltage; and the control circuit is used for generating a switch control signal to control the conduction state of the at least one switching tube.
Optionally, the main power circuit adopts a topology selected from any one of the following: step-down, step-up, non-inverting step-up and step-down, forward, and flyback.
In the switch converter and the control circuit thereof of the embodiment of the invention, the light-load control circuit is adopted to compare the inductive current of the switch converter with the preset threshold value when the load end of the switch converter is in the light-load state, and prolong the conduction time of the pulse width modulation signal under the condition that the inductive current is smaller than the preset threshold value until the inductive current reaches the preset threshold value, so that the conduction and turn-off times of a switch tube in the switch converter can be reduced under the light-load state, the switching loss is reduced, and the efficiency of the switch converter under the light load is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic circuit diagram of a switching converter according to the prior art;
fig. 2 shows a schematic circuit diagram of a switching converter according to the prior art;
FIGS. 3A and 3B show simulated waveforms of prior art switching converters at different inductances, respectively;
fig. 4 shows a schematic circuit diagram of a switching converter according to the invention;
FIG. 5 shows a schematic circuit diagram of the error signal generating circuit in FIG. 4;
FIG. 6 shows a schematic circuit diagram of the slope compensation circuit of FIG. 4;
FIG. 7 shows a schematic circuit diagram of the light load control circuit of FIG. 4;
fig. 8A and 8B show simulated waveforms of switching converters of the prior art and the embodiment of the present invention, respectively, at a large inductance.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are identified with the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
It should be understood that in the following description, a "circuit" refers to a conductive loop made up of at least one element or sub-circuit by electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that the two be absent intermediate elements.
In this application, the switching transistor is a transistor operating in a switching mode to provide a current path, and includes one selected from a bipolar transistor or a field effect transistor. The first end and the second end of the switching tube are respectively a high potential end and a low potential end on a current path, and the control end is used for receiving a driving signal to control the switching tube to be switched on and switched off.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 2 shows a schematic circuit diagram of a switching converter according to the prior art. As shown in fig. 2, the main power circuit of the switching converter 200 includes switching transistors MD1 and MD2 connected in series between an input terminal and a ground terminal, an inductor Lx connected between an intermediate node of the switching transistors MD1 and MD2 and an output terminal, and an output capacitor Co connected between the output terminal and the ground terminal. The switching converter 200 has an input terminal receiving a dc input voltage Vin and an output terminal providing a dc output voltage Vout. The voltage dividing network formed by the resistors R1 and R2 is used for obtaining the feedback signal FB of the dc output voltage Vout.
The control circuit of the switching converter 200 is used to provide switching control signals to the switching tubes MD1 and MD 2. The switch control signal is a drive signal generated in accordance with a pulse width modulation signal. For example, the switching control signal of the switching tube MD1 is an in-phase signal of the pwm signal, and the switching control signal of the switching tube MD2 is an inverted signal of the pwm signal.
The control circuit of the switching converter 200 includes a first on-time control circuit 210, a second on-time control circuit 220, an error signal generation circuit 230, a PWM comparator 240, a ramp compensation circuit 250, a minimum off-time control circuit 260, a logic circuit 270, and a drive circuit 280.
The first on-time control circuit 210 is used to set a first on-time Ton1 of the switching period Tsw, and the second on-time control circuit 220 is used to set a second on-time Ton2 of the switching period Tsw. The first on-time Ton1 and the second on-time Ton2 are used to generate a reset signal to control the on-time of the pulse width modulation signal PWM.
The error signal generation circuit 230 compares the feedback signal FB of the dc output voltage Vout with the reference voltage VREF0 to generate an error signal Vc.
The ramp compensation circuit 240 generates a ramp signal Vramp at the inductor current reduction stage of the switching converter 200 according to the dc output voltage Vout and the pulse width modulation signal PWM, and compensates the error signal Vc according to the ramp signal Vramp, so that the switching converter can use a ceramic capacitor with low ESR as an output capacitor, thereby reducing the circuit area and reducing the ripple of the output voltage.
Further, the slope of the ramp signal Vramp generated by the ramp compensation circuit 240 in the switching converter 200 according to the embodiment of the present invention is not fixed, and the slope is related to the dc output voltage Vout, so that the ramp compensation circuit 240 has the function of adaptive ramp modulation.
The PWM comparator 250 further compares the superimposed signal of the error signal Vc and the ramp signal Vramp with the feedback signal FB to obtain an intermediate signal V1, and the intermediate signal V1 is used to generate a set signal to control the off-time of the pulse width modulation signal PWM.
The minimum off-time control circuit 260 is used to set a minimum off-time Toff _ min (or a maximum switching frequency) corresponding to a predetermined output voltage and a predetermined load.
The logic circuit 270 is configured to generate a set signal and a reset signal according to the intermediate signal V1, the first on-time Ton1, and the second on-time Ton2, respectively, and generate a pulse width modulation signal PWM according to the set signal and the reset signal.
Further, the logic circuit 270 includes a nand gate 271, a nand gate 272, and an RS flip-flop 273. The nand gate 271 has two inputs respectively receiving the intermediate signal V1 and the minimum off-time Toff _ min of the PWM comparator 250, and an output providing a set signal. The nand gate 272 has two inputs respectively receiving the first on-time Ton1 and the second on-time Ton2, and an output providing the reset signal. The RS flip-flop 273 generates a pulse width modulation signal PWM based on the set signal and the reset signal.
The driving circuit 280 converts the pulse width modulation signal PWM into a switching control signal to control the conduction state of the switching tubes MD1 and MD 2.
In contrast to the switching converter shown in fig. 1, the on-time of the switching converter 200 in fig. 2 is no longer fixed, and the logic circuit 270 adaptively adjusts the on-time according to the intermediate signal V1, the first on-time Ton1 and/or the second on-time Ton2. That is, the logic circuit 270 is determined according to the maximum value among the high level time of the intermediate signal V1, the first on-time Ton1, and the second on-time Ton2. The ramp signal Vramp is a phase correction compensation voltage, and can be used to correct the problem of phase lag due to low ESR.
In addition, the intermediate signal V1 not only controls the off-time of the switching period Tsw, but also controls the on-time of the switching period Tsw according to the high-level time of the intermediate signal V1 when the high-level time of the intermediate signal V1 is greater than the first on-time Ton1, so that the working time of the switching converter can be ensured to be greater than the first on-time Ton1 in some cases, and the requirement of transient response can be met.
Further, setting the first on-time Ton1 as:
Ton1＝Vout/Vin*Tsw
wherein Vout represents a voltage value of the dc output voltage, vin represents a voltage value of the dc input voltage, and Tsw represents a switching period of the switching converter, which can ensure consistency of operating frequencies of the switching converter.
Further, setting the second on-time Ton2 as:
Ton2＝A/(Vin-Vout)
wherein, a represents a preset constant, vout represents a voltage value of the dc output voltage, and Vin represents a voltage value of the dc input voltage, so that when the dc input voltage Vin and the dc output voltage Vout are close to each other, the on-time of the switching converter can be prolonged, so that the switching converter can linearly transit to 100% duty ratio.
As can be seen from the above description, the conventional switching converter 200 basically solves the three disadvantages of the conventional switching converter described above, but the switching converter 200 still has the disadvantages that there is no inductor current information in the structure, which results in poor adaptability of the switching converter 200 to the inductor size. Fig. 3A and 3B show simulated waveforms of prior art switching converters at different inductances, respectively. In fig. 3A and 3B, the input voltage Vin =5V, the output voltage Vout =1.2V, the load current Iload =2mA, the inductance of fig. 3A is 1uH, and the inductance of fig. 3B is 4.7uH. It is obvious from fig. 3A and 3B that when the inductance is 1uH, the output waveform of the system is better, and when the inductance is 4.7uH, the system is in Burst mode (Burst mode), and under light load, the switch tube is continuously turned on for a plurality of cycles, and then turned off for a longer time.
Fig. 4 shows a schematic circuit diagram of a switching converter according to the invention. As shown in fig. 4, the switching converter 300 adopts a Buck topology and operates in a floating mode, and includes a main power circuit and a control circuit, the main power circuit includes switching tubes MD1 and MD2 connected in series between an input end and a ground end, an inductor Lx is connected between an intermediate node of the switching tubes MD1 and MD2 and an output end, and an output capacitor Co is connected between the output end and the ground end. The switching tube MD1 is called a main switching tube, and the switching tube MD2 is called a synchronous switching tube. The switching converter 300 has an input terminal receiving a dc input voltage Vin and an output terminal providing a dc output voltage Vout. The voltage dividing network formed by the resistors R1 and R2 is used for obtaining the feedback signal FB of the dc output voltage Vout.
The control circuit of the switching converter 300 is used to provide switching control signals to the switching tubes MD1 and MD 2. The switch control signal is a drive signal generated in accordance with a pulse width modulation signal. For example, the switching control signal of the switching tube MD1 is an in-phase signal of the pwm signal, and the switching control signal of the switching tube MD2 is an inverted signal of the pwm signal.
The control circuit of the switching converter 300 includes a first on-time control circuit 310, a second on-time control circuit 320, an error signal generation circuit 330, a PWM comparator 340, a slope compensation circuit 350, a minimum off-time control circuit 360, a logic circuit 370, a drive circuit 380, and a light-load control circuit 390.
The first on-time control circuit 310 is used for setting a first on-time Ton1 of the switching period Tsw, and the second on-time control circuit 320 is used for setting a second on-time Ton2 of the switching period Tsw. The first on-time Ton1 and the second on-time Ton2 are used to generate a reset signal to control the on-time of the pulse width modulation signal PWM.
The error signal generating circuit 330 compares the feedback signal FB of the dc output voltage Vout with the reference voltage VREF0 to generate an error signal Vc.
The ramp compensation circuit 340 generates a ramp signal Vramp at the inductor current falling stage of the switching converter 300 according to the dc output voltage Vout and the pulse width modulation signal PWM, and compensates the error signal Vc according to the ramp signal Vramp, so that the switching converter can use a ceramic capacitor with low ESR as an output capacitor, thereby reducing the circuit area and reducing the ripple of the output voltage.
Further, the slope of the ramp signal Vramp generated by the ramp compensation circuit 340 in the switching converter 300 according to the embodiment of the present invention is not fixed, and the slope is related to the dc output voltage Vout, so that the ramp compensation circuit 340 has the function of adaptive ramp modulation.
The PWM comparator 350 further compares the superimposed signal of the error signal Vc and the ramp signal Vramp with the feedback signal FB to obtain an intermediate signal V1, and the intermediate signal V1 is used to generate a set signal to control the off-time of the pulse width modulation signal PWM.
The minimum off-time control circuit 360 is used to set a minimum off-time Toff _ min (or a maximum switching frequency) corresponding to a predetermined output voltage and a predetermined load.
The logic circuit 370 is configured to generate a set signal and a reset signal according to the intermediate signal V1, the first on-time Ton1, and the second on-time Ton2, respectively, and generate a pulse width modulation signal PWM according to the set signal and the reset signal.
As in the prior art, the on-time of the switching converter 300 in fig. 4 is not fixed, and the logic circuit 370 adaptively adjusts the on-time according to the intermediate signal V1, the first on-time Ton1 and the second on-time Ton2. That is, the logic circuit 270 is determined according to the maximum value among the high level time of the intermediate signal V1, the first on-time Ton1, and the second on-time Ton2. The ramp signal Vramp is a phase correction compensation voltage that can be used to correct the problem of phase lag due to low ESR.
In addition, the intermediate signal V1 not only controls the turn-off time of the switching period Tsw, but also controls the turn-on time of the switching period Tsw according to the high level time of the intermediate signal V1 when the high level time of the intermediate signal V1 is greater than the first turn-on time Ton1, so that the working time of the switching converter can be ensured to be greater than the first turn-on time Ton1 in some cases, and the requirement of transient response can be met.
Further, the first on-time Ton1 is set as:
Ton1＝Vout/Vin*Tsw
wherein Vout represents a voltage value of the dc output voltage, vin represents a voltage value of the dc input voltage, and Tsw represents a switching period of the switching converter, which can ensure consistency of operating frequencies of the switching converter.
Further, setting the second on-time Ton2 as:
Ton2＝A/(Vin-Vout)
wherein, a represents a preset constant, vout represents a voltage value of the dc output voltage, and Vin represents a voltage value of the dc input voltage, so that when the dc input voltage Vin and the dc output voltage Vout are close to each other, the on-time of the switching converter can be prolonged, so that the switching converter can linearly transit to 100% duty ratio.
Further, the logic circuit 370 includes a nand gate 371, a nand gate 372, and an RS flip-flop 373. The nand gate 371 has a first input terminal and a second input terminal respectively receiving the intermediate signal V1 and the minimum off-time Toff _ min of the PWM comparator 350, and an output terminal providing a set signal. The nand gate 372 has a first input terminal and a second input terminal for receiving the first on-time Ton1 and the second on-time Ton2, respectively, and an output terminal for providing a reset signal. The RS flip-flop 373 generates a pulse width modulation signal PWM based on the set signal and the reset signal.
The driving circuit 380 converts the pulse width modulation signal PWM into a switching control signal to control the conduction state of the switching tubes MD1 and MD 2.
The light-load control circuit 390 is configured to set a third on-time Ton3 according to the inductor current of the switching converter when the system is in a light-load state, and provide the third on-time Ton3 to the third input terminal of the nand gate 372. When the load of the system is heavy, the light-load control circuit 390 outputs the third on-time Ton3 as a logic high level, and the light-load control circuit 390 does not work; when the system is in a light load state, the light load control circuit 390 operates, and compares the inductor current obtained by sampling the main switching tube with a preset threshold, if the inductor current is smaller than the preset threshold, the light load control circuit 390 outputs a third on-time Ton3 as a logic low level, so that the logic circuit 370 outputs a pulse width modulation signal PWM and keeps the logic high level all the time, so that the main switching tube MD1 is in an on state, and the light load control signal Tctrl is not turned into a logic high level until the inductor current reaches the preset threshold.
The light-load control circuit 390 of this embodiment provides a minimum inductor current peak value (Ipk = Ton × (Vin-Vout)/L) corresponding to the conduction of the switching tube, so if the inductance of the switching converter is relatively small, the inductor current can certainly exceed the preset threshold set by the light-load control circuit 390 within the original conduction time, and the light-load control circuit 390 does not participate in the circuit when the inductance is relatively small, and only when the inductance of the switching converter is relatively large, the light-load control circuit 390 can act when the inductor current cannot reach the preset threshold within the original conduction time, so that the conduction time of the switching tube is prolonged, thereby solving the Burst problem of the system when the inductance is large, simultaneously not interfering with the normal application of the small inductance, and greatly increasing the application range of the system.
Fig. 5 shows a schematic circuit diagram of the error signal generating circuit in fig. 4. As shown in fig. 5, the error signal generating circuit 330 includes an error amplifier 331, a capacitor Cc, and a compensation resistor Rea and a compensation capacitor Cea. The inverting input terminal and the non-inverting input terminal of the error amplifier 331 receive the feedback signal FB and the reference voltage VREF0, respectively, and the output terminal is used for providing the error signal Vc. The capacitor Cc has a first terminal connected to the output terminal of the error amplifier 231 and a second terminal connected to ground. The compensation resistor Rea and the compensation capacitor Cea are sequentially connected in series between the output terminal of the error amplifier 231 and the ground.
Fig. 6 shows a schematic circuit diagram of the slope compensation circuit in fig. 4. As shown in fig. 6, the slope compensation circuit 340 includes a slope signal generation module 341 and a voltage gain amplification module 342. The ramp signal generating module 341 is configured to generate the ramp signal Vramp according to the PWM signal PWM and the dc output voltage Vout. The voltage gain module 342 is configured to gain amplify the ramp signal Vramp.
Further, the ramp signal generating module 341 includes a switch K1, a switch K2, a resistor Rr, and a capacitor Cr. The switch K1, the resistor Rr and the switch K2 are sequentially connected in series between the direct-current output voltage Vout and the ground, the first end of the capacitor Cr is connected with the middle node of the resistor Rr and the switch K2, and the second end of the capacitor Cr is grounded. The switch K1 and the switch K2 are respectively controlled by an inverted signal of a pulse width modulation signal PWM and the pulse width modulation signal PWM.
In each switching period Tsw of the switching converter 300, the switch K1 and the switch K2 are both turned on and off for a period of time. For example, in a first time period beginning at a falling edge of the pulse width modulation signal PWM, the switch K1 is turned on, the switch K2 is turned off, the dc output voltage Vout charges the capacitor Cr, and the voltage across the capacitor Cr gradually increases with time to generate the ramp signal Vramp. In a second time period when the rising edge of the pulse width modulation signal PWM starts, the switch K1 is turned off, the switch K2 is turned on, and the capacitor Cr is discharged through a discharge path formed by the switch K2. Thus, the ramp signal generating module 241 may generate a ramp signal of the same switching period as the switching converter 300.
When the switch K1 is turned on, a charging current is provided to the capacitor Cr through the dc output voltage Vout, and after the system operation is stable, the ramp signal Vramp at the time of turning off the switching tube MD2 can be expressed as:
Vramp＝Ap*Vout/(Rr*Cr)
ap represents a gain coefficient of the voltage gain amplifying module 342, which is a constant, rr represents a resistance value of the resistor Rr, and Cr represents a capacitance value of the capacitor Cr, and different dc output voltages Vout can be adapted.
Fig. 7 shows a schematic circuit diagram of the light-load control circuit in fig. 4. As shown in fig. 7, the light-load control circuit 390 includes a light-load detection module 391, a current sampling module 392, a comparator 393, and a nand gate 394. The light load detection module 391 is configured to provide a light load indication signal PSM at a logic high level when the load end of the switching converter is in a light load state. The current sampling module 392 obtains the inductor current HCS by sampling the main switching tube MD1 of the switching converter 300. The comparator 393 is configured to compare the inductor current HCS with a reference voltage VREF1 representing the preset threshold to obtain a comparison signal. The nand gate 394 sets the third on-time Ton3 according to the light load indication signal PSM and the comparison signal of the comparator 393.
When the load end of the switching converter is in a heavy load state, the light load detection module 391 outputs a light load indication signal PSM of a logic low level, the third on-time Ton3 is a logic high level, and the light load control circuit 390 does not function; when the load end of the switching converter is in a light load state, the light load detection module 391 outputs a light load indication signal PSM at a logic high level, releases a comparison signal of the comparator 393, and if the inductive current HCS is smaller than the reference voltage VREF1, the comparison signal is at the logic high level, and the nand gate 394 outputs a third on-time Ton3 at the logic low level, so that the pulse width modulation signal PWM is kept at the logic high level all the time, and the third on-time Ton3 is not inverted to the logic high level until the inductive current HCS is larger than the reference voltage VREF 1.
It should be noted that the light load detection module 391 of this embodiment may be implemented by a circuit capable of determining a load state in the art. In one embodiment, the light load detection module 391 may determine whether the load side of the switching converter is in a light load state by detecting a switch node voltage of the converter. For example, when the time when the switch node voltage is greater than zero reaches the preset time, the light load detection module 391 determines that the switch converter is in the light load state, and outputs the light load indication signal PSM as a logic high level.
Fig. 8A and 8B show simulated waveforms of switching converters of the prior art and the embodiment of the present invention, respectively, under a large inductance. In fig. 8A and 8B, the input voltage Vin =5V, the output voltage Vout =1.2V, the load current Iload =2mA, and the inductance is 4.7uH. As can be seen from fig. 8A and 8B, the output waveform of the switching converter according to the embodiment of the present invention is a single pulse under the condition of a large inductance, instead of continuously conducting for several cycles in the Burst mode, and then turning off for a long time, so that the conducting and turning-off times of the switching tube under the same load can be greatly reduced, the switching loss is reduced, and the efficiency under the light load is improved.
In summary, in the switching converter and the control circuit thereof according to the embodiments of the present invention, the light-load control circuit is adopted to compare the inductive current of the switching converter with the preset threshold when the load end of the switching converter is in the light-load state, and extend the on-time of the pulse width modulation signal when the inductive current is smaller than the preset threshold until the inductive current reaches the preset threshold, so that the turn-on and turn-off times of the switching tube in the switching converter can be reduced in the light-load state, the switching loss can be reduced, and the efficiency of the switching converter under the light load can be improved.
In a further embodiment, the control circuit adjusts the conduction time of the switching tube of the switching converter according to the maximum value of the high level time, the first conduction time and the second conduction time of the intermediate signal, so that the conduction time of the switching tube can be prolonged when the direct-current input voltage and the direct-current output voltage are close to each other, the switching converter can linearly transit to 100% duty ratio, and the light load efficiency and the stability of the switching converter are improved.
In a further embodiment, the control circuit generates a ramp signal in an inductive current reduction stage of the switching converter by using the ramp compensation circuit, and compensates the error signal according to the ramp signal, so that the switching converter can use a ceramic capacitor with low ESR as an output capacitor, which is beneficial to maintaining the system stability of the switching converter and inhibiting output ripples, and thus, the stability and transient performance of the switching converter can be considered. Further, the slope compensation circuit adaptively adjusts the amplitude of the slope signal according to the dc output voltage, so that different modes of the switching converter can be adaptively adjusted, since the design cost and the manufacturing cost for redesigning the control circuit for different types of switching converters can be reduced.
In the foregoing embodiments, although the switching converter with the buck topology is described with reference to fig. 4, it is understood that the control circuit according to the embodiments of the present invention may also be used in switching converters with other topologies, including, but not limited to, buck, boost, buck-boost, non-inverting buck-boost, forward, flyback, and other topologies.
In the foregoing description, well-known structural elements and steps have not been described in detail. It should be understood by those skilled in the art that the corresponding structural elements and steps may be implemented by various technical means. In addition, in order to form the same structural elements, those skilled in the art may also design a method which is not exactly the same as the above-described method. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in combination to advantage.
In accordance with embodiments of the present invention, the foregoing examples are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.
Claims (13)
1. A control circuit for a switching converter that uses at least one switching transistor to control the transfer of power from an input terminal to an output terminal to produce a dc output voltage from a dc input voltage, wherein the control circuit comprises:
a first on-time control circuit for generating a first on-time based on the DC output voltage and the DC input voltage and a switching cycle of the switching converter;
a PWM comparator for comparing a superimposed signal related to an error signal of the DC output voltage with a feedback signal related to the DC output voltage to generate an intermediate signal;
the logic circuit is used for generating a set signal and a reset signal according to the intermediate signal and the first on-time respectively, generating a pulse width modulation signal according to the set signal and the reset signal, acquiring the on-time by adopting the reset signal, and acquiring the off-time related to the direct current output voltage by adopting the set signal;
the driving circuit is used for converting the pulse width modulation signal into a switch control signal so as to control the conduction state of the at least one switching tube; and
and the light-load control circuit is used for comparing the inductive current of the switch converter with a preset threshold value when the load end of the switch converter is in a light-load state, and prolonging the conduction time of the pulse width modulation signal under the condition that the inductive current is smaller than the preset threshold value until the inductive current reaches the preset threshold value.
2. The control circuit of claim 1, further comprising:
a second on-time control circuit for generating a second on-time based on a voltage difference between the DC input voltage and the DC output voltage,
wherein the logic circuit adjusts the on-time based on the intermediate signal, the first on-time, and the second on-time.
3. The control circuit of claim 2, wherein the light load control circuit comprises:
the light load detection module is used for providing a logic high level light load indication signal when a load end of the switch converter is in a light load state;
the current sampling module is used for obtaining the inductive current;
the first comparator is used for comparing the inductive current with a reference voltage representing the preset threshold value to obtain a comparison signal; and
a first NAND gate for setting a third conduction time according to the light load indication signal and the comparison signal,
wherein the logic circuit adjusts the on-time based on the intermediate signal, the first on-time, the second on-time, and the third on-time.
4. The control circuit of claim 3, wherein the logic circuit comprises:
the first input end and the second input end of the second NAND gate respectively receive the intermediate signal and the minimum turn-off time, the output end of the second NAND gate provides the setting signal, and the minimum turn-off time is a fixed time period;
a third nand gate, wherein the first to third input ends respectively receive the first on-time, the second on-time and the third on-time, and the output end provides the reset signal; and
and the RS trigger generates the pulse width modulation signal according to the setting signal and the reset signal respectively.
5. The control circuit of claim 4, further comprising:
a minimum off-time control circuit for generating the minimum off-time, the off-time being greater than the minimum off-time.
6. The control circuit of claim 1, further comprising:
an error signal generation circuit for comparing the feedback signal with a reference voltage to obtain the error signal.
7. The control circuit of claim 6, wherein the error signal generation circuit comprises:
the inverting input end and the non-inverting input end of the error amplifier respectively receive the feedback signal and the reference voltage, and the output end of the error amplifier is used for providing the error signal; and
and the first end of the first capacitor is connected with the output end of the error amplifier, and the second end of the first capacitor is grounded.
8. The control circuit of claim 7, wherein the error signal generation circuit further comprises:
and the compensation resistor and the compensation capacitor are sequentially connected between the output end of the error amplifier and the ground.
9. The control circuit of claim 1, further comprising:
and the PWM comparator compares a superposed signal of the error signal and the ramp signal with the feedback signal so as to generate the intermediate signal.
10. The control circuit of claim 9, wherein the slope compensation circuit comprises:
the ramp signal generating module generates the ramp signal according to the pulse width modulation signal and the direct current output voltage; and
and the voltage gain module is used for carrying out gain amplification on the ramp signal.
11. The control circuit of claim 10, wherein the ramp signal generation module comprises:
the first switch, the first resistor and the second switch are sequentially connected between the direct current output voltage and the ground; and
a second capacitor, a first end is connected with the first resistor and the middle node of the second switch, a second end is grounded,
the first switch and the second switch are respectively controlled by an inverted signal of the pulse width modulation signal and the pulse width modulation signal, so that the direct current output voltage is used for charging the second capacitor in a first time period beginning at a falling edge of the pulse width modulation signal, and the second capacitor is discharged in a second time period beginning at a rising edge of the pulse width modulation signal, so as to obtain the ramp signal.
12. A switching converter, comprising:
the main power circuit adopts at least one switching tube to control the electric energy transmission from the input end to the output end, so as to generate direct current output voltage according to the direct current input voltage; and
a control circuit according to any of claims 1-11, arranged to generate a switch control signal to control the conductive state of the at least one switching tube.
13. The switching converter of claim 12, the main power circuit employing a topology selected from any one of: step-down, step-up, non-inverting step-up and step-down, forward, and flyback.
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| CN116885947A (en) * | 2023-09-07 | 2023-10-13 | 深圳市思远半导体有限公司 | Switching power supply, control circuit, chip and equipment thereof |
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