CN115498861B - Power supply control circuit based on peak-valley value current mode - Google Patents
Power supply control circuit based on peak-valley value current mode Download PDFInfo
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- CN115498861B CN115498861B CN202211160067.2A CN202211160067A CN115498861B CN 115498861 B CN115498861 B CN 115498861B CN 202211160067 A CN202211160067 A CN 202211160067A CN 115498861 B CN115498861 B CN 115498861B
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- 238000005070 sampling Methods 0.000 claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims abstract description 11
- 238000004146 energy storage Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 10
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 description 3
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
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- 238000012544 monitoring process Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
The invention discloses a power supply control circuit based on a peak-valley value current mode, which comprises: the power stage circuit, the differential amplifier, the first comparator, the Timer circuit, the logic control circuit, the output resistor, the output capacitor and the sampling resistor; the input end of the power stage circuit is connected with the input voltage, and the output end of the power stage circuit is respectively connected with one end of the output resistor, one end of the output capacitor, one end of the sampling resistor and the reverse input end of the differential amplifier; one end of the sampling resistor is also connected with the positive input end of the first comparator; the input of the forward input end of the differential amplifier is a reference voltage, and the output end of the differential amplifier is connected with the reverse input end of the first comparator; the output end of the first comparator is connected with the input end of the logic control circuit; the input end of the logic control circuit is also connected with the output end of the Timer circuit, and the output end of the logic control circuit is connected with the power stage circuit; the Timer circuit input terminal receives the input voltage and the output voltage. The invention can avoid the problems of undershoot and overshoot of the output voltage caused by mode switching.
Description
Technical Field
The invention relates to the technical field of power management, in particular to a power control circuit based on a peak-valley value current mode.
Background
BUCK-BOOST is short for inductance type switch BUCK-BOOST DCDC voltage stabilizer. The basic principle is as shown in fig. 1, a power stage Circuit is formed by a MOS switch ABCD and an inductor, a Control Circuit (Control Circuit) enables the switch ABCD to alternately work according to a certain time sequence, and energy is moved from an input VIN to an output VOUT by utilizing an energy storage element inductor while keeping the output voltage VOUT constant; the output voltage of the BUCK-BOOST may be greater than, less than, or equal to the input voltage, as compared to other types of DCDC regulators. The technology is widely applied to application scenes of battery power supply.
When VIN > VOUT, D keeps on long, C keeps off long, A and B are alternately conducted, and BUCK-BOOST works in a simple BUCK mode (BUCK mode); when VIN < < VOUT, A remains on long, B remains off long, C and D are alternately on, BUCK-BOOST operates in a simple BOOST mode (BOOST mode). Both BUCK mode and BOOST mode can work normally only in a certain VOUT/VIN ratio range, and when VIN is close to VOUT, a special BUCK-BOOST mode (BUCK-BOOST mode) needs to be designed to enable ABCD to work cooperatively, so that the constant VOUT can be realized.
The existing scheme is that the average value of the current output to VOUT is smaller than the peak current actually controlled by a loop in the BUCK mode and the BUCK-BOOST mode near the switching point of the BUCK mode; in BUCK-BOOST mode, the average value of the current output to VOUT is larger than the peak current actually controlled by the loop. When the mode is switched, the working point of the loop cannot be suddenly changed, so that voltage overshoot occurs at the VOUT end when the BUCK mode is switched to the BUCK-BOOST mode; when the BUCK-BOOST mode is switched to the BUCK mode, voltage undershoot occurs at the VOUT terminal.
Disclosure of Invention
In order to solve the problems, the invention provides a power supply control circuit based on a peak-to-valley current mode.
In order to achieve the above object, the present invention provides the following solutions:
A peak-to-valley current mode based power control circuit comprising: the power stage circuit, the differential amplifier, the first comparator, the Timer circuit, the logic control circuit, the output resistor, the output capacitor and the sampling resistor;
the input end of the power stage circuit is connected with the input voltage, and the output end of the power stage circuit is respectively connected with one end of the output resistor, one end of the output capacitor, one end of the sampling resistor and the reverse input end of the differential amplifier; the other end of the output resistor and the other end of the output capacitor are grounded; one end of the sampling resistor is also connected with the positive input end of the first comparator, and the other end of the sampling resistor is grounded; the input of the positive input end of the differential amplifier is a reference voltage, and the output end of the differential amplifier is connected with the negative input end of the first comparator; the output end of the first comparator is connected with the input end of the logic control circuit; the input end of the logic control circuit is also connected with the output end of the Timer circuit, and the output end of the logic control circuit is connected with the power stage circuit; the input end of the Timer circuit is connected with the input voltage and the output voltage.
Optionally, the power stage circuit includes a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch, and an energy storage inductor;
The source electrode of the first MOS switch is an input end of the power stage circuit, and the drain electrode of the first MOS switch is connected with the drain electrode of the second MOS switch and one end of the energy storage inductor respectively; the source electrode of the second MOS switch is grounded; the other end of the energy storage inductor is connected with the drain electrode of the third MOS switch and the drain electrode of the fourth MOS switch respectively; the source electrode of the third MOS switch is grounded; the source electrode of the fourth MOS switch is the output end of the power stage circuit; the drain electrode of the second MOS switch and the drain electrode of the third MOS switch are also connected with one end of the sampling resistor; the grid electrode of the first MOS switch, the grid electrode of the second MOS switch, the grid electrode of the third MOS switch and the grid electrode of the fourth MOS switch are all connected with the output end of the logic control circuit.
Optionally, the Timer circuit includes a second comparator, a third comparator, a fourth comparator, and an and gate;
The positive input end of the second comparator is connected with the output voltage, the negative input end of the second comparator is connected with the input voltage, and the output end of the second comparator is connected with the input end of the logic control circuit; the positive input end of the third comparator is connected with the output voltage, the negative input end of the third comparator is connected with the input voltage, and the output end of the third comparator is connected with the first input end of the AND gate; the positive input end of the fourth comparator is connected with the input voltage, the negative input end of the fourth comparator is connected with the output voltage, and the output end of the fourth comparator is connected with the second input end of the AND gate; the output end of the AND gate is connected with the input end of the logic control circuit.
Optionally, when VIN > VOUT, the power control circuit operates in a BUCK mode, and the sampling resistor, the first comparator, and the differential amplifier form a valley current mode loop;
When VIN < < VOUT, the power supply control circuit works in a BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop;
when the difference value between VIN and VOUT is within the threshold value range, the power supply control circuit works in a BUCK-BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop;
Wherein VIN is an input voltage and VOUT is an output voltage.
Optionally, when the power supply control circuit works in a BUCK mode, calculating the common conduction time of the first MOS switch and the fourth MOS switch by the third comparator, and determining the common conduction time of the second MOS switch and the fourth MOS switch by the valley current mode loop;
When the power supply control circuit works in a BOOST mode, the fourth comparator calculates the common conduction time of the first MOS switch and the fourth MOS switch; determining the common conduction time of the first MOS switch and the third MOS switch by the peak current mode loop;
When the power supply control circuit works in a BUCK-BOOST mode, the first comparator calculates the common conduction time of the second MOS switch and the fourth MOS switch; calculating, by the third comparator and the fourth comparator, a time when the first MOS switch and the fourth MOS switch are commonly turned on; and determining the common conduction time of the first MOS switch and the third MOS switch by the peak current mode loop.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
The power supply control circuit provided by the invention adopts self-adaptive on time valley current mode control in a BUCK mode, and adopts self-adaptive offtime peak current mode control in BUCK-BOOST and BOOST, so that the problems of undershoot and overshoot of output voltage caused by incapability of abrupt change of a working point of a loop in mode switching are avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of BUCK-BOOST;
FIG. 2 is a schematic diagram of a power control circuit based on a peak-to-valley current mode according to the present invention;
fig. 3 is a schematic diagram of a Timer circuit according to the present invention;
FIG. 4 is a timing diagram of the switching signal and inductor current signal in BUCK mode of operation;
FIG. 5 is a timing diagram of the switching signal and inductor current signal in BUCK-BOOST mode of operation;
FIG. 6 is a timing diagram of the switching signal and inductor current signal in the BOOST mode of operation;
FIG. 7 is a waveform diagram at the time of switching between BUCK mode and BUCK-BOOST mode.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
As shown in fig. 2, the power control circuit based on peak-to-valley current mode provided in this embodiment includes: a power stage circuit (dashed box portion), a differential amplifier Gm, a first comparator COMP1, a Timer circuit, a Logic control circuit Logic, an output resistor Rout, an output capacitor Cout, and a sampling resistor Rsns.
The input end of the power stage circuit is connected with the input voltage VIN, and the output end of the power stage circuit is respectively connected with one end of the output resistor Rout, one end of the output capacitor Cout, one end of the sampling resistor Rsns and the reverse input end of the differential amplifier Gm; the other end of the output resistor Rout and the other end of the output capacitor Cout are grounded; one end of the sampling resistor Rsns is also connected with the positive input end of the first comparator COMP1, and the other end of the sampling resistor Rsns is grounded; the input of the positive input end of the differential amplifier Gm is a reference voltage VREF, and the output end of the differential amplifier Gm is connected with the negative input end of the first comparator COMP 1; the output end of the first comparator COMP1 is connected with the input end of the Logic control circuit Logic; the input end of the Logic control circuit Logic is also connected with the output end of the Timer circuit, and the output end of the Logic control circuit Logic is connected with the power stage circuit; the input terminal of the Timer circuit is connected with the input voltage VIN and the output voltage VOUT.
As shown in fig. 2, the power stage circuit provided in this embodiment includes a first MOS switch a, a second MOS switch B, a third MOS switch C, a fourth MOS switch D, and an energy storage inductor IND. The source electrode of the first MOS switch A is an input end of the power stage circuit, and the drain electrode of the first MOS switch A is respectively connected with the drain electrode of the second MOS switch B and one end of the energy storage inductor IND; the source electrode of the second MOS switch B is grounded; the other end of the energy storage inductor IND is respectively connected with the drain electrode of the third MOS switch C and the drain electrode of the fourth MOS switch D; the source electrode of the third MOS switch C is grounded; the source electrode of the fourth MOS switch D is the output end of the power stage circuit; the drain electrode of the second MOS switch B and the drain electrode of the third MOS switch C are also connected with one end of a sampling resistor Rsns; the grid electrode of the first MOS switch A, the grid electrode of the second MOS switch B, the grid electrode of the third MOS switch C and the grid electrode of the fourth MOS switch D are all connected with the output end of the Logic control circuit Logic.
As shown in fig. 3, the Timer circuit provided in this embodiment includes a second comparator COMPA, a third comparator COMPB, a fourth comparator COMPC, and an and gate.
The positive input end of the second comparator COMPA is connected with the output voltage VOUT, the negative input end of the second comparator COMPA is connected with the input end of the Logic control circuit Logic, and the output end of the second comparator COMPA is connected with the input end of the Logic control circuit Logic; the positive input end of the third comparator COMPB is connected with the output voltage VOUT, the negative input end of the third comparator COMPB is connected with the input voltage VIN, and the output end of the third comparator COMPB is connected with the first input end of the and gate; the positive input end of the fourth comparator COMPC is connected with the input voltage VIN, the negative input end of the fourth comparator COMPC is connected with the output voltage VOUT, and the output end of the fourth comparator COMPC is connected with the second input end of the and gate; the output end of the AND gate is connected with the input end of the Logic control circuit Logic.
The working principle of the power supply control circuit provided in this embodiment is as follows: the internal reference voltage VREF and the VOUT voltage feedback signal are amplified by difference to generate a current control signal Vc, the inductive current is sampled at the switches B and C, and the sampled signal flows through Rsns to generate VSNS; VSNS and Vc are compared to generate a pulse width modulation signal PWM; the Timer circuit generates a T1 signal (output signal of the second comparator COMPA) and a T2 signal (output signal of the and gate) by monitoring the VIN and VOUT voltages; PWM, T1 and T2 jointly control switch A, B, C, D to realize the voltage stabilization of VOUT.
The generation circuits of T1 and T2 are shown in fig. 3. When VIN > VOUT, the power supply control circuit provided by the embodiment works in a BUCK mode, and the circuit formed by COMPB calculates the common conduction time of the switch AD; the time for which the switches BD are commonly turned on is determined by the valley current mode loop. When VIN < < VOUT, the power supply control circuit provided by the embodiment works in a BOOST mode, and the circuit formed by COMPC calculates the common conduction time of the switch AD; the time at which the switches AC are commonly on is determined by the peak current mode loop. When VIN is close to VOUT, the power supply control circuit provided by the embodiment works in a BUCK-BOOST mode, and a circuit formed by COMPA calculates the common conduction time of the switches B and D; the circuit formed by COMPB and COMPC calculates the time when the switch AD is commonly turned on; the time at which the switches AC are commonly on is determined by the peak current mode loop.
With the self-adaptive adjustment of VIN and VOUT, T1 and T2 are adjusted automatically according to the values of T1 and T2 by the power control circuit according to the embodiment, so that the charge and discharge of the energy storage inductor IND are balanced. By means of the self-adaptive offtime circuit, the switching frequency of the power supply control circuit provided by the embodiment is almost unchanged in the full voltage range.
The power supply control circuit provided by the embodiment adopts self-adaptive on time valley current mode control in a BUCK mode, and adopts self-adaptive offtime peak current mode control in BUCK-BOOST and BOOST. The problems of undershoot and overshoot of the output voltage caused by incapability of abrupt change of the working point of a loop during mode switching are avoided.
As shown in fig. 4, when VIN > VOUT, the power control circuit provided in this embodiment operates in the valley current mode BUCK mode, the switch C is turned off, and the switch D remains on for a long time. The start switch a of each switching cycle is turned on, the inductor current increases linearly with time, and the Timer circuit starts to count. When the preset time is reached, the signal T2 turns off A, turns B on, and the inductance current linearly decreases along with the time. When the inductor current sampling signal VSNS reaches the valley value set by Vc, the PWM signal turns B off and a on, thereby entering the next switching cycle.
Fig. 5 is a timing diagram of the switching signal and the inductor current signal in the BUCK-BOOST mode, wherein fig. 5 (a) is a timing diagram of the switching signal and the inductor current signal when VIN > =vout, and fig. 5 (b) is a timing diagram of the switching signal and the inductor current signal when VIN < =vout. As shown in fig. 5, when VIN approaches VOUT (i.e., the difference between VIN and VOUT is within the threshold range), the power control circuit provided in this embodiment operates in the same BUCK-BOOST mode, regardless of VIN > =vout or VIN < =vout. The switches a and C are turned on at the beginning of each switching cycle and the inductor current increases linearly with time. When the inductor current sampling signal VSNS reaches the peak value set by Vc, the PWM signal turns off the switch C and turns on the switch D. And meanwhile, the Timer2 circuit starts timing, and when the preset time is reached, the switch A is turned off by the T2 signal, and the switch B is turned on. Meanwhile, the Timer1 circuit starts to count, when the preset time is reached, the switch BD is turned off by the T1 signal, the switch AC is turned on, and the power supply control circuit provided by the embodiment enters the next switching period.
As shown in fig. 6, when VIN < < VOUT, the power control circuit provided in this embodiment operates in the peak current mode BOOST mode, and switch a remains long-turned on and switch B remains long-turned off. The switch C is turned on at the beginning of each switching cycle. The inductor current increases linearly with time, and when the inductor current sampling signal VSNS reaches the peak value set by Vc, the PWM signal turns C off and D on. And meanwhile, the Timer2 circuit starts to count, and when the preset time is reached, the T2 signal turns off D and turns on C, so that the next switching period is entered.
Waveforms at the time of switching the BUCK mode and the BUCK-BOOST mode are shown in FIG. 7. Under the same conditions, the variation of VOUT is greatly reduced compared with the transient waveform in the prior art.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In summary, the present description should not be construed as limiting the invention.
Claims (4)
1. A peak-to-valley current mode based power control circuit, comprising: the power stage circuit, the differential amplifier, the first comparator, the Timer circuit, the logic control circuit, the output resistor, the output capacitor and the sampling resistor;
The input end of the power stage circuit is connected with the input voltage, and the output end of the power stage circuit is respectively connected with one end of the output resistor, one end of the output capacitor, one end of the sampling resistor and the reverse input end of the differential amplifier; the other end of the output resistor and the other end of the output capacitor are grounded; one end of the sampling resistor is also connected with the positive input end of the first comparator, and the other end of the sampling resistor is grounded; the input of the positive input end of the differential amplifier is a reference voltage, and the output end of the differential amplifier is connected with the negative input end of the first comparator; the output end of the first comparator is connected with the input end of the logic control circuit; the input end of the logic control circuit is also connected with the output end of the Timer circuit, and the output end of the logic control circuit is connected with the power stage circuit; the input end of the Timer circuit is connected with the input voltage and the output voltage;
The Timer circuit comprises a second comparator, a third comparator, a fourth comparator and an AND gate;
The positive input end of the second comparator is connected with the output voltage, the negative input end of the second comparator is connected with the input voltage, and the output end of the second comparator is connected with the input end of the logic control circuit; the positive input end of the third comparator is connected with the output voltage, the negative input end of the third comparator is connected with the input voltage, and the output end of the third comparator is connected with the first input end of the AND gate; the positive input end of the fourth comparator is connected with the input voltage, the negative input end of the fourth comparator is connected with the output voltage, and the output end of the fourth comparator is connected with the second input end of the AND gate; the output end of the AND gate is connected with the input end of the logic control circuit.
2. The peak-to-valley current mode based power supply control circuit according to claim 1, wherein the power stage circuit comprises a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch, and an energy storage inductor;
The source electrode of the first MOS switch is an input end of the power stage circuit, and the drain electrode of the first MOS switch is connected with the drain electrode of the second MOS switch and one end of the inductor respectively; the source electrode of the second MOS switch is grounded; the other end of the inductor is connected with the drain electrode of the third MOS switch and the drain electrode of the fourth MOS switch respectively; the source electrode of the third MOS switch is grounded; the source electrode of the fourth MOS switch is the output end of the power stage circuit; the drain electrode of the second MOS switch and the drain electrode of the third MOS switch are also connected with one end of the sampling resistor; the grid electrode of the first MOS switch, the grid electrode of the second MOS switch, the grid electrode of the third MOS switch and the grid electrode of the fourth MOS switch are all connected with the output end of the logic control circuit.
3. The peak-to-valley current mode based power supply control circuit of claim 2, wherein when VIN is greater than VOUT and the difference between VIN and VOUT exceeds a threshold range, the power supply control circuit operates in a BUCK mode, the sampling resistor, the first comparator, and the differential amplifier form a valley current mode loop;
When VIN is smaller than VOUT and the difference value between VIN and VOUT exceeds a threshold value range, the power supply control circuit works in a BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop;
when the difference value between VIN and VOUT is within the threshold value range, the power supply control circuit works in a BUCK-BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop;
Wherein VIN is an input voltage and VOUT is an output voltage.
4. The peak-to-valley current mode based power supply control circuit according to claim 3, wherein when the power supply control circuit is operated in a BUCK mode, the third comparator calculates a time when the first MOS switch and the fourth MOS switch are commonly turned on, and the valley current mode loop determines a time when the second MOS switch and the fourth MOS switch are commonly turned on;
When the power supply control circuit works in a BOOST mode, the fourth comparator calculates the common conduction time of the first MOS switch and the fourth MOS switch; determining the common conduction time of the first MOS switch and the third MOS switch by the peak current mode loop;
When the power supply control circuit works in a BUCK-BOOST mode, the second comparator calculates the common conduction time of the second MOS switch and the fourth MOS switch; calculating, by the third comparator and the fourth comparator, a time when the first MOS switch and the fourth MOS switch are commonly turned on; and determining the common conduction time of the first MOS switch and the third MOS switch by the peak current mode loop.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211160067.2A CN115498861B (en) | 2022-09-22 | 2022-09-22 | Power supply control circuit based on peak-valley value current mode |
| TW112136031A TWI862181B (en) | 2022-09-22 | 2023-09-21 | Power supply control circuit based on peak-valley value current mode and inductor switch buck-boost dc/dc voltage regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211160067.2A CN115498861B (en) | 2022-09-22 | 2022-09-22 | Power supply control circuit based on peak-valley value current mode |
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| CN115498861A CN115498861A (en) | 2022-12-20 |
| CN115498861B true CN115498861B (en) | 2024-10-15 |
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| CN202211160067.2A Active CN115498861B (en) | 2022-09-22 | 2022-09-22 | Power supply control circuit based on peak-valley value current mode |
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| CN116613990B (en) * | 2023-04-14 | 2023-11-03 | 江苏帝奥微电子股份有限公司 | Power supply control system and method for automatically switching peak-valley current mode along with duty ratio |
| CN116885943B (en) * | 2023-06-26 | 2023-12-15 | 江苏帝奥微电子股份有限公司 | Power supply control system based on peak current mode frequency-reducing |
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| US11563378B2 (en) * | 2019-09-16 | 2023-01-24 | Texas Instruments Incorporated | Seamless DCM-PFM transition for single pulse operation in DC-DC converters |
| US11342846B2 (en) * | 2019-09-20 | 2022-05-24 | Texas Instruments Incorporated | Digital control for voltage converter |
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| US11705811B2 (en) * | 2020-11-10 | 2023-07-18 | M3 Technology Inc. | Buck-boost converter and hybrid control method |
| CN113949267B (en) * | 2021-10-19 | 2022-09-27 | 珠海智融科技股份有限公司 | Four-switch BUCKBOOST controller based on average current mode |
| CN114785127B (en) * | 2022-04-15 | 2024-04-02 | 西安电子科技大学重庆集成电路创新研究院 | Multi-mode smooth transition wide-input-range DC-DC converter |
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| CN111262435A (en) * | 2020-03-11 | 2020-06-09 | 昌芯(西安)集成电路科技有限责任公司 | Control circuit and control method of four-switch buck-boost converter |
| CN111245242A (en) * | 2020-03-26 | 2020-06-05 | 珠海英集芯半导体有限公司 | Average current mode-based BUCK-BOOST converter and conversion method thereof |
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