TW202414978A - Power supply control circuit based on peak-valley value current mode - Google Patents

Abstract

A power supply control circuit based on a peak-valley value current mode is provided. The power supply control circuit comprises a power level circuit, a differential amplifier, a first comparator, a Timer circuit, a logic control circuit, an output resistor, an output capacitor and a sampling resistor. An input terminal of the power-level circuit is connected with an input voltage, and an output terminal of the power-level circuit is connected with one terminal of the output resistor, one terminal of the output capacitor, one terminal of the sampling resistor and a reverse input terminal of the differential amplifier. One terminal of the sampling resistor is also connected with a positive input terminal of the first comparator. A positive input terminal of the differential amplifier is connected with a reference voltage, and an output terminal of the differential amplifier is connected with a reverse input terminal of the first comparator. An output terminal of the first comparator is connected with an input terminal of the logic control circuit. the input terminal of the logic control circuit is also connected with an output terminal of the Timer circuit, and an output terminal of the logic control circuit is connected with the power level circuit. An input terminal of the Timer circuit is connected with the input voltage and an output voltage.

Description

A power control circuit based on peak and valley current mode

The present invention relates to the field of power management technology, and in particular to a power control circuit based on a peak-valley current mode.

BUCK-BOOST is the abbreviation of inductive switch buck-boost DCDC voltage regulator. Its basic principle is shown in Figure 1. Switch ABCD and energy storage inductor IND form a power stage circuit. The control circuit allows switch ABCD to work alternately in a certain sequence. While keeping the output voltage VOUT constant, the energy is moved from the input voltage VIN to the output voltage VOUT by using the energy storage inductor IND. Compared with other types of DCDC regulators, the output voltage VOUT of BUCK-BOOST can be greater than, less than or equal to the input voltage VIN. This technology has been widely used in battery-powered application scenarios.

When VIN is greater than VOUT, and the difference between VIN and VOUT exceeds the threshold range, switch D remains on for a long time, switch C remains off for a long time, switches A and B are turned on alternately, and BUCK-BOOST works in a simple buck mode (BUCK mode); when VIN is less than VOUT, and the difference between VIN and VOUT exceeds the threshold range, switch A remains on for a long time, switch B remains off for a long time, switches C and D are turned on alternately, and BUCK-BOOST works in a simple boost mode (BOOST mode). Both the buck mode and the boost mode can only work normally within a certain VOUT/VIN ratio range. When VIN is close to VOUT, a special buck-boost mode (BUCK-BOOST mode) needs to be designed to allow switches ABCD to work together to achieve a constant VOUT.

The existing solution is that near the switching point between BUCK mode and BUCK-BOOST mode, in BUCK mode, the average current output to the VOUT end is less than the peak current actually controlled by the loop; in BUCK-BOOST mode, the average current output to the VOUT end is greater than the peak current actually controlled by the loop. When switching modes, the operating point of the loop cannot change suddenly, resulting in a voltage overshoot at the VOUT end when the BUCK mode switches to the BUCK-BOOST mode; and a voltage undershoot at the VOUT end when the BUCK-BOOST mode switches to the BUCK mode.

In order to solve the above problems, the present invention provides a power control circuit based on the peak-valley current mode.

To achieve the above purpose, the present invention provides the following scheme: A power control circuit based on the peak-valley current mode, comprising: a power stage circuit, a differential amplifier, a first comparator, a timer circuit, a logic control circuit, an output resistor, an output capacitor and a sampling resistor; The input end of the power stage circuit is connected to the input voltage, and the output end of the power stage circuit is respectively connected to one end of the output resistor, one end of the output capacitor, one end of the sampling resistor and the reverse input end of the differential amplifier; the other end of the output resistor and the other end of the output capacitor are grounded; one end of the sampling resistor is also connected to the positive input end of the first comparator, and the other end of the sampling resistor is grounded; the differential amplifier The positive input terminal of the differential amplifier is connected to the reference voltage, the output terminal of the differential amplifier is connected to the negative input terminal of the first comparator; the output terminal of the first comparator is connected to the input terminal of the logic control circuit; the input terminal of the logic control circuit is also connected to the output terminal of the timer circuit, and the output terminal of the logic control circuit is connected to the power stage circuit; the input terminal of the timer circuit is connected to the input voltage and the output voltage.

Optionally, the power stage circuit includes a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch and an energy storage inductor; The source of the first MOS switch is the input end of the power stage circuit, the drain of the first MOS switch is respectively connected to the drain of the second MOS switch and one end of the energy storage inductor; the source of the second MOS switch is grounded; the other end of the energy storage inductor is respectively connected to the drain of the third MOS switch and the drain of the fourth MOS switch; the source of the third MOS switch is grounded; the source of the fourth MOS switch is the output end of the power stage circuit; the drain of the second MOS switch and the drain of the third MOS switch are also connected to one end of the sampling resistor; the gate of the first MOS switch, the gate of the second MOS switch, the gate of the third MOS switch and the gate of the fourth MOS switch are all connected to the output end of the logic control circuit.

Optionally, the timer circuit includes a second comparator, a third comparator, a fourth comparator and an AND gate; The positive input terminal of the second comparator is connected to the output voltage, the reverse input terminal of the second comparator is connected to the input voltage, and the output terminal of the second comparator is connected to the input terminal of the logic control circuit; the positive input terminal of the third comparator is connected to the output voltage, the reverse input terminal of the third comparator is connected to the input voltage, and the output terminal of the third comparator is connected to the first input terminal of the AND gate; the positive input terminal of the fourth comparator is connected to the input voltage, the reverse input terminal of the fourth comparator is connected to the output voltage, and the output terminal of the fourth comparator is connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the input terminal of the logic control circuit.

Optionally, when VIN is greater than VOUT and the difference between VIN and VOUT exceeds the threshold range, the power control circuit operates in BUCK mode, and the sampling resistor, the first comparator and the differential amplifier form a valley current mode loop; When VIN is less than VOUT and the difference between VIN and VOUT exceeds the threshold range, the power control circuit operates in BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop; When the difference between VIN and VOUT is within the threshold range, the power control circuit operates in BUCK-BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop; Wherein, VIN is the input voltage and VOUT is the output voltage.

Optionally, when the power control circuit operates in BUCK mode, the third comparator calculates the time when the first MOS switch and the fourth MOS switch are turned on together, and the valley current mode loop determines the time when the second MOS switch and the fourth MOS switch are turned on together; When the power control circuit operates in BOOST mode, the fourth comparator calculates the time when the first MOS switch and the fourth MOS switch are turned on together; the peak current mode loop determines the time when the first MOS switch and the third MOS switch are turned on together; When the power control circuit operates in the BUCK-BOOST mode, the second comparator calculates the time when the second MOS switch and the fourth MOS switch are turned on together; the third comparator and the fourth comparator calculate the time when the first MOS switch and the fourth MOS switch are turned on together; and the peak current mode loop determines the time when the first MOS switch and the third MOS switch are turned on together.

According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects: The power control circuit provided by the present invention adopts self-adjusting on time valley current mode control in BUCK mode, and self-adjusting off time peak current mode control in BUCK-BOOST mode and BOOST mode, thereby avoiding the output voltage undershoot and overshoot problems caused by the inability of the loop working point to change suddenly when the mode is switched.

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative labor are within the scope of protection of the present invention.

In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

As shown in FIG2 , the power control circuit based on the peak-valley current mode provided in this embodiment includes: a power stage circuit (dashed frame portion), a differential amplifier Gm, a first comparator COMP1, a timer Timer circuit, a logic control circuit Logic, an output resistor Rout, an output capacitor Cout, and a sampling resistor Rsns.

The input end of the power stage circuit is connected to the input voltage VIN, and the output end of the power stage circuit is respectively connected to one end of the output resistor Rout, one end of the output capacitor Cout, one end of the sampling resistor Rsns, and the reverse input end of the differential amplifier Gm; the other end of the output resistor Rout and the other end of the output capacitor Cout are grounded; one end of the sampling resistor Rsns is also connected to the positive input end of the first comparator COMP1, and the other end of the sampling resistor Rsns is grounded; the differential amplifier G The positive input terminal of m is connected to the reference voltage VREF, the output terminal of the differential amplifier Gm is connected to the negative input terminal of the first comparator COMP1; the output terminal of the first comparator COMP1 is connected to the input terminal of the logic control circuit Logic; the input terminal of the logic control circuit Logic is also connected to the output terminal of the Timer circuit, and the output terminal of the logic control circuit Logic is connected to the power stage circuit; the input terminal of the Timer circuit is connected to the input voltage VIN and the output voltage VOUT.

As shown in FIG2 , the power stage circuit provided in this embodiment includes a first MOS switch A, a second MOS switch B, a third MOS switch C, a fourth MOS switch D, and an energy storage inductor IND. The source of the first MOS switch A is the input end of the power stage circuit, and the drain of the first MOS switch A is connected to the drain of the second MOS switch B and one end of the energy storage inductor IND respectively; the source of the second MOS switch B is grounded; the other end of the energy storage inductor IND is connected to the drain of the third MOS switch C and the drain of the fourth MOS switch D respectively; the source of the third MOS switch C is grounded; the source of the fourth MOS switch D is the output end of the power stage circuit. end; the drain of the second MOS switch B and the drain of the third MOS switch C are also connected to one end of the sampling resistor Rsns, the drain of the second MOS switch B is the switching point (SW1), and the drain of the third MOS switch C is the switching point 2 (SW2); the gate of the first MOS switch A, the gate of the second MOS switch B, the gate of the third MOS switch C, and the gate of the fourth MOS switch D are all connected to the output end of the logic control circuit Logic.

As shown in FIG. 3 , the Timer circuit provided by this embodiment includes a second comparator COMPA, a third comparator COMPB, a fourth comparator COMPC, and an AND gate.

The positive input terminal of the second comparator COMPA is connected to the output voltage VOUT, the reverse input terminal of the second comparator COMPA is connected to the input voltage VIN, the first switch S1 and the first capacitor C1, the reverse input terminal of the second comparator COMPA is connected to the first current I1=input voltage VIN/first resistor R1, the output terminal of the second comparator COMPA is connected to the input terminal of the logic control circuit Logic; the positive input terminal of the third comparator COMPB is connected to the output voltage VOUT, the reverse input terminal of the third comparator COMPB is connected to the input voltage VOUT, and the reverse input terminal of the third comparator COMPB is connected to the input voltage VIN. The input voltage VIN, the second switch S2, the second resistor R2 and the second capacitor C2 are connected, and the output terminal of the third comparator COMPB is connected to the first input terminal of the AND gate; the positive input terminal of the fourth comparator COMPC is connected to the input voltage VIN, the reverse input terminal of the fourth comparator COMPC is connected to the output voltage VOUT, the third switch S3, the second resistor R2 and the second capacitor C2, and the output terminal of the fourth comparator COMPC is connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the input terminal of the logic control circuit Logic.

The working principle of the power control circuit provided in this embodiment is as follows: the reference voltage VREF and the voltage feedback signal VFB of VOUT are differentially amplified to generate a current control signal Vc, the inductor current is sampled at switch B and switch C, and generates an inductor current sampling signal VSNS after flowing through Rsns; VSNS is compared with Vc to generate a pulse width modulation signal PWM; the Timer circuit generates a T1 signal (the output signal of the second comparator COMPA) and a T2 signal (the output signal of the AND gate) by monitoring the VIN and VOUT voltages; the PWM, T1 signal and T2 signal jointly control switches A, B, C, and D to achieve voltage regulation of VOUT.

The circuit for generating the T1 signal and the T2 signal is shown in FIG3. When VIN is greater than VOUT, and the difference between VIN and VOUT exceeds the threshold range, the power control circuit provided in the present embodiment operates in the BUCK mode, and the circuit formed by the third comparator COMPB calculates the time when switch A and switch D are turned on together; the valley current mode loop determines the time when switch B and switch D are turned on together. Among them, the sampling resistor Rsns, the first comparator COMP1 and the differential amplifier Gm constitute the valley current mode loop. When VIN is less than VOUT, and the difference between VIN and VOUT exceeds the threshold range, the power control circuit provided in the present embodiment operates in the BOOST mode, and the circuit formed by the fourth comparator COMPC calculates the time when switch A and switch D are turned on together; the peak current mode loop determines the time when switch A and switch C are turned on together. The sampling resistor Rsns, the first comparator COMP1 and the differential amplifier Gm form a peak current mode loop. When VIN is close to VOUT, the power control circuit provided by the present embodiment operates in the BUCK-BOOST mode, the circuit formed by the second comparator COMPA calculates the time when the switch B and the switch D are turned on together; the circuit formed by the third comparator COMPB and the fourth comparator COMPC calculates the time when the switch A and the switch D are turned on together; the peak current mode loop determines the time when the switch A and the switch C are turned on together. The sampling resistor Rsns, the first comparator COMP1 and the differential amplifier Gm form a peak current mode loop.

The T1 signal and the T2 signal are adjusted along with the self-regulation of VIN and VOUT. The power control circuit provided by the present embodiment will automatically adjust the common conduction time of switch A and switch C, or the common conduction time of switch B and switch D according to the values of the T1 signal and the T2 signal, so that the charge and discharge of the energy storage inductor IND are balanced. Relying on the peak current mode loop with self-adjustment of the off time or the valley current mode loop with self-adjustment of the on time, the power control circuit provided by the present embodiment keeps the switching frequency almost unchanged in the full voltage range.

The power control circuit provided in this embodiment adopts self-adjusting on time valley current mode control in BUCK mode, and self-adjusting off time peak current mode control in BUCK-BOOST mode and BOOST mode, thereby avoiding the output voltage undershoot and overshoot problems caused by the inability of the loop operating point to change suddenly when switching between modes.

FIG4 is a timing diagram of the switch signal and the inductor current signal _IL in the BUCK working mode. As shown in FIG4, when VIN is greater than VOUT and the difference between VIN and VOUT exceeds the threshold range, the power control circuit provided in the present embodiment operates in the valley current mode BUCK mode, switch C is turned off, and switch D remains on. At the beginning of each switching cycle, switch A is turned on, switch B is turned off, and the inductor current increases linearly with time, and the Timer circuit starts timing. When the preset time is reached, the T2 signal turns off switch A and turns on switch B, and the inductor current decreases linearly with time. When the inductor current sampling signal VSNS reaches the valley value set by Vc, PWM turns off switch B and turns on switch A, thereby entering the next switching cycle.

FIG5A and FIG5B are timing diagrams of the switch signal and the inductor current signal _IL in the BUCK-BOOST working mode, wherein FIG5A is a timing diagram of the switch signal and the inductor current signal _IL when VIN＞=VOUT, and FIG5B is a timing diagram of the switch signal and the inductor current signal _IL when VIN＜=VOUT. As shown in FIG5A and FIG5B, when VIN is close to VOUT (i.e., the difference between VIN and VOUT is within the threshold range), whether VIN＞=VOUT or VIN＜=VOUT, the power control circuit provided in this embodiment works in the same BUCK-BOOST mode. At the beginning of each switching cycle, switch A and switch C are turned on, switch B and switch D are turned off, and the inductor current increases linearly with time. When the inductor current sampling signal VSNS reaches the peak value set by Vc, PWM turns off switch C and turns on switch D. At the same time, the Timer circuit starts timing. When the preset time is reached, the T2 signal turns off switch A and turns on switch B. At the same time, the Timer circuit starts timing. When the preset time is reached, the T1 signal turns off switches B and D, and turns on switches A and C, and the power control circuit provided by this embodiment enters the next switching cycle.

FIG6 is a timing diagram of the switch signal and the inductor current signal _IL in the BOOST working mode. As shown in FIG6, when VIN is less than VOUT and the difference between VIN and VOUT exceeds the threshold range, the power control circuit provided in the present embodiment works in the peak current mode BOOST mode, and switch A remains normally on in each switching cycle, and switch B remains normally off in each switching cycle. At the beginning of each switching cycle, switch C is turned on and switch D is turned off. The inductor current increases linearly with time. When the inductor current sampling signal VSNS reaches the peak value set by Vc, PWM turns off switch C and turns on switch D. At the same time, the Timer circuit starts timing. When the preset time is reached, the T2 signal turns off switch D and turns on switch C, thereby entering the next switching cycle.

The waveforms when switching between BUCK mode and BUCK-BOOST mode are shown in Figure 7. Under the same conditions, compared with the transient waveform of the existing technology, the change of VOUT is greatly reduced.

This article uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. At the same time, for ordinary technicians in this field, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In general, the content of this specification should not be understood as limiting the present invention.

A: First MOS switch/switch B: Second MOS switch/switch C: Third MOS switch/switch D: Fourth MOS switch/switch COMP1: First comparator COMPA: Second comparator COMPB: Third comparator COMPC: Fourth comparator C1: First capacitor C2: Second capacitor Cout: Output capacitor Gm: Differential amplifier IND: Energy storage inductor I1: First current I _L : Inductor current signal Logic: Logic control circuit PWM: Pulse width modulation signal R1: First resistor R2: Second resistor Rsns: Sampling resistor S1: First switch S2: Second switch S3: Third switch SW1: Switching point 1 SW2: Switching point 2 T1, T2: signal Timer: timer circuit Vc: control signal VFB: voltage feedback signal VIN: input voltage VREF: reference voltage VSNS: inductor current sampling signal VOUT: output voltage Rout: output resistance

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technical personnel in this field, other drawings can be obtained based on these drawings without paying creative labor.

Figure 1 is a schematic diagram of BUCK-BOOST. Figure 2 is a schematic diagram of a power control circuit based on a peak-valley current mode provided by the present invention. Figure 3 is a schematic diagram of a timer circuit provided by the present invention. Figure 4 is a timing diagram of a switch signal and an inductor current signal in BUCK working mode. Figures 5A and 5B are timing diagrams of a switch signal and an inductor current signal in BUCK-BOOST working mode. Figure 6 is a timing diagram of a switch signal and an inductor current signal in BOOST working mode. Figure 7 is a waveform diagram when switching between BUCK mode and BUCK-BOOST mode.

A: First MOS switch

B: Second MOS switch

C: Third MOS switch

D: Fourth MOS switch

COMP1: First comparator

Cout: output capacitance

Gm: Differential amplifier

IND: Energy storage inductor

Logic: logic control circuit

PWM: Pulse Width Modulation Signal

Rsns: sampling resistor

SW1: Switch point 1

SW2: Switch point 2

T1, T2: signal

Timer: Timer circuit

Vc: control signal

VFB: voltage feedback signal

VIN: Input voltage

VREF: reference voltage

VSNS: Inductor current sampling signal

VOUT: output voltage

Rout: output resistance

Claims (7)

A power control circuit based on a peak-valley current mode includes: a power stage circuit, a differential amplifier, a first comparator, a timer circuit, a logic control circuit, and a sampling resistor; The input end of the power stage circuit is connected to the input voltage, and the output end of the power stage circuit is respectively connected to one end of the sampling resistor and the reverse input end of the differential amplifier; one end of the sampling resistor is also connected to the positive input end of the first comparator, and the other end of the sampling resistor is grounded; the positive input end of the differential amplifier is connected to the reference voltage, and the output end of the differential amplifier is connected to the reverse input end of the first comparator; the output end of the first comparator is connected to the input end of the logic control circuit; the input end of the logic control circuit is also connected to the output end of the timer circuit, and the output end of the logic control circuit is connected to the power stage circuit; the input end of the timer circuit is connected to the input voltage and the output voltage. A power control circuit based on a peak-valley current mode as described in claim 1, wherein the power stage circuit includes a first MOS switch, a second MOS switch, a third MOS switch, a fourth MOS switch and an energy storage inductor; The source of the first MOS switch is the input end of the power stage circuit, the drain of the first MOS switch is respectively connected to the drain of the second MOS switch and one end of the energy storage inductor; the source of the second MOS switch is grounded; the other end of the energy storage inductor is respectively connected to the drain of the third MOS switch and the drain of the fourth MOS switch; the source of the third MOS switch is grounded; the source of the fourth MOS switch is the output end of the power stage circuit; the drain of the second MOS switch and the drain of the third MOS switch are also connected to one end of the sampling resistor; the gate of the first MOS switch, the gate of the second MOS switch, the gate of the third MOS switch and the gate of the fourth MOS switch are all connected to the output end of the logic control circuit. A power control circuit based on a peak-valley current mode as described in claim 2, wherein the timer circuit includes a second comparator, a third comparator, a fourth comparator, and a gate; The positive input terminal of the second comparator is connected to the output voltage, the reverse input terminal of the second comparator is connected to the input voltage, and the output terminal of the second comparator is connected to the input terminal of the logic control circuit; the positive input terminal of the third comparator is connected to the output voltage, the reverse input terminal of the third comparator is connected to the input voltage, and the output terminal of the third comparator is connected to the first input terminal of the AND gate; the positive input terminal of the fourth comparator is connected to the input voltage, the reverse input terminal of the fourth comparator is connected to the output voltage, and the output terminal of the fourth comparator is connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the input terminal of the logic control circuit. A power control circuit based on a peak-valley current mode as described in claim 3, wherein, when VIN is greater than VOUT and the difference between VIN and VOUT exceeds the threshold range, the power control circuit operates in a BUCK mode, and the sampling resistor, the first comparator and the differential amplifier form a valley current mode loop; When VIN is less than VOUT and the difference between VIN and VOUT exceeds the threshold range, the power control circuit operates in a BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop; When the difference between VIN and VOUT is within the threshold range, the power control circuit operates in a BUCK-BOOST mode, and the sampling resistor, the first comparator and the differential amplifier form a peak current mode loop; Wherein, VIN is the input voltage and VOUT is the output voltage. A power control circuit based on a peak-valley current mode as described in claim 4, wherein when the power control circuit operates in a BUCK mode, the third comparator calculates the time when the first MOS switch and the fourth MOS switch are turned on together, and the valley current mode loop determines the time when the second MOS switch and the fourth MOS switch are turned on together; When the power control circuit operates in a BOOST mode, the fourth comparator calculates the time when the first MOS switch and the fourth MOS switch are turned on together; and the peak current mode loop determines the time when the first MOS switch and the third MOS switch are turned on together; When the power control circuit operates in the BUCK-BOOST mode, the second comparator calculates the time when the second MOS switch and the fourth MOS switch are turned on together; the third comparator and the fourth comparator calculate the time when the first MOS switch and the fourth MOS switch are turned on together; and the peak current mode loop determines the time when the first MOS switch and the third MOS switch are turned on together. A power control circuit based on a peak-valley current mode as described in any one of claim items 1-5, further comprising: an output resistor and an output capacitor; The output end of the power stage circuit is also connected to one end of the output resistor and one end of the output capacitor respectively; the other end of the output resistor and the other end of the output capacitor are grounded. An inductive switching buck-boost DC/DC voltage regulator comprises: a power control circuit based on a peak-valley current mode as described in any one of claims 1-6.