CN106992679B - Dual-fixed-time buck-boost switching type power circuit and control circuit and method thereof - Google Patents
Dual-fixed-time buck-boost switching type power circuit and control circuit and method thereof Download PDFInfo
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- CN106992679B CN106992679B CN201610037181.4A CN201610037181A CN106992679B CN 106992679 B CN106992679 B CN 106992679B CN 201610037181 A CN201610037181 A CN 201610037181A CN 106992679 B CN106992679 B CN 106992679B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
Abstract
The invention provides a buck-boost switching type power circuit with double fixed time, and a control circuit and a control method thereof. This two fixed time buck-boost switching power supply circuit contains: a voltage step-down circuit, comprising: an inductor having a first end and a second end; a first power switch of a voltage reduction circuit, one end of which is coupled with the first end of the inductor, and the other end of which is coupled with an input voltage; one end of the power element of the voltage reduction circuit is coupled with the first end of the inductor, and the other end of the power element of the voltage reduction circuit is grounded; a boost circuit, comprising: the inductor; a first power switch of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is grounded; and a power element of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is coupled with an output voltage; and a control circuit.
Description
Technical Field
The present invention relates to a dual constant time (dual constant time) buck-boost switching power circuit, and more particularly, to a current mode or voltage mode buck-boost switching power circuit requiring two sets of constant time. The invention also relates to a control circuit and a method for controlling the buck-boost switching power supply circuit.
Background
Referring to fig. 1A, a method for controlling a buck-boost switching power circuit is disclosed in U.S. Pat. No. 6166527. The buck-boost switching power circuit includes an inductor L, four power switches a, B, C, D, and a control circuit 20. The control circuit 20 controls the switching of the four power switches a, B, C, D to convert the input voltage Vin to the output voltage Vout, wherein the input voltage Vin may be higher or lower than the output voltage Vout, so that the power circuit may need to perform step-down or step-up conversion. In the control circuit 20, the error amplifier 22 compares the feedback signal FB (information indicating the output voltage Vout) with the reference voltage Vref to generate an error amplified signal Vea. PWM comparators 24,25 compare the error amplified signal Vea with the voltage waveforms VX and VY, respectively, and the logic circuit 29 generates switch control signals VA, VB, VC, VD according to the comparison results of the PWM comparators 24,25 to control the power switches a, B, C, D, respectively.
The relationship among the error amplified signal Vea, the voltage waveforms VX and VY, and the switch control signals VA, VB, VC, VD is as shown in fig. 1B, when the error amplified signal Vea falls between the voltages V1 and V2, the power circuit performs pure step-down conversion, when the error amplified signal Vea falls between the voltages V2 and V3, the power circuit performs step-up and step-down conversion, and when the error amplified signal Vea falls between the voltages V3 and V4, the power circuit performs pure step-up conversion. In the pure step-down conversion mode, the power switch C is kept disconnected and the power switch D is kept conducted, and in the pure step-up conversion mode, the power switch A is kept conducted and the power switch B is kept disconnected. In the buck-boost conversion mode, as shown in the figure, the switch control signals VA and VB are generated according to the relative relationship between the error amplification signal Vea and the voltage waveform VX, and the switch control signals VC and VD are generated according to the relative relationship between the error amplification signal Vea and the voltage waveform VY, that is, the power circuit performs a hybrid operation of boosting (switch C and D operations) and stepping down (switch a and B operations).
The above prior art is characterized by comprising a pure voltage-increasing conversion mode, a pure voltage-decreasing conversion mode and a voltage-increasing and decreasing conversion mode, and must comprise a voltage-increasing and decreasing conversion section, i.e. V2 must be smaller than V3, otherwise the system is unstable. In the buck-boost conversion mode, four switches are switched in any cycle, which results in switching loss (switching loss), and thus the energy loss is increased. The conflict of these two features is a major disadvantage of this prior art.
Fig. 2A shows another prior art structure of US 7176667, in which an error amplifier 22 is used to generate two sets of error amplified signals Vea1 and Vea2, which are alternatively inputted to a PWM comparator 24 for comparison with a voltage waveform OSC. In addition, a fixed pulse width generating circuit 26 is provided in the circuit, and the logic circuit 29 generates switch control signals VA, VB, VC, VD according to the output of the PWM comparator 24 and the output of the fixed pulse width generating circuit 26, and controls the power switches a, B, C, D, respectively.
Referring to fig. 2B, the united states patent US 7176667 is divided into four switching modes, except for a pure buck switching mode M1 and a pure boost switching mode M4, an intermediate buck switching mode M2 and an intermediate boost switching mode M3 are further provided therebetween, in the intermediate buck switching mode M2, the switching control signals VA and VB follow the output of the PWM comparator 24 and the switching control signals VC and VD are fixed pulse widths, and in the intermediate buck switching mode M3, the switching control signals VC and VD follow the output of the PWM comparator 24 and the switching control signals VA and VB are fixed pulse widths.
The drawback of the prior art is that the control mechanism of the four switching modes is complicated, requiring additional fixed pulse width generation circuit 26 and other circuit elements, and two intermediate switching modes (M2 and M3) indicate increased opportunities for the circuit to operate in this region, while four power switches in the intermediate switching modes are all activated, increasing switching losses and power consumption.
In addition, the prior art US 6166527 and US 7176667 are fixed frequency technologies, which are limited by the relationship between the switching frequency and the bandwidth, and the response of the load change of the technologies is relatively slow; furthermore, the above-mentioned prior art needs more complicated circuit assistance in the implementation of Pulse Frequency Modulation (PFM), for example, when the load current is extremely small, or cannot achieve PFM, for example, when the input voltage Vin is close to the output voltage Vout; the TPS63020 controller of the prior art shown in fig. 3 is also a constant frequency technology and includes a buck-boost conversion mode, and an average current mode control (average current mode) is further required to add a slope compensation circuit (slope compensation) to suppress the sub-harmonic oscillation (sub-harmonic oscillation) tendency.
Fig. 4A shows another prior art architecture of US 2011/0156685a1, the buck-boost switching power circuit includes an inductor L, four power switches a, B, C, D, and a control circuit 30. The control circuit 30 controls the switching of the four power switches a, B, C, D to convert the input voltage Vin to the output voltage Vout. In the control circuit 30, an error amplifier 32 compares a feedback signal FB (information indicating the output voltage Vout) with a reference voltage Vref to generate an error amplification signal, which is input to a PWM comparator 34. In addition, the circuit obtains the signal related to the inductor current, and inputs the signal to the PWM comparator 34 for comparison with the error amplified signal. The output of the PWM comparator 34 is delivered to the on-time generation circuit 37 to generate the on-time of the switch. The driving circuit 39 generates the switch driving signals VA, VB, VC, VD according to the generated on-time, and controls the power switches a, B, C, D. This prior art is characterized in that only one PWM comparator 34 is required in the circuit, since only one set of on-times needs to be generated. Although this prior art can realize the buck-boost switching power circuit with a very simple circuit, it has the disadvantage that, no matter the input power is larger than, smaller than, or close to the output voltage, the circuit is operated in the buck-boost conversion mode, and the four switches a, B, C, and D are switched every operation cycle, as shown in fig. 4B and 4C, the switches a and C are turned on (the current direction is as a solid line), and then the switches B and D are turned on, and the switching loss is large.
In view of the above drawbacks of the prior art, the present invention provides a buck-boost switching power circuit, which has a fast load change response; it does not require slope compensation; it can be applied to PFM operation without complex circuit control; further, it is possible to achieve a pure buck conversion mode and a pure boost conversion mode, and preferably without a buck-boost conversion mode or an intermediate mode.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a buck-boost switching power circuit which has quick load change response; it does not require slope compensation; it can be applied to PFM operation without complex circuit control; further, it is possible to achieve a pure buck conversion mode and a pure boost conversion mode, and preferably without a buck-boost conversion mode or an intermediate mode.
To achieve the above object, in one aspect, the present invention provides a fixed-time buck-boost switching power circuit, including: the voltage reduction circuit comprises an inductor, a first capacitor and a second capacitor, wherein the inductor is provided with a first end and a second end; a first power switch of a voltage reduction circuit, one end of which is coupled with the first end of the inductor, and the other end of which is coupled with an input voltage; one end of the power element of the voltage reduction circuit is coupled with the first end of the inductor, and the other end of the power element of the voltage reduction circuit is grounded; a boost circuit including the inductor; a first power switch of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is grounded; and a power element of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is coupled with an output voltage; and a control circuit, it produces a first fixed time (constant time) and a second fixed time, the first fixed time controls the voltage-reducing circuit, the second fixed time controls the voltage-increasing circuit; the first fixed time is a fixed-off time (constant-on time), the first power switch of the voltage-reducing circuit is not conducted within the fixed-off time, and the second fixed time is a fixed-on time (constant-on time), so that the first power switch of the voltage-boosting circuit is conducted within the fixed-on time.
In the buck-boost switching power supply circuit, the power element of the buck circuit or the power element of the boost circuit may be a switch or a diode.
To achieve the above object, from another perspective, the present invention provides a control circuit for controlling a constant-time buck-boost switching power circuit, including: the voltage reduction circuit comprises an inductor, a first capacitor and a second capacitor, wherein the inductor is provided with a first end and a second end; a first power switch of a voltage reduction circuit, one end of which is coupled with the first end of the inductor, and the other end of which is coupled with an input voltage; one end of the power element of the voltage reduction circuit is coupled with the first end of the inductor, and the other end of the power element of the voltage reduction circuit is grounded; a boost circuit, comprising: the inductor; a first power switch of a booster circuit, one end of which is coupled with the second end of the inductor and the other end of which is grounded, a power element of the booster circuit, one end of which is coupled with the second end of the inductor and the other end of which is coupled with an output voltage; the control circuit comprises an error amplifier for comparing a feedback signal related to an output voltage with a reference voltage to generate an error amplification signal; a first PWM comparator for comparing a signal related to a first inductor current or a first sawtooth wave signal with the error amplification signal; a second PWM comparator for comparing a signal related to a second inductor current or a second sawtooth wave signal with the error amplification signal; a shift signal generator for generating a shift signal by a phase difference between the signal related to the first inductor current or the first sawtooth wave signal and the signal related to the second inductor current or the second sawtooth wave signal; a first fixed time generator for generating the first fixed time according to the output of the first PWM comparator; a second fixed time generator for generating the second fixed time according to the output of the second PWM comparator; a first driving circuit, which generates a voltage-reducing switch control signal according to the output of the first fixed time generator to control the voltage-reducing circuit; and a second driving circuit, which generates a boost switch control signal according to the output of the second fixed time generator to control the boost circuit. The first fixed time is a fixed-off time (constant-on time), the first power switch of the voltage-reducing circuit is not conducted within the fixed-off time, and the second fixed time is a fixed-on time (constant-on time), so that the first power switch of the voltage-boosting circuit is conducted within the fixed-on time.
In the buck-boost switching power supply circuit, the displacement signal in the control circuit is preferably greater than a peak-to-valley value of the first inductor current related signal or the first sawtooth wave signal, so that the buck-boost switching power supply circuit is only operated in a buck conversion mode or a boost conversion mode, but not in the buck-boost conversion mode.
To achieve the above object, in another aspect, the present invention provides a method for controlling a fixed-time buck-boost switching power circuit, including: the voltage reduction circuit comprises an inductor, a first capacitor and a second capacitor, wherein the inductor is provided with a first end and a second end; a first power switch of a voltage reduction circuit, one end of which is coupled with the first end of the inductor, and the other end of which is coupled with an input voltage; one end of the power element of the voltage reduction circuit is coupled with the first end of the inductor, and the other end of the power element of the voltage reduction circuit is grounded; a boost circuit including the inductor; a first power switch of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is grounded; a power element of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is coupled with an output voltage; the control method comprises the following steps: generating a first fixed time (constant time) for controlling the buck circuit and a second fixed time for controlling the boost circuit; the first fixed time is a fixed-off time (constant-on time), the first power switch of the voltage-reducing circuit is not conducted within the fixed-off time, and the second fixed time is a fixed-on time (constant-on time), so that the first power switch of the voltage-boosting circuit is conducted within the fixed-on time.
The purpose, technical content, features and effects of the present invention will be more readily understood through the following detailed description of specific embodiments.
Drawings
FIG. 1A is a schematic diagram of a buck-boost switching power circuit and related circuitry;
FIG. 1B is a schematic diagram of signal waveforms corresponding to the circuit of FIG. 1A;
FIG. 2A is a schematic diagram of a buck-boost switching power circuit and related circuitry;
FIG. 2B is a state transition table (state machine) corresponding to the circuit of FIG. 2A;
FIG. 3 is a schematic diagram of a buck-boost switching power circuit and related circuitry;
FIG. 4A is a schematic diagram of a buck-boost switching power circuit and related circuitry;
FIG. 4B is a schematic diagram of signal waveforms corresponding to the circuit of FIG. 4A;
FIG. 4C is a schematic diagram of the current direction corresponding to the circuit of FIG. 4A;
FIG. 5 shows a first embodiment of a buck-boost switching power supply circuit of the present invention;
FIGS. 6A and 6B are schematic signal waveforms corresponding to the circuit of FIG. 5;
FIG. 7A is a schematic diagram of a buck-boost circuit and related circuitry;
FIG. 7B is a schematic diagram showing a preferred current direction of the buck-boost switching power supply circuit according to the embodiment of the present invention;
FIG. 8 shows a buck-boost switching power supply circuit according to a second embodiment of the present invention;
FIGS. 9A and 9B are schematic signal waveforms corresponding to the circuit of FIG. 8;
FIGS. 10 and 11 show two embodiments of the voltage controlled buck-boost switching power supply circuit of the present invention;
fig. 12-14 show additional embodiments of buck-boost switching power supply circuits of the present invention, in which diodes are used as power devices.
Description of the symbols in the drawings
20 control circuit
22 buck-boost switching power circuit
24,25,34 PWM comparator
32 error amplifier
39 drive circuit
30 control circuit
40,45 buck-boost switching power circuit
50,55,60,65,70,75 and 80 buck-boost switching power circuit
100 step-down circuit
200 boost circuit
300 control circuit
301-level control circuit
302 error amplifier
303 displacement signal
304,306 PWM comparator
310,314 drive circuit
316 zero current detection circuit
A, B, C, D power switch
Signals related to the inductor current of CSBCK, CSBST
EAO error amplified signal
FB feedback signal
L-shaped inductor
OSC oscillation waveform
VA, VB, VC, VD switch driving signal
Vea, Vea1, Vea2 error amplified signal
Vin input voltage
Vout output voltage
Vref reference voltage
VX, VY sawtooth waveform
Detailed Description
Referring to fig. 5, a current-controlled dual-fixed-time architecture is taken as an example to illustrate a first embodiment of the present invention. The buck-boost switching power circuit 50 of the present embodiment includes a buck circuit 100, a boost circuit 200, and a control circuit 300. The voltage reduction circuit 100 includes an inductor L and two power switches a and B; the boost circuit 200 includes an inductor L and two power switches C and D. The control circuit 300 controls the switching of the four power switches a, B, C, D to convert the input voltage Vin into the output voltage Vout. In the control circuit 300, the error amplifier 302 compares the feedback signal FB (information indicating the output voltage Vout) with the reference voltage Vref to generate an error amplified signal EAO, which is input to the PWM comparator 304 and the PWM comparator 306. In addition, the circuit obtains the signal CSBCK related to the inductor current, and inputs the signal CSBCK to the PWM comparator 304 for comparing with the error amplification signal EAO. Furthermore, the circuit generates a shift signal 303, which is superimposed on the inductor current related signal CSBCK to become another inductor current related signal CSBST, and is inputted into the PWM comparator 306. The output of the PWM comparator 304 is delivered to a fixed non-conduction time generation circuit 308 to generate the non-conduction time of the switch. The driving circuit 310 generates the switch driving signals VA and VB to control the power switches a and B according to the generated off-time. The output of the PWM comparator 306 is delivered to a fixed on-time generation circuit 312 to generate the on-time of the switch. The driving circuit 314 generates the switch driving signals VC, VD according to the generated on-time to control the power switches C, D.
Referring to fig. 6A, when the buck-boost switching power circuit 50 operates in the pure buck conversion mode, EAO does not intersect with the signal CSBST related to the inductor current, so VC is constantly low, the switch C is constantly non-conductive, VD is constantly high, and the switch D is constantly conductive; switch a is turned on at t0, at which time the signal CSBCK associated with the inductor current starts to rise until EAO intersects the signal CSBCK associated with the inductor current, at which time t1, switch a is turned off at t1, continues to be turned off for a fixed off-time TOFF, and is then turned on again at t2, and so on; the above operation control makes the present pure step-down conversion Mode a Peak Current Mode (Peak Current Mode). Referring to fig. 6B, when the buck-boost switching power circuit 50 operates in the pure boost conversion mode, EAO does not intersect with the signal CSBCK related to the inductor current, so VB is constantly low, the switch B is not turned on, VA is constantly high, and the switch a is constantly turned on; switch C is not turned on at T0, at which time the inductor current begins to drop until EAO crosses signal CSBST associated with the inductor current, switch C is turned on at T1 and continues to be turned on for a fixed on-time TON, then is turned off again at T2, and so on; the above operation control makes the present pure step-up conversion mode a Valley current mode (Valley current mode).
The present invention is characterized in that two sets of fixed time, one is a fixed on-time and one is a fixed off-time, are generated according to the output results of the PWM comparator 308 and the PWM comparator 312 for controlling the step-up circuit 200 and the step-down circuit 100, so that the operation in the pure step-up conversion mode and the pure step-down conversion mode is performed in a fixed time, and both the two operation modes have the advantages of fast load response and no slope compensation.
Referring to fig. 7A, the buck-boost circuit 40 includes a buck circuit 100 and a boost circuit 200, where the buck-boost circuit 40 is in a pure buck conversion mode when the input voltage Vin is greater than the output voltage Vout, and in a pure boost conversion mode when the input voltage Vin is less than the output voltage Vout, and when the input voltage Vin is close to the output voltage Vout, it is desirable that the buck-boost circuit 40 does not operate in the buck-boost conversion mode as shown in fig. 4C or fig. 1B, so as to achieve the effect of reducing the switching loss; preferably, as shown by the solid arrow in fig. 7B, the switches a and D of the buck-boost circuit 45 are turned on for as long as possible without entering the intermediate mode or the buck-boost conversion mode.
Referring to fig. 5, another feature of the present invention is that the step-down circuit 100 is controlled according to the fixed off-time TOFF generated by the fixed off-time generator 308, and the step-down circuit 200 is controlled according to the fixed on-time TON generated by the fixed on-time generator 312, such combination allowing the switches a and D to be extended without limitation. Further, the shift signal 303 in the control circuit 300 is preferably selected such that the bottom of CSBST is greater than the peak of CSBCK (which is equivalent to making the shift signal 303 greater than the peak-bottom of CSBCK), so that the control circuit 300 of the present invention can make the buck-boost switching power circuit 50 be in the buck conversion mode when the input voltage is greater than the output voltage, and in the boost conversion mode when the input voltage is less than the output voltage, and when the input voltage Vin is close to the output voltage Vout, because the slope of the inductor current is very gentle, and because of the above-mentioned combination of the conducting/non-conducting time and the preferred selection of the shift signal, the switches a, D can be extended without limitation, and at this time, the buck-boost switching power circuit 50 operates in the Pulse Frequency Modulation (PFM) mode. In many of the prior art of the buck-boost switching power supply circuits including four power devices, the buck switching mode is performed when the input voltage Vin is greater than the output voltage Vout, the boost switching mode is performed when the input voltage Vin is less than the output voltage Vout, and the buck-boost switching mode or the intermediate mode is performed when the input voltage Vin is close to the output voltage Vout.
Another feature of the present invention is that the control circuit for controlling the buck-boost switching power circuit can be operated in a Continuous Conduction Mode (CCM) Mode, and can be easily applied in a Discontinuous Conduction Mode (DCM) Mode and a Pulse Frequency Modulation (PFM) Mode. Referring to fig. 8, for example, but not limited to, a zero current signal generated by a zero current detection circuit 316 is added to the driving circuits 310 and 314, such that when the inductor current decreases from a positive current to a zero current, the switch B or D is controlled to be non-conductive, such that the inductor current is not negative, and the buck-boost switching power circuit 55 operates in the discontinuous conduction mode. As shown in fig. 9A and 9B, the control signals of the power switches a, B, C, D and the waveforms of the inductor currents are used to operate the buck-boost switching power circuit 55 in the discontinuous conduction mode. In addition, under the condition of extremely small load current, the buck-boost switching power circuit 55 will enter the PFM mode, and the frequency will be automatically decreased without a complicated additional control circuit.
Fig. 5 and 8 show a current-controlled buck-boost switching power circuit architecture, but the present invention is also applicable to a voltage-controlled (voltage mode) switching power circuit architecture. Fig. 10 and 11 show the voltage-controlled buck-boost switching power circuits 60,65 of CCM and DCM, respectively, in which one of the input terminals of the PWM comparator 304 receives the error amplification signal EAO, and the other terminal receives the sawtooth signal generated inside the circuit; one of the input terminals of the PWM comparator 306 receives the error amplified signal EAO, and the other terminal receives a sawtooth wave signal generated inside the circuit and adds a shift signal 303. Various methods for generating sawtooth signals and waveforms are known in the art, and are not described herein since they are not essential to the present invention.
The invention is not limited to use in synchronous (synchronous) buck-boost switching power supply circuits having four power switches. Fig. 12-14 illustrate embodiments of different combinations of the boost circuit 200, the buck circuit 100, and the driver circuits 310,314 of fig. 5,8,10, and 11, wherein the secondary control stage circuit 301 is, for example, but not limited to, the secondary control stage circuit 301 of fig. 5,8,10, and 11: fig. 12 shows an embodiment in which switch B is replaced by a diode. The embodiment of fig. 13 wherein switch D is replaced by a diode. FIG. 14 shows an embodiment in which switches B and D are both replaced by diodes. The above embodiments can be applied to the buck-boost switching power circuit in the current mode, the voltage mode, the DCM mode and the CCM mode, and two PWM comparators are used to generate the two sets of fixed on/off time for control.
The present invention has been described in terms of the preferred embodiments, and the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Those skilled in the art will recognize a variety of equivalent variations that are within the spirit of the invention. For example, each of the power switches A, B, C, D may be PMOS or NMOS, and the positive and negative inputs of the PWM comparators 304,306 may be correspondingly inverted; the polarity of the CSBCK, CSBST and the shift signal 303 can be changed accordingly. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above.
Claims (10)
1. A fixed time buck-boost switching power supply circuit, comprising:
a voltage step-down circuit, comprising:
an inductor having a first end and a second end;
a first power switch of a voltage reduction circuit, one end of which is coupled with the first end of the inductor, and the other end of which is coupled with an input voltage; and
one end of the power element of the voltage reduction circuit is coupled with the first end of the inductor, and the other end of the power element of the voltage reduction circuit is grounded;
a boost circuit, comprising:
the inductor;
a first power switch of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is grounded; and
a power element of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is coupled with an output voltage; and
a control circuit, which generates a first fixed time according to a feedback signal related to the output voltage, a reference voltage, and a signal related to a first inductor current or a first sawtooth wave signal, and generates a second fixed time according to the feedback signal related to the output voltage, the reference voltage, and a signal related to a second inductor current or a second sawtooth wave signal, the first fixed time controls the voltage-reducing circuit, the second fixed time controls the voltage-increasing circuit; the first fixed time is a fixed non-conducting time, so that the first power switch of the voltage reduction circuit is not conducted within the fixed non-conducting time, and the second fixed time is a fixed conducting time, so that the first power switch of the voltage boost circuit is conducted within the fixed conducting time; wherein the difference between the signal related to the first inductor current or the first sawtooth wave signal and the signal related to the second inductor current or the second sawtooth wave signal is a shift signal.
2. The constant-time buck-boost switching power circuit of claim 1, wherein the displacement signal is greater than a peak-to-valley value of the first inductor current related signal or greater than a peak-to-valley value of the first sawtooth signal, such that the buck-boost switching power circuit operates only in a buck conversion mode or a boost conversion mode but not in a buck-boost conversion mode, wherein the peak-to-valley value of the first inductor current related signal is a difference between the peak value of the first inductor current related signal and the valley value of the first inductor current related signal, and the peak-to-valley value of the first sawtooth signal is a difference between the peak value of the first sawtooth signal and the valley value of the first sawtooth signal.
3. The fixed-time buck-boost switching power supply circuit of claim 1 or 2, wherein the control circuit comprises:
an error amplifier for comparing the feedback signal related to the output voltage with the reference voltage to generate an error amplified signal;
a first PWM comparator for comparing the signal related to the first inductor current or the first sawtooth wave signal with the error amplification signal;
a second PWM comparator for comparing the signal related to the second inductor current or the second sawtooth wave signal with the error amplification signal;
a displacement signal generator for generating the displacement signal so that the signal related to the first inductive current or the first sawtooth wave signal is different from the signal related to the second inductive current or the second sawtooth wave signal by the displacement signal;
a first fixed time generator for generating the first fixed time according to the output of the first PWM comparator;
a second fixed time generator for generating the second fixed time according to the output of the second PWM comparator;
a first driving circuit, which generates a voltage-reducing switch control signal according to the output of the first fixed time generator to control the voltage-reducing circuit; and
a second drive circuit, which generates a boost switch control signal according to the output of the second fixed time generator to control the boost circuit.
4. The fixed-time buck-boost switching power supply circuit of claim 3, wherein the buck circuit, the boost circuit, the buck switch control signal, and the boost switch control signal are one of the following combinations:
(A)
The power element of the voltage reduction circuit is a second power switch of the voltage reduction circuit;
the power element of the booster circuit is a second power switch of the booster circuit;
the voltage reduction switch control signal is used for controlling a first power switch of the voltage reduction circuit and a second power switch of the voltage reduction circuit; and
the boost switch control signal is used for controlling a first power switch of the boost circuit and a second power switch of the boost circuit;
(II)
The power element of the voltage reduction circuit is a voltage reduction diode;
the power element of the booster circuit is a second power switch of the booster circuit;
the voltage reduction switch control signal is used for controlling a first power switch of the voltage reduction circuit; and
the boost switch control signal is used for controlling a first power switch of the boost circuit and a second power switch of the boost circuit;
(III)
The power element of the voltage reduction circuit is a second power switch of the voltage reduction circuit;
the power element of the booster circuit is a booster diode;
the voltage reduction switch control signal is used for controlling a first power switch of the voltage reduction circuit and a second power switch of the voltage reduction circuit; and
the boost switch control signal is used for controlling a first power switch of the boost circuit; and
(IV)
The power element of the voltage reduction circuit is a voltage reduction diode;
the power element of the booster circuit is a booster diode;
the voltage reduction switch control signal is used for controlling a first power switch of the voltage reduction circuit; and
the boost switch control signal is used for controlling a first power switch of the boost circuit.
5. The constant-time buck-boost switching power supply circuit of claim 4, wherein the displacement signal in the control circuit is greater than a peak-to-valley value of the first inductor current related signal or greater than a peak-to-valley value of the first sawtooth signal, such that
The above (one) has the following features:
in a buck conversion mode, the first power switch of the buck circuit is not turned on for the first fixed time, the second power switch of the buck circuit is switched in reverse phase with the first power switch of the buck circuit when operating in a continuous conduction mode, and in a discontinuous conduction mode, the second power switch of the buck circuit is switched in reverse phase with the first power switch of the buck circuit except under the condition that the first power switch of the buck circuit and the second power switch of the buck circuit are not turned on; the first power switch of the booster circuit is constantly conducted, and the second power switch of the booster circuit is constantly not conducted;
in a boost conversion mode, the first power switch of the boost circuit is turned on for the second fixed time, the second power switch of the boost circuit is switched in phase opposition to the first power switch of the boost circuit when operating in a continuous conduction mode, and in a discontinuous conduction mode, the second power switch of the boost circuit is switched in phase opposition to the first power switch of the boost circuit except under a condition that neither the first power switch of the boost circuit nor the second power switch of the boost circuit is conductive; the first power switch of the voltage reduction circuit is constantly conducted, and the second power switch of the voltage reduction circuit is constantly not conducted;
the second aspect has the following features:
in a buck conversion mode, the first power switch of the buck circuit is not conducted for the first fixed time, the first power switch of the boost circuit is constantly conducted, and the second power switch of the boost circuit is constantly not conducted;
in a boost conversion mode, the first power switch of the boost circuit is turned on for the second fixed time, the second power switch of the boost circuit is switched in reverse phase with the first power switch of the boost circuit in a continuous conduction mode operation, and the first power switch of the buck circuit is constantly turned on;
the above (iii) has the following features:
in a buck conversion mode, the first power switch of the buck circuit is not turned on for the first fixed time, the second power switch of the buck circuit is switched in reverse phase with the first power switch of the buck circuit when operating in a continuous conduction mode, and in a discontinuous conduction mode, the second power switch of the buck circuit is switched in reverse phase with the first power switch of the buck circuit except under the condition that the first power switch of the buck circuit and the second power switch of the buck circuit are not turned on; the first power switch of the booster circuit is constantly conducted;
in the boost conversion mode, the first power switch of the boost circuit is conducted for the second fixed time, the first power switch of the buck circuit is conducted constantly, and the second power switch of the buck circuit is not conducted constantly; and
the above (iv) has the following features:
when in a voltage reduction conversion mode, the first power switch of the voltage reduction circuit is not conducted for the first fixed time, and the first power switch of the voltage boost circuit is constantly conducted;
in the boost conversion mode, the first power switch of the boost circuit is conducted for the second fixed time, and the first power switch of the buck circuit is conducted constantly;
wherein the peak-to-valley value of the first inductor current related signal is a difference between the peak value of the first inductor current related signal and the valley value of the first inductor current related signal, and the peak-to-valley value of the first sawtooth wave signal is a difference between the peak value of the first sawtooth wave signal and the valley value of the first sawtooth wave signal.
6. A control circuit for controlling a fixed-time buck-boost switching power circuit, the fixed-time buck-boost switching power circuit comprising a buck circuit and a boost circuit, the buck circuit comprising: an inductor having a first end and a second end; a first power switch of a voltage reduction circuit, one end of which is coupled with the first end of the inductor, and the other end of which is coupled with an input voltage; one end of the power element of the voltage reduction circuit is coupled with the first end of the inductor, and the other end of the power element of the voltage reduction circuit is grounded; the booster circuit includes: the inductor; a first power switch of the boost circuit, one end of which is coupled with the second end of the inductor; and a power element of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is coupled with an output voltage; wherein the control circuit comprises:
an error amplifier for comparing a feedback signal related to the output voltage with a reference voltage to generate an error amplified signal;
a first PWM comparator for comparing a signal related to a first inductor current or a first sawtooth wave signal with the error amplification signal;
a second PWM comparator for comparing a signal related to a second inductor current or a second sawtooth wave signal with the error amplification signal;
a shift signal generator for generating a shift signal by a phase difference between the first inductor current related signal or the first sawtooth wave signal and the second inductor current related signal or the second sawtooth wave signal;
a first fixed time generator for generating a first fixed time according to the output of the first PWM comparator;
a second fixed time generator for generating a second fixed time according to the output of the second PWM comparator;
a first driving circuit, which generates a voltage-reducing switch control signal according to the first fixed time to control the voltage-reducing circuit; and
a second driving circuit, which generates a boost switch control signal according to the second fixed time to control the boost circuit;
the first fixed time is a fixed non-conducting time, so that the first power switch of the voltage reduction circuit is not conducted within the fixed non-conducting time, and the second fixed time is a fixed conducting time, so that the first power switch of the voltage boost circuit is conducted within the fixed conducting time.
7. The control circuit of claim 6, wherein the shift signal is greater than a peak-to-valley value of the first inductor current related signal or greater than a peak-to-valley value of the first sawtooth signal, such that the constant-time buck-boost switching power circuit operates only in a buck conversion mode or a boost conversion mode but does not operate in a buck-boost conversion mode, wherein the peak-to-valley value of the first inductor current related signal is a difference between a peak value of the first inductor current related signal and a valley value of the first inductor current related signal, and the peak-to-valley value of the first sawtooth signal is a difference between a peak value of the first sawtooth signal and a valley value of the first sawtooth signal.
8. A method for controlling a fixed-time buck-boost switching power circuit, the fixed-time buck-boost switching power circuit comprising a buck circuit and a boost circuit, the buck circuit comprising: an inductor having a first end and a second end; a first power switch of a voltage reduction circuit, one end of which is coupled with the first end of the inductor, and the other end of which is coupled with an input voltage; one end of the power element of the voltage reduction circuit is coupled with the first end of the inductor, and the other end of the power element of the voltage reduction circuit is grounded; the booster circuit includes: the inductor; a first power switch of the boost circuit, one end of which is coupled with the second end of the inductor; and a power element of the booster circuit, one end of which is coupled with the second end of the inductor, and the other end of which is coupled with an output voltage; the control method is characterized by comprising the following steps:
generating a first fixed time according to a feedback signal related to the output voltage, a reference voltage, and a signal related to a first inductor current or a first sawtooth wave signal;
generating a second fixed time according to the feedback signal related to the output voltage, the reference voltage, and a signal related to a second inductor current or a second sawtooth wave signal;
the first fixed time controls the voltage reduction circuit, and the second fixed time controls the voltage boosting circuit;
the first fixed time is a fixed non-conducting time, so that the first power switch of the voltage reduction circuit is not conducted within the fixed non-conducting time, and the second fixed time is a fixed conducting time, so that the first power switch of the voltage boost circuit is conducted within the fixed conducting time; wherein the difference between the signal related to the first inductor current or the first sawtooth wave signal and the signal related to the second inductor current or the second sawtooth wave signal is a shift signal.
9. The method of claim 8, wherein the step of generating the first fixed time and the second fixed time comprises:
comparing a feedback signal related to the output voltage with the reference voltage to generate an error amplification signal;
comparing the signal related to the first inductor current or the first sawtooth wave signal with the error amplification signal to generate a first comparison result;
adding the displacement signal to the signal related to the first inductive current or the first sawtooth wave signal to generate a signal related to the second inductive current or the second sawtooth wave signal;
comparing the signal related to the second inductor current or the second sawtooth wave signal with the error amplification signal to generate a second comparison result;
generating the first fixed time according to the first comparison result; and
and generating the second fixed time according to the second comparison result.
10. The method of claim 9, wherein the displacement signal is greater than a peak-to-valley value of the first inductor current related signal or greater than a peak-to-valley value of the first sawtooth wave signal, such that the constant time buck-boost switching power circuit operates only in a buck conversion mode or a boost conversion mode but not in a buck-boost conversion mode, wherein the peak-to-valley value of the first inductor current related signal is a difference between the peak value of the first inductor current related signal and the valley value of the first inductor current related signal, and the peak-to-valley value of the first sawtooth wave signal is a difference between the peak value of the first sawtooth wave signal and the valley value of the first sawtooth wave signal.
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| CN109327137B (en) * | 2017-07-31 | 2020-10-30 | 立锜科技股份有限公司 | Double-fixed-time switching type power circuit, switching circuit and method thereof |
| US10135340B1 (en) * | 2017-09-11 | 2018-11-20 | Linear Technology Holding Llc | Pass through regulation of buck-boost regulator |
| CN111082657A (en) * | 2018-10-18 | 2020-04-28 | 圣邦微电子（北京）股份有限公司 | Buck-boost converter and control method |
| CN110138212A (en) * | 2019-06-01 | 2019-08-16 | 深圳市永航新能源技术有限公司 | Half-bridge driven no dead-time control method, control device and charging equipment |
| WO2020243891A1 (en) * | 2019-06-04 | 2020-12-10 | Abb Schweiz Ag | Apparatus and method for power conversion |
| CN111262434B (en) * | 2020-02-20 | 2022-03-29 | 上海南芯半导体科技股份有限公司 | Buck-boost DC-DC converter and control method |
| CN112019048B (en) * | 2020-08-20 | 2022-03-22 | 成都芯源系统有限公司 | Switching converter, controller and control method thereof |
| US11594969B2 (en) * | 2020-12-30 | 2023-02-28 | Astec International Limited | Non-inverting buck-boost converter |
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