CN115498013B - Preparation method of power chip termination region, structure of termination region and power chip - Google Patents
Preparation method of power chip termination region, structure of termination region and power chip Download PDFInfo
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- CN115498013B CN115498013B CN202210864613.4A CN202210864613A CN115498013B CN 115498013 B CN115498013 B CN 115498013B CN 202210864613 A CN202210864613 A CN 202210864613A CN 115498013 B CN115498013 B CN 115498013B
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- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims description 36
- 150000002500 ions Chemical class 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 17
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000002513 implantation Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- -1 arsenic ions Chemical class 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
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Abstract
A preparation method of a power chip termination region, a termination region structure and a power chip, wherein the preparation method comprises the following steps: providing an N-type substrate; forming a P+ grounding ring on the N-type substrate; forming a field oxide layer correspondingly at the position of the N-type substrate corresponding to the termination region; the termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in the field oxide layer region. The technical scheme has the beneficial effects that through the structural arrangement of the parallel area and the corner area of the termination area, the P+ grounding ring determines the first electric field intensity of the corner, and the electric field intensity can be adjusted by the first P-type ring P+ grounding ring, so that the design can use the minimum curvature, the electric field intensity is increased by avoiding the power line crowding caused by the corner, the width of the field termination area can be effectively reduced, and the total area of the chip is reduced, thereby reducing the cost.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a power chip termination region and a method for manufacturing a power chip.
Background
Insulated Gate Bipolar Transistors (IGBTs) are a new type of power electronics that combine MOS field effects with bipolar transistors. The high-voltage power supply has the advantages of large MOSFET input resistance, easiness in driving and simplicity in control; and has the advantages of reduced on-voltage and large on-state current of the bipolar transistor. When the device is blocked and closed, the device needs to bear certain voltage withstand capacity, and the voltage withstand capacity depends on the electric field distribution in the device at the position where the high electric field peak is accumulated and broken down. The high-voltage power supply has become one of core components in modern power electronic circuits, and is widely applied to the fields of traffic, energy, industry, household appliances and the like. Most of the application scenes of the IGBT are applied to high-power high-current, and a plurality of chips are required to be connected in parallel in many cases, so that the requirement on the consistency of parameters is high.
However, the structure of the whole chip comprises two parts of a cell area and a termination area, the design rule of the cell area of the device is that the cell area of the device is a plane repeatedly formed in two dimensions, but the edge of the cell area loses symmetry, so that the termination area structure is required to dissipate the electric field distribution born by the cut-off voltage of the device, and the device meets the rated voltage-withstanding requirement. Therefore, attention is paid to the distribution of electric fields within cells and at the boundary between termination regions in the device design, and the main termination region structures of the current technology are field plate structure (FIELD PLATE), floating Ring (Floating Ring), junction boundary extension (Junction Termination Extension) and surface electric field lowering structure (ReSurf) based on this consideration, which mainly extend the junction depletion region of the boundary as far as possible to reach the breakdown voltage value of the edge. However, the design method can cope with devices with smaller rated voltage, and the design cost of devices with higher rated voltage is higher, so that the efficiency is further reduced.
Disclosure of Invention
Aiming at the problems of the termination area in the prior art, a preparation method of the power chip termination area for improving the withstand voltage of the termination area in a high-power chip is provided.
Another object of the present invention is to provide a method for manufacturing a power chip for improving withstand voltage of a termination area in a high-power chip.
The specific technical scheme is as follows:
A preparation method of a power chip termination region comprises the following steps:
Providing an N-type substrate;
forming a P+ grounding ring on the N-type substrate;
forming a field oxide layer correspondingly at the position of the N-type substrate corresponding to the termination region;
The termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in the field oxide layer region.
Preferably, the P-type ring is linearly arranged in the silicon surface exposed between the two field oxide layers.
Preferably, a first p+ ground ring between the termination region and the cell region, the first p+ ground ring being at the junction of the corner region and the flat region of the termination region.
Preferably, the method for forming the p+ grounding ring comprises the following steps:
determining a first position of a P+ ground ring domain;
Exposing the first position by using a mask;
Implanting P-type ions at a predetermined dose to the exposed first location.
Preferably, the method for forming the field oxide layer includes:
determining a second location of the field oxide layer;
Exposing the second position by using a second photomask;
etching the exposed second position to form a first groove;
And depositing and forming the field oxide layer in the first groove.
Preferably, the method for forming the P-type ring comprises the following steps:
Placing a third photomask on the top of the N-type substrate, wherein the third photomask is provided with a preset number of through holes corresponding to the positions of the field oxide layers, and preset intervals are arranged among the through holes;
implanting P-type ions with preset doses into the through holes;
forming a P-type ring by adopting a wet oxidation process and burying the P-type ring at a position which is not the field oxide layer;
the oxide layer is exposed through the mask four and a predetermined dose of arsenic ions is implanted.
Preferably, the implantation dose of the P-type ions is as follows: the boun/100 KeV/4.0-8.0E14cm-2.
Preferably, the implantation dose of the P-type ions is as follows: the boron/360 KeV/1.0-4.0E14cm-2.
Also included is a structure of a termination region of a power chip, comprising:
a P+ grounding ring is formed on the N-type substrate;
forming a field oxide layer correspondingly at the position of the N-type substrate corresponding to the termination region;
The termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in the field oxide layer region.
Also included is a power chip wherein the termination region structure of the power chip employs the termination region structure of claim 9.
The technical scheme has the following advantages or beneficial effects:
Through the structural arrangement of the parallel region and the corner region of the termination region, wherein the P+ grounding ring determines the first electric field intensity of the corner, the electric field intensity can be adjusted by the first P-type ring P+ grounding ring, so that the design can use larger curvature, the electric field intensity is increased by avoiding the power line crowding caused by the corner, the width of the field termination region can be effectively reduced, and the total area of the chip is further reduced;
The method can inhibit the breakdown voltage reduction caused by interface charge, mobile ion capacity and the like of the silicon/oxide layer, and needs to be explained that most of the method can reduce the electric field strength by increasing the radian of the bent angle or increase the breakdown voltage value by increasing the distance between the P-type rings in the termination area when the voltage breakdown is completed due to the bent angle, and increase the cost of the chip.
Drawings
Embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The drawings, however, are for illustration and description only and are not intended as a definition of the limits of the invention.
FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating a power chip termination region according to the present invention;
FIG. 2 is a schematic diagram of a parallel region in an embodiment of a method for fabricating a power chip termination region according to the present invention;
FIG. 3 is a schematic diagram illustrating a corner region in an embodiment of a method for fabricating a power chip termination region according to the present invention;
Fig. 4 is a schematic structural diagram of a corner region in an embodiment of a method for manufacturing a power chip termination region according to the present invention;
FIG. 5 is a schematic diagram illustrating a structure of a corner region in an embodiment of a method for fabricating a power chip termination region according to the present invention;
Fig. 6-11 are schematic views of a partially exploded structure of a corresponding process schematic diagram of an embodiment of a method for fabricating a termination region of a power chip according to the present invention;
Fig. 12 is a schematic structural diagram of a termination area B and a cell area a according to an embodiment of a method for manufacturing a termination area of a power chip of the present invention;
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
As shown in fig. 1, an embodiment of a method for preparing a power chip termination region includes the following steps:
Providing an N-type substrate 1; the material of the N-type substrate 1 is an N-type substrate with a lattice direction and a base concentration of 1.0e14 cm < -3 >;
forming a P+ grounding ring on the N-type substrate 1;
Forming a field oxide layer 3 correspondingly at the position of the N-type substrate 1 corresponding to the termination region;
As shown in fig. 2-3, the termination region includes a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first and second P-type ring structures are located in a region other than the field oxide layer 3.
It should be noted that, the parallel area is shown in fig. 2, and the direction shown in fig. 2 is a schematic design drawing of four flat-edge unit flat areas of the chip;
the intermediate STI Region can be accomplished in two ways
1.STIFOX process
2. STI + TEOS Oxide deposited process
The silicon-based surface exposed in the middle may be implanted Linear P TOP Ring (linear P-ring at the top position) or Linear P burrier Ring (buried P-ring), and the buried P-ring is preferable in this embodiment.
The corner region is shown in FIG. 3, the layout design of the corner of the chip is shown in FIG. 4 by correcting the spacing between the P+ first floating field ring and the field plate, or the polysilicon field plate extending from above the P+ grounding ring region reaches the region of the intermediate field oxide layer 3 as shown in FIG. 5.
The power semiconductor device (Power semiconductor device) includes a planar gate/trench gate MOSFET transistor, an Insulated Gate Bipolar Transistor (IGBT), a rectifier, a synchronous rectifier, and the like. These semiconductor device chips (Die) are divided into three parts, an active region, a gate region and a field termination region, by the function of the IGBT chip. The active region and the gate region are also called as cell regions, and are functional regions of the chip, and mainly affect voltage and current related parameters of the chip, such as: turn-on voltage, gate voltage, switching and shorting characteristics, etc. The field termination region in the prior art is a passive region where a terminal structure of a field limiting ring (FIELD LIMITING RINGS, FLRs) and a field plate (FIELD PLATES, FPs) are combined to provide connection and channel cut-off, so that an electric field around an active region is mainly minimized and is not used for conducting current, and the voltage endurance capability of the device can be improved by increasing the number and the width of the field limiting rings and the length of the field plate. In addition, in order to improve the high temperature performance of the chip, semi-insulating materials such as: the oxygen-doped semi-insulating polysilicon (semi-insulating polycrystalline silicon, SIPOS) improves the high-temperature pressure resistance of the chip, effectively blocks the pollution of ions to the device, and improves the reliability of the device.
In the prior art, the field termination region designed to have higher breakdown voltage capability than the active region is mostly determined by selecting proper ring width, number and length of the field plate. However, there is a nonlinear relationship between the device voltage endurance capability and the number of rings, the ring width and the field plate length, and as the rated voltage of the device is larger, for example, the voltage of a turbine, a hydro-generator and the voltage of a field termination area required by 3300V or 6500V or more are necessarily increased, so how to design an optimized termination area structure can improve the ion resistance capability is a great technical difficulty.
In order to deal with the problem that the rated voltage of the device is larger and larger, the voltage withstand width of the field termination area is necessarily increased, and the larger the device is, the larger the cost is. The structure arrangement of the parallel region and the corner region of the termination region comprises the arranged P-type ring, and the depletion region of the P region is increased, so that the distance can be shortened, and the N ion layer is further arranged above the P-type ring, so that the reduction of breakdown voltage caused by the interface charge, mobile ion capacity and the like of the silicon/oxide layer can be effectively inhibited by the N ion layer.
It should be noted that, the preparation process of the termination region corresponds to that shown in fig. 6 to 11:
In a preferred embodiment, the P-type ring is arranged linearly in the termination region in the silicon surface exposed in the middle of the two field oxide layers 3.
In a preferred embodiment, as shown in fig. 12, a first p+ ground ring between the termination region B and the cell region a is located at the intersection of the corner region and the flat region of the first termination region, and further, the distance between the two is 1.0-4.0um. The structures of the termination area B and the cell area a are shown in fig. 12.
In this embodiment, the corner region p+ and the flat edge region p+ are high in electric field intensity due to the dense electric field intensity change of the corner power line caused by the curvature radius, and the corner region electric field intensity is optimized by improving and enlarging the corner region p+ to enlarge the curvature radius and reduce the electric field intensity, and matching with the linear P-type ring adjustment. The existing processing mode extends to the corner area directly, namely that the failure point of the ending area is at the junction of the corner area or on the corner area at present.
In a preferred embodiment, a method of forming a p+ ground ring includes: determining a first position of a P+ ground ring domain; exposing the first position by using a photomask; a predetermined dose of P-type ions is implanted into the exposed first location. Preferably, the implantation dose of the P-type ions is as follows: the boun/100 KeV/4.0-8.0E14cm-2.
In a preferred embodiment, the method of forming the field oxide layer 3 comprises: determining a second position of the field oxide layer 3; exposing the second position by using a second photomask; etching the exposed second position to form a first groove;
A field oxide layer 3 is deposited in the first trench. In this embodiment, the first trench may be formed by a LOCOS FOX process.
In a preferred embodiment, a method of forming a P-type ring includes:
Placing a third photomask on the top of the N-type substrate 1; the position of the photomask three corresponding to the non-field oxide layer 3 is provided with a predetermined number of through holes, and a predetermined interval is arranged between the through holes;
p-type ions with preset dosage are implanted into the through holes, and preferably, the implantation dosage of the P-type ions is as follows: the boun/100 KeV/4.0-8.0E14cm-2.
Forming a P-type ring by adopting a wet oxidation process and burying the P-type ring below the field oxide layer 3;
The oxide layer is exposed through the mask four and a predetermined dose of Arsenic ions is implanted, arsenic/2.0e12cm-2/100-200 KeV.
The technical scheme of the invention also comprises an embodiment of the termination area of the power chip, wherein the embodiment comprises the following steps:
a P+ grounding ring is formed on the N-type substrate 1;
Forming a field oxide layer 3 correspondingly at the position of the N-type substrate 1 corresponding to the termination region;
The termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in a region which is not the field oxide layer 3.
The technical scheme of the invention also comprises an embodiment of the power chip, wherein the structure of the termination area of the power chip adopts the structure of the termination area.
The technical scheme of the invention also comprises an embodiment of a preparation method of the power chip, as shown in fig. 6-11, wherein the preparation method comprises the following steps:
Providing an N-type substrate 1;
forming a P+ grounding ring on the N-type substrate 1;
Forming a field oxide layer 3 correspondingly at the position of the N-type substrate 1 corresponding to the termination region;
The termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in a region which is not the field oxide layer 3;
Continuously forming a polysilicon layer on the top of the substrate 1 and extending to the field oxide layer 3;
executing a back surface process, and sequentially forming a stop layer and a P-type layer on one surface of the bottom of the substrate 1, which is opposite to the polycrystalline silicon layer;
and continuing to perform metal layer layout on the polysilicon layer.
In this embodiment, the process for preparing the termination region is described in detail in the process for preparing the termination region, which is not described herein.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included within the scope of the present invention.
Claims (8)
1. A method for fabricating a termination region of a power chip, comprising the steps of:
Providing an N-type substrate;
forming a P+ grounding ring on the N-type substrate;
Forming field oxide layers at intervals corresponding to the positions of the corresponding termination areas of the N-type substrate;
the termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in the N-type substrate and are not in the field oxide layer region;
the second P-type ring structure and the field oxide layer are alternately arranged at intervals;
The first and second P-type rings are linearly arranged in the silicon surface exposed between the two field oxide layers;
The first P+ grounding ring between the termination region and the cell region is arranged at the junction of the corner region and the parallel region of the termination region.
2. The method of claim 1, wherein the method of forming the p+ ground ring comprises:
Determining a first position of the P+ grounding ring region;
Exposing the first position by using a mask;
Implanting P-type ions at a predetermined dose to the exposed first location.
3. The method of manufacturing according to claim 1, wherein the method of forming the field oxide layer comprises:
determining a second location of the field oxide layer;
Exposing the second position by using a second photomask;
etching the exposed second position to form a first groove;
And depositing and forming the field oxide layer in the first groove.
4. The method of manufacturing according to claim 1, wherein the method of forming the P-type ring comprises:
Placing a third photomask on the top of the N-type substrate, wherein the third photomask is provided with a preset number of through holes corresponding to the positions of the field oxide layers, and preset intervals are arranged among the through holes;
implanting P-type ions with preset doses into the through holes;
And forming a P-type ring by adopting a wet oxidation process and burying the P-type ring at a position which is not the field oxide layer.
5. The method of claim 2, wherein the P-type ions are implanted at a dose of: the boun/100 KeV/4.0-8.0E14cm-2.
6. The method of claim 4, wherein the P-type ions are implanted at a dose of: the boron/360 KeV/1.0-4.0E14cm-2.
7. A structure of a termination region of a power chip, wherein a method for manufacturing the structure of the termination region of the power chip is manufactured by using the manufacturing method of any one of claims 1 to 6, and the structure of the termination region of the power chip includes:
a P+ grounding ring is formed on the N-type substrate;
forming a field oxide layer correspondingly at the position of the N-type substrate corresponding to the termination region;
The termination region comprises a corner region and a parallel region, the parallel region is provided with a first P-type ring structure, the corner region is provided with a second P-type ring structure, and the first P-type ring structure and the second P-type ring structure are positioned in the field oxide layer region.
8. A power chip, wherein the termination region structure of the power chip adopts the termination region structure of claim 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210864613.4A CN115498013B (en) | 2022-07-21 | 2022-07-21 | Preparation method of power chip termination region, structure of termination region and power chip |
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| CN202210864613.4A CN115498013B (en) | 2022-07-21 | 2022-07-21 | Preparation method of power chip termination region, structure of termination region and power chip |
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| CN115498013A CN115498013A (en) | 2022-12-20 |
| CN115498013B true CN115498013B (en) | 2024-04-26 |
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| JP2008016562A (en) * | 2006-07-04 | 2008-01-24 | Rohm Co Ltd | Semiconductor device |
| CN104103691A (en) * | 2013-04-15 | 2014-10-15 | 英飞凌科技奥地利有限公司 | Semiconductor device with compensation regions |
| CN105047712A (en) * | 2014-04-17 | 2015-11-11 | 富士电机株式会社 | Vertical semiconductor device and method of manufacturing the vertical semiconductor device |
| CN105185830A (en) * | 2015-08-28 | 2015-12-23 | 深圳深爱半导体股份有限公司 | Power transistor and junction termination structure thereof |
| CN111344866A (en) * | 2017-09-14 | 2020-06-26 | 株式会社电装 | Semiconductor device and method for manufacturing the same |
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| US7737469B2 (en) * | 2006-05-16 | 2010-06-15 | Kabushiki Kaisha Toshiba | Semiconductor device having superjunction structure formed of p-type and n-type pillar regions |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2008016562A (en) * | 2006-07-04 | 2008-01-24 | Rohm Co Ltd | Semiconductor device |
| CN104103691A (en) * | 2013-04-15 | 2014-10-15 | 英飞凌科技奥地利有限公司 | Semiconductor device with compensation regions |
| CN105047712A (en) * | 2014-04-17 | 2015-11-11 | 富士电机株式会社 | Vertical semiconductor device and method of manufacturing the vertical semiconductor device |
| CN105185830A (en) * | 2015-08-28 | 2015-12-23 | 深圳深爱半导体股份有限公司 | Power transistor and junction termination structure thereof |
| CN111344866A (en) * | 2017-09-14 | 2020-06-26 | 株式会社电装 | Semiconductor device and method for manufacturing the same |
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