CN115483820B - Adjustable dead time circuit - Google Patents
Adjustable dead time circuit Download PDFInfo
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- CN115483820B CN115483820B CN202211142650.0A CN202211142650A CN115483820B CN 115483820 B CN115483820 B CN 115483820B CN 202211142650 A CN202211142650 A CN 202211142650A CN 115483820 B CN115483820 B CN 115483820B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Abstract
The application discloses an adjustable dead time circuit, which is characterized by comprising the following components: the delay adjusting circuit, the delay unit circuit and the short-pass protection circuit module; the delay adjusting circuit, the delay unit circuit and the short-pass protection circuit are sequentially connected. The delay adjustment circuit is used for adjusting dead time based on output current; the delay unit circuit is used for adding a section of delay on the rising edge of the PWM signal; the short-pass protection circuit module is used for eliminating the part with high and low edges and high level. The circuit is easy to realize, the system cost is low, the dead time can be adjusted in time according to the actual application requirement, and the dead time adjustment range is wide, so that the dead time meets the system requirement.
Description
Technical Field
The application relates to the field of dead time circuits, in particular to an adjustable dead time circuit.
Background
In the gate driving circuit, the power switch is not an ideal switching device, and a certain delay is required for turning on and off. When the complementary PWM signal is adopted to control the power switch, a delay time is added to the rising edge of the PWM signal in order to avoid the through of the bridge arm, and the added delay time is called dead time. If the added dead time is too small, the bridge arm has a risk of direct connection. If the bridge arm is directly connected, additional power consumption is caused, and even the bridge arm is damaged. If the added dead time is too large, the inductor freewheels through the body diode of the power switch in the dead time, which can result in reduced system efficiency. In the traditional scheme, a fixed dead time circuit is adopted, so that the dead time is set to be larger, the bridge arm is ensured not to be directly connected under various working conditions, and the efficiency of the system is reduced.
Disclosure of Invention
The application provides an adjustable dead time circuit, which is characterized in that current is linearly regulated through an off-chip resistor, and then the current is utilized to charge a capacitor to generate dead time, namely the dead time is linearly regulated through the off-chip resistor.
In order to achieve the above object, the present application provides the following solutions:
an adjustable dead time circuit comprising: the delay adjusting circuit, the delay unit circuit and the short-pass protection circuit module;
the delay adjusting circuit, the delay unit circuit and the short-pass protection circuit are sequentially connected;
the delay adjustment circuit is used for adjusting dead time based on output current;
the delay unit circuit is used for adding a section of delay on the rising edge of the PWM signal;
the short-pass protection circuit module is used for eliminating the part with high and low edges and high level.
Preferably, the delay adjustment circuit includes: the circuit comprises a plurality of PMOS transistors, a plurality of NMOS transistors, a first constant current source, a zero setting resistor, a fixed value resistor, an off-chip resistor and a first capacitor.
Preferably, the delay adjustment circuit is configured to obtain the constant output current based on the first current member, and then linearly adjust a current value of the output current through the off-chip resistor, and mirror the output current to the delay unit circuit to generate dead time.
Preferably, the delay unit circuit includes: the device comprises a plurality of PMOS transistors, a plurality of NMOS transistors, a second constant current source, a third constant current source and a second capacitor.
Preferably, the delay unit circuit charges the second capacitor through the output current, compares the voltage on the second capacitor with a reference voltage, and outputs a high level when the voltage on the second capacitor reaches the reference voltage value, i.e. adds a delay period on the rising edge of the PWM signal.
Preferably, the short-pass protection circuit module includes: a high-side short-pass protection circuit and a low-side short-pass protection circuit.
Preferably, the high-side short-pass protection circuit includes: a first inverter and a first nor gate; the low-side short-pass protection circuit comprises: a second inverter and a second nor gate.
Preferably, the high-side short-pass protection circuit is configured to receive the PWM signal input on the low side and the signal with the dead time added after the high side is processed by the first inverter, and perform nor operation by using the first nor gate, so as to eliminate a portion of the high-side signal and the low-side signal that is simultaneously "1", that is, eliminate a portion of the high-side signal and the low-side signal that is simultaneously high level.
Preferably, the bottom side short-pass protection circuit is configured to receive the PWM signal input by the high side and the signal with the dead time added after the low side is processed by the second inverter, and perform nor operation by using the second nor gate, so as to eliminate a portion of the high side signal and the low side signal that is simultaneously "1", that is, eliminate a portion of the high side and the low side that is simultaneously high level.
The beneficial effects of the application are as follows:
(1) According to the application, the dead time can be adjusted in time according to the actual application requirements, so that the dead time meets the system requirements better;
(2) The dead time adjustment range is wide;
(3) The application is easy to realize and the system cost is low.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the embodiments are briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an adjustable dead time circuit connection according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a delay adjustment circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a circuit connection of a delay cell according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a high-side short-pass protection circuit connection in an embodiment of the present application;
fig. 5 is a schematic diagram of connection of a bottom-side short-pass protection circuit in an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
In this embodiment, an adjustable dead time circuit includes: the delay adjusting circuit, the delay unit circuit and the short-pass protection circuit module; the delay adjusting circuit, the delay unit circuit and the short-pass protection circuit are sequentially connected, and the connection relation is shown in figure 1. The delay adjusting circuit is used for adjusting dead time based on the output current; the delay unit circuit is used for adding a section of delay on the rising edge of the PWM signal; the short-pass protection circuit module is used for eliminating the part with high and low sides and high level.
In this embodiment, the connection relationship of the delay adjustment circuit is as shown in fig. 2, and includes: 10 PMOS transistors, 5 NMOS transistors, a first constant current source and a zeroing resistor R Z Fixed resistor R S Off-chip resistor R DEAD And a first capacitor C C 。
As shown in fig. 2, the delay adjustment circuit obtains a stable reference current based on a current-voltage negative feedback structure. The delay adjusting circuit obtains a constant output current, the current value of the output current can be linearly adjusted through an off-chip resistor, and the output current is mirrored into the delay unit circuit by using a current mirror to generate dead time, so that the function of indirectly adjusting the dead time by the off-chip resistor is realized.
In the embodiment, the delay adjusting circuit uses a negative feedback structure comprising 4 NMOS transistors, 6 PMOS transistors, a first constant current source, and a zeroing resistor R Z And a first capacitor C C The composed error amplifier therefore needs to take loop stability into account by the firstCapacitor C C Separating the primary pole from the secondary pole and then using the zeroing resistor R Z The zero point of the right half plane is pushed to infinity, thereby improving loop stability. The output of the delay adjusting circuit is output current I DEAD By adjusting the output current I DEAD The dead time may be adjusted: v can be obtained according to the 'virtual short' characteristic of the input end of the error amplifier FB ＝V REF Through an off-chip resistor R DEAD Can be used for setting the voltage V FB Converted into current as long as the current across the resistor and the output current I DEAD The proportion relation is certain, and the resistance R outside the regulating piece is regulated DEAD The output current I can be linearly adjusted DEAD I.e. linearly adjusting the dead time.
The circuit connection of the delay unit is shown in fig. 3, and the delay unit consists of an RC delay circuit and a comparator module, and comprises: 6 PMOS transistors, 7 NMOS transistors, a second constant current source, a third constant current source and a second capacitor C 1 。
The delay unit circuit is used for charging the capacitor through current, then the comparator is used for comparing the voltage on the capacitor with the reference voltage, and when the voltage on the capacitor reaches the reference voltage value, the comparator outputs high level, namely a period of delay is added on the rising edge of the PWM signal.
In the present embodiment, the current I outputted by the second constant current source DEAD ' is by I in delay adjustment circuit DEAD Obtained by mirroring the current mirror, when the rising edge of the input PWM signal comes, MN6 is turned off, current I DEAD ' pair of second capacitors C 1 Charging a second capacitor C 1 The upper plate voltage rises from 0, when the second capacitor C 1 The upper plate voltage rises to meet V C1 ＝V REF Output V at the time OUT To a high level; when the input PWM signal changes from high level to low level, MN6 is turned on, and a second capacitor C 1 Through the discharge of the MN6 tube, the second capacitor C is used as a switching tube with smaller on-resistance 1 The upper plate voltage drops rapidly. When the second capacitor C 1 The upper plate voltage drops to meet V C1 ＝V REF Output V at the time OUT To a low level.
The short-pass protection circuit is added at the rear part of the delay unit and is used for eliminating the part with high and low sides and high level at the same time, so that bridge arm straight-through caused by disorder of logic signals is avoided. In this embodiment, the short-pass protection circuit is composed of a high-side short-pass protection circuit and a bottom-side short-pass protection circuit.
As shown in fig. 4, the high-side short-pass protection circuit is implemented by using an inverter and a nor gate, and performs nor operation on the low-side input PWM signal and the inverted signal with the dead time added to the high side, so that the part of the high-side signal and the low-side signal, which is simultaneously "1", is eliminated, and the upper bridge arm power switch is ensured not to be turned on due to phase disorder of the input signal.
As shown in fig. 5, the low-side short-pass protection circuit is implemented by an inverter and a nor gate, and performs nor operation on the high-side input PWM signal and the inverted signal with the dead time added to the low side, so as to eliminate the part of the high-side signal and the low-side signal which is simultaneously "1", and ensure that the power switch of the lower bridge arm is not turned on due to the phase disorder of the input signal.
The above embodiments are merely illustrative of the preferred embodiments of the present application, and the scope of the present application is not limited thereto, but various modifications and improvements made by those skilled in the art to which the present application pertains are made without departing from the spirit of the present application, and all modifications and improvements fall within the scope of the present application as defined in the appended claims.
Claims (6)
1. An adjustable dead time circuit, comprising: the delay adjusting circuit, the delay unit circuit and the short-pass protection circuit module;
the delay adjusting circuit, the delay unit circuit and the short-pass protection circuit are sequentially connected;
the delay adjustment circuit is used for adjusting dead time based on output current;
the delay unit circuit is used for adding a section of delay on the rising edge of the PWM signal;
the short-pass protection circuit module is used for eliminating the part with high and low edges and high level at the same time;
the delay adjustment circuit includes: 10 PMOS transistors, 5 NMOS transistors, a first constant current source, a zeroing resistor, a fixed value resistor, an off-chip resistor and a first capacitor;
wherein one end of the first constant current source is connected with the grid electrode of the transistor MP1, the drain electrode of the transistor MP1 and the grid electrode of the transistor MP2, and the other end of the first constant current source is connected with the source electrode of the transistor MN1, the source electrode of the transistor MN2, the source electrode of the transistor MN3, the source electrode of the transistor MN4 and the fixed resistor R S One end of (d) off-chip resistance R DEAD Is commonly grounded; the source of transistor MP1 and the source of transistor MP2, the source of transistor MP5, the source of transistor MP6, the source of transistor MP7, the source of transistor MP8 are commonly connected to a power supply V DD The method comprises the steps of carrying out a first treatment on the surface of the The drain of the transistor MP2 is connected with the source of the transistor MP3 and the source of the transistor MP 4; the gate of the transistor MP3 is connected to the reference voltage V REF The drain of the transistor MP3 is connected with the drain of the transistor MN1, the gate of the transistor MN1 and the gate of the transistor MN 4; gate of transistor MP4 and zero resistor R Z One end of (d) off-chip resistance R DEAD The other end of the transistor MP10 is commonly connected to V FB The drain of the transistor MP4 is connected with the gate of the transistor MN2, the drain of the transistor MN2 and the gate of the transistor MN 3; the drain of the transistor MN3 is connected to the drain of the transistor PM5, the gate of the transistor PM5, and the gate of the transistor PM 6; drain of the transistor PM6 and a first capacitance C C Is connected to the drain of the transistor MN4 and the gate of the transistor MN 5; first capacitor C C And a zero-setting resistor R Z Is connected with the other end of the connecting rod; source and constant value resistor R of transistor MN5 S The drain is connected with the drain of the transistor MP9, the grid of the transistor MP9 and the grid of the transistor MP 10; the source of the transistor MP9 is connected with the drain of the transistor MP7, the grid of the transistor MP7 and the grid of the transistor MP 8; the drain of transistor MP8 is connected to the source of transistor MP 10; the delay adjusting circuit obtains constant output current based on the first constant current source, and then can linearly adjust the current value of the output current through the off-chip resistor, and the output current is mirrored in the delay unit circuit to generate dead time;
the delay adjusting circuit comprises a negative feedback structure, and comprises an error amplifier consisting of a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP4, a transistor MP5, a transistor MP6, a first constant current source, a zero setting resistor and a first capacitor, wherein a main pole point and a secondary main pole point are separated through the first capacitor, and then a zero point of a right half plane is pushed to infinity by using the zero setting resistor, so that loop stability is improved, the output of the delay adjusting circuit is the output current, and dead time is adjusted by adjusting the output current.
2. The adjustable dead time circuit of claim 1 wherein the delay cell circuit comprises: 6 PMOS transistors, 7 NMOS transistors, a second constant current source, a third constant current source and a second capacitor;
wherein the input of the inverter is connected to V IN The output is connected to the gate of transistor MN 6; drain of transistor MN6 and one end of the second constant current source, second capacitor C 1 A gate of the transistor MP15 is connected to the source of the transistor MN6 and the second capacitor C 1 The other end of the transistor MN7, one end of the third constant current source, the source of the transistor MN8, the source of the transistor MN9, the source of the transistor MN10, the source of the transistor MN11, and the source of the transistor MN12 are commonly connected to the ground; the other end of the second constant current source is connected with the source stage of the transistor MP11, the source stage of the transistor MP12, the source stage of the transistor MP13 and the source stage of the transistor MP 16; the drain of the transistor MP11 is connected with the gate of the transistor MP11, the gate of the transistor MP16 and the source of the transistor MN 7; the gate of the transistor MN7 is connected with the gate of the transistor MN8, the gate of the transistor MN9, the drain of the transistor MN8, the drain of the transistor MP14 and the drain of the transistor MN 10; the grid electrode of the transistor MP12 is connected with the drain electrode of the transistor MP12, the grid electrode of the transistor MP13 and the other end of the third constant current source; the drain of the transistor MP13 is connected with the source of the transistor MP14 and the source of the transistor MP 15; the gate of the transistor MP14 is connected to the reference voltage V REF The method comprises the steps of carrying out a first treatment on the surface of the Drain of transistor MP15 and drain of transistor MN9, and transistorThe gate of the transistor MN10, the gate of the transistor MN11, and the gate of the transistor MN12 are connected; the drain of transistor MN12 and the drain of transistor MP16 are commonly connected to output V OUT The method comprises the steps of carrying out a first treatment on the surface of the The delay unit circuit charges the second capacitor through the output current, compares the voltage on the second capacitor with the reference voltage, and outputs a high level when the voltage on the second capacitor reaches the reference voltage value, namely a section of delay is added on the rising edge of the PWM signal;
the current IDEAD 'output by the second constant current source is obtained by mirroring the current in the delay adjustment circuit through a current mirror, when the rising edge of the input PWM signal arrives, the transistor MN6 is turned off, the current IDEAD' charges the second capacitor, the upper plate voltage of the second capacitor rises from 0, and when the upper plate voltage of the second capacitor rises to meet V C1 ＝V REF Output V at the time OUT To a high level; when the input PWM signal changes from high level to low level, the transistor MN6 is turned on, the second capacitor discharges through the transistor MN6, and the voltage of the upper plate of the second capacitor drops rapidly due to the smaller on-resistance of the transistor MN6 as a switching tube, when the voltage of the upper plate of the second capacitor drops to meet V C1 ＝V REF Output V at the time OUT To a low level.
3. The adjustable dead time circuit of claim 1 wherein the short-pass protection circuit module comprises: a high-side short-pass protection circuit and a low-side short-pass protection circuit.
4. The adjustable dead time circuit of claim 3 wherein the high-side short-pass protection circuit comprises: a first inverter and a first nor gate; the low-side short-pass protection circuit comprises: a second inverter and a second nor gate.
5. The adjustable dead time circuit of claim 4 wherein the high-side short-pass protection circuit receives the PWM signal input on the low side and the signal with the dead time added after the high side is processed by the first inverter, and performs a nor operation by the first nor gate, so as to eliminate the portion of the high-low side signal that is simultaneously "1", i.e., eliminate the portion of the high-low side signal that is simultaneously high.
6. The adjustable dead time circuit of claim 4 wherein the low-side short-pass protection circuit receives the PWM signal input on the high side and the signal with the dead time added after the low side is processed by the second inverter, and performs a nor operation by the second nor gate, so as to eliminate the portion of the high-low side signal that is simultaneously "1", i.e., eliminate the portion of the high-low side signal that is simultaneously high.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211142650.0A CN115483820B (en) | 2022-09-20 | 2022-09-20 | Adjustable dead time circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211142650.0A CN115483820B (en) | 2022-09-20 | 2022-09-20 | Adjustable dead time circuit |
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| CN115483820A CN115483820A (en) | 2022-12-16 |
| CN115483820B true CN115483820B (en) | 2023-09-12 |
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| CN114567157A (en) * | 2021-12-14 | 2022-05-31 | 深圳青铜剑技术有限公司 | Dead time control circuit integrated in dual-channel gate drive chip |
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| KR101713993B1 (en) * | 2010-09-28 | 2017-03-09 | 페어차일드코리아반도체 주식회사 | Driver and high voltage drive circuit including the same |
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| CN105024529A (en) * | 2015-07-28 | 2015-11-04 | 周海波 | Intelligent power module adaptive dead-time generation circuit and application method |
| CN108242886A (en) * | 2018-03-12 | 2018-07-03 | 无锡安趋电子有限公司 | A kind of anti-straight-through protection adaptive dead zone circuit and the driving circuit comprising the circuit |
| CN113839651A (en) * | 2021-10-21 | 2021-12-24 | 上海先之路微电子科技有限公司 | Delay time linear controllable circuit, chip and electronic equipment |
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