CN113839651A - Delay time linear controllable circuit, chip and electronic equipment - Google Patents

Delay time linear controllable circuit, chip and electronic equipment Download PDF

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Publication number
CN113839651A
CN113839651A CN202111228684.7A CN202111228684A CN113839651A CN 113839651 A CN113839651 A CN 113839651A CN 202111228684 A CN202111228684 A CN 202111228684A CN 113839651 A CN113839651 A CN 113839651A
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delay
current
capacitor
voltage
delay time
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王伟
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Shanghai Weimao Electronic Technology Co ltd
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Shanghai Xianzhilu Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks

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  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

The application discloses a delay time linear controllable circuit, a chip and an electronic device, wherein the delay time circuit comprises a reference current generating module, a current limiting module and a control module, wherein the reference current generating module is used for generating a reference current which is inversely proportional to the resistance value of a current limiting resistor; the current source module is connected with the output end of the reference current generation module and used for carrying out integral control on the reference current under the control of a clock control signal with a specific duty ratio and outputting pulse type charging current with the duty ratio changing along with the duty ratio of the clock control signal; the time delay module comprises a capacitor and a time delay unit, wherein the first end of the capacitor is grounded, the second end of the capacitor is connected to the output end of the charging current of the current source module, the time delay unit is connected to the second end of the capacitor and used for outputting a time delay signal after the voltage of the capacitor reaches the reference voltage according to the voltage change of the capacitor, and the charging time when the voltage of the capacitor reaches the reference voltage at a single time corresponds to the single time delay time. The delay time of the circuit is adjustable linearly, and the adjustable range and the accuracy are higher.

Description

Delay time linear controllable circuit, chip and electronic equipment
Technical Field
The application relates to the technical field of integrated circuits, in particular to a delay time linear controllable circuit, a chip and electronic equipment.
Background
In the analog quantity detection and protection circuit, the detection result is often required to be filtered and delayed to increase the anti-interference capability of the detection and protection circuit, so that the delay time control technology has wide application in integrated circuit design and application.
For a fixed delay time requirement, it can be realized by an RC filter circuit inside the chip or a counting circuit using an internal clock inside the chip. However, for some specific applications, the delay time needs to be adjusted appropriately according to the actual application scenario. In a conventional common method for adjusting delay time, a capacitor inside or outside a chip is charged and discharged through an internal current source, and the charging time is adjusted by adjusting a capacitance value, so that the delay time is adjusted.
For the method using the internal capacitor of the chip, the capacitance of the on-chip capacitor is limited by the process and is not easy to be made, so the method is obviously limited by the capacitance of the on-chip capacitor and cannot realize the setting of larger delay time.
For the method using the chip peripheral capacitor, the off-chip capacitor is usually a Surface Mount Technology (SMT) capacitor, the capacitance value is relatively discrete, and the selectable range is limited, so the adjustable delay time also has the limitations of relatively discrete, limited adjustable range, and the like; and the off-chip capacitor usually uses a low-cost ceramic capacitor, the capacitor is influenced by manufacturing process, materials, direct-current bias voltage, temperature and the like, the deviation of capacitance values is large, the precision of delay time is seriously influenced, and the whole system application is easily influenced by the fluctuation of the price of the off-chip capacitor, so that the system cost is influenced.
Therefore, the adjustable range and accuracy of the delay time adjustment in the related art are limited.
Disclosure of Invention
As described in the background art, the delay control circuit of the related art has a limited range and accuracy of delay time adjustment.
In order to solve the above problem, the present invention provides a new delay time linear controllable circuit, comprising: the reference current generating module is used for generating a reference current inversely proportional to the resistance value of the current-limiting resistor; the current source module is connected with the output end of the reference current generation module and used for carrying out integral control on the reference current under the control of a clock control signal with a specific duty ratio and outputting pulse type charging current with the duty ratio changing along with the duty ratio of the clock control signal; the time delay module comprises a capacitor and a time delay unit, wherein the first end of the capacitor is grounded, the second end of the capacitor is connected to the output end of the charging current of the current source module, the time delay unit is connected to the second end of the capacitor and used for outputting a time delay signal after the voltage of the capacitor reaches the reference voltage according to the voltage change of the capacitor, and the charging time when the voltage of the capacitor reaches the reference voltage at a single time corresponds to the delay time of the time delay signal output at a single time.
Optionally, the delay unit includes a comparator, one input end of the comparator is connected to the second end of the capacitor, the other input end of the comparator is used for being connected to the reference voltage, and the comparator is used for comparing the voltage of the capacitor with the reference voltage and outputting a comparison result as a delay signal of a single cycle.
Optionally, the method further includes: the output end of the delay unit is further connected to the current source module, and when the delay unit outputs the delay signal of a single period, the delay signal is further used for controlling the current source module to discharge the capacitor and reset the voltage of the capacitor so as to enter the next charging period.
Optionally, the reference current generating module includes: the voltage-to-current unit is provided with a current limiting resistor which is an off-chip variable resistor; the voltage-to-current unit is connected with the current-limiting resistor and used for applying reference voltage on the current-limiting resistor so that the reference current generation module generates reference current inversely proportional to the resistance value of the current-limiting resistor and outputs the reference current to the current source module; wherein the current limiting resistor is an off-chip variable resistor.
Optionally, the reference current generating module further includes an open/short detection unit for detecting an electrical connection state of a connection end between the off-chip variable resistor and the voltage-to-current conversion unit. Optionally, the open-short detection unit is configured to detect the voltage of the connection terminal, and compare the voltage with a first threshold and a second threshold to determine an open circuit or a short circuit state of the connection terminal, where the first threshold is a connection terminal threshold voltage corresponding to the open circuit state, and the second threshold is a connection short threshold voltage corresponding to the short circuit state.
Optionally, the delay circuit further comprises a delay control logic module, connected to the output end of the delay module, and configured to adjust the delay time of the delay signal.
Optionally, the delay control logic module includes a counter, and the counter is configured to count the received delay signal, and output an extended delay signal when the count value reaches a threshold N, where the extended delay time of the extended delay signal is N times of a single delay time, and N is an integer greater than or equal to 1.
The present application further provides a chip, comprising: a delay time linearly controllable circuit as claimed in any one of the preceding claims.
The present application further provides an electronic device, comprising: a delay time linearly controllable circuit as claimed in any one of the preceding claims.
According to the linear controllable delay time circuit, the reference current generating module generates the charging current inversely proportional to the resistance value of the current limiting resistor, the charging current is subjected to integral control, the rectangular wave current with the adjustable duty ratio is formed, and then the capacitor in the delay module is charged, so that the required delay time is generated. The delay time can change along with the change of the current-limiting resistance value and the duty ratio, and the adjustable range, the accuracy and the linearity of the resistance adjustment are higher, so that the linear adjustment of a wider delay time range can be realized, and the delay time has good delay accuracy, adjustment linearity and power consumption.
Furthermore, the current-limiting resistor can be an off-chip resistor, the adjustable range is larger, the chip area is not occupied, the delay time is not required to be adjusted through the size of the capacitor, the area of the capacitor in the chip can be reduced, the chip area is saved, and the delay requirement of most system applications is met.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a delay time linear controllable circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a delay time linear controllable circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a delay time linear controllable circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a reference current generating module of a delay time linear controllable circuit according to an embodiment of the present application;
FIGS. 5a and 5b are schematic diagrams of signals of a delay time linear controllable circuit according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a delay time linear controllable circuit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
The invention is more clearly and completely described by the following embodiments and the accompanying drawings.
Please refer to fig. 1, which is a schematic structural diagram of a delay time linear controllable circuit according to an embodiment of the present application.
The delay time linear controllable circuit in this embodiment includes: a reference current generating module 110, a current source module 120 and a delay module 130.
The reference current generating module 110 is used for generating a reference current I inversely proportional to the resistance of a current-limiting resistorREF. A reference current I can be formed by applying a reference voltage across a current limiting resistor RREF。
A current source module 120 connected to the output terminal of the reference current generating module 110 and havingUnder the control of a clock control signal clk _ out with a specific duty ratio, the reference current I is controlledREFIntegral control is carried out, and rectangular wave charging current I with duty ratio changing along with the duty ratio of a clock control signal clk _ out is outputREF_o。
Specifically, the reference current IREFIs periodically modulated by the current source module 120 to output a charging current IREF_OCharging current IREF_OIs a rectangular wave current with the duty ratio of a clock control signal clk _ out changing, and the peak current is IREF. In some embodiments, the charging current IREF_OIs the same as the duty cycle of the clock control signal clk _ out. In other embodiments, the charging current IREF_OThe duty ratio of the clock control signal clk _ out and the duty ratio of the clock control signal clk _ out may have other linear proportional relationships, and may be determined by the modulated duty ratio of the current source module 120 and may be set reasonably according to actual needs.
In some embodiments, the current source module 120 may be implemented by a switch control circuit, which periodically switches on the reference current IREFAnd a charging current IREF_OPath between output terminals, reference current IREFAnd modulating the current into rectangular wave current output. In other embodiments, the current source module 120 may also adopt other circuit structures, and those skilled in the art can reasonably select the circuit structure according to actual situations to implement the reference current IREFModulation of (3).
The delay module 130 includes a capacitor int _ C and a delay unit 131. Preferably, the capacitor int _ C is an on-chip capacitor, and has a high integration level.
The first terminal of the capacitor int _ C is grounded, and the second terminal is connected to the charging current I of the current source module 120REF_OThe delay unit 131 is connected to the second end of the capacitor int _ C, and is configured to output the delay signal Vo according to a change of the voltage Vc of the capacitor int _ C, where a single charging time of the capacitor int _ C corresponds to a single delay time.
The current source module 120 outputs a charging current IREF_OCharging the capacitance int _ C due to the charging current IREF_OIs a periodic rectangular wave current, so the capacitance int _ C is periodically conductedCharging in the presence of a charging current IREF_OWhen the voltage is output, the voltage of the capacitor int _ C (i.e., the positive plate voltage) rises; in the absence of a charging current IREF_OAt the time of output, the voltage of the positive plate of the capacitor int _ C remains unchanged.
The delay unit 131 is configured to output a delay signal according to a voltage change at the second end (positive plate) of the capacitor int _ C. Preferably, the delay unit 131 is used for connecting the voltage of the capacitor int _ C with a reference voltage VREFComparing, when the capacitor int _ C is charged to a capacitor voltage Vc ≧ VREFThe delay unit 131 outputs a delay signal. Specifically, when the delay unit 131 is in the capacitor voltage Vc < VREFWhen the output end level is low level, when the capacitor voltage Vc is more than or equal to VREFThe delay unit 131 outputs the delay signal Vo as a high level signal; or, the delay unit 131 is in the capacitor voltage Vc < VREFWhen the output end level is high level, when the capacitor voltage Vc is more than or equal to VREFThe delay unit 131 outputs the delay signal Vo as a low level signal. That is, when the capacitor int _ C is charged to the capacitor voltage Vc ≧ VREFIn time, the signal level at the output terminal of the delay unit 131 is inverted.
The capacitor int _ C is charged to the reference voltage VREFThe required charging time, i.e. the charging current IREF_OThe time required from the input to the delay module 130 to the output of the delay signal Vo from the delay module 130 is the single delay time TDDelay time TDEqual to the charging time of the capacitor int _ C, which depends on the charging current IREF_OThe smaller the duty cycle, the longer the charging time, the delay time TDThe longer.
The output end of the delay unit 131 is further connected to the current source module 120, and when the delay unit 131 outputs the delay signal Vo, the delay signal Vo is further used to control the current source module 120 to discharge the capacitor int _ C, and rapidly release the charge of the positive plate of the capacitor int _ C to start the next round of timing. The current source module 120 may be connected to the second end of the capacitor int _ C through a grounded switch, and the delay signal Vo may control the switch to be turned on, so that the second end of the capacitor int _ C is grounded, and the charge is released.
Fig. 2 is a schematic structural diagram of a delay time linear controllable circuit according to another embodiment of the present invention.
In this embodiment, the delay unit 131 includes a comparator CMP, one input terminal of the comparator CMP is connected to the second terminal of the capacitor int _ C, and the other input terminal is used for being connected to the reference voltage VREFThe comparator CMP is used for comparing the voltage Vc of the capacitor int _ C with the reference voltage VREFComparing and outputting the comparison result as a delay signal Vo, specifically, when VC>VREFThe output signal of the comparator is inverted to generate a delay signal VO。
Preferably, the comparator CMP is a hysteresis comparator, which can improve the stability of the output signal and prevent unnecessary glitch interference.
In this embodiment, the reference current generating module 110 includes: a voltage-to-current unit 111 and a current limiting resistor Ext _ R. In the implementation, the current limiting resistor Ext _ R is an off-chip resistor and is connected to the chip pin PAD, the off-chip resistor has low cost, the resistance value has a large selectable range and is not limited by the size of the chip, the chip cost can be reduced, and the adjustable range and the accuracy of the delay time can be improved. In some embodiments, the current limiting resistor Ext _ R may be a fixed resistor set according to the delay time requirement; in some embodiments, the current limiting resistor Ext _ R may also be a variable resistor, and the resistance value may be adjusted according to the requirement for the delay time.
Under the condition that the requirement of other resistance value adjusting ranges is small, the current limiting resistor Ext _ R can also adopt a chip built-in resistor, can comprise a plurality of parallel resistors, and adjusts the resistance value of the current limiting resistor Ext _ R by controlling the number of the effective resistors connected into the circuit.
The voltage-to-current unit 111 converts the input reference voltage Vref _ in into a reference current I inversely proportional to the resistance of the current limiting resistor Ext _ RREFI.e. by
Figure BDA0003315167340000071
When the scaling factor a is equal to 1,
Figure BDA0003315167340000072
the reference voltage Vref _ in is mainly used for generating a reference current IREFA reference voltage V connectable to the comparator CMPREFAnd (4) independently setting.
In this embodiment, the delay time linear controllable circuit further includes a clock modulation module 140, and the clock modulation module 140 is configured to modulate the input clock signal clk _ in, convert the modulated input clock signal clk _ in into a clock control signal clk _ out with a specific duty ratio D, and output the clock control signal clk _ out. The clock signal clk _ in may be a clock signal used by other functional modules on the chip during operation, or may be generated by an oscillator alone, and the clock signal clk _ in is modulated by the clock modulation module 140 to obtain the clock control signal clk _ out with the required duty ratio D characteristic. The duty cycle D may be adjusted as desired by configuring the clock modulation module 140.
The clock modulation module 140 can be implemented in a digital circuit form, and there are various implementation manners in the prior art, and those skilled in the art can reasonably select the clock modulation module according to needs, which is not described herein.
Fig. 3 is a schematic structural diagram of a delay time linear controllable circuit according to another embodiment of the present invention.
In this embodiment, since the current limiting resistor Ext _ R is an off-chip resistor, the problem of abnormal connection with the PAD of the chip is likely to occur. Therefore, in this embodiment, the reference current generating module 110 further includes an open/short detecting unit 112 for detecting an electrical connection state of the connection terminal between the current limiting resistor Ext _ R and the voltage-to-current converting unit 111.
The open-short detection unit 112 may implement the detection of the open short by detecting the voltage of the connection terminal between the current limiting resistor Ext _ R and the voltage-to-current unit 111. When the voltage of the connection terminal exceeds the preset range, it is determined that the connection state between the current limiting resistor Ext _ R and the voltage-to-current unit 111 is abnormal. For example, when the current limiting resistor Ext _ R is an off-chip resistor, the open/short detection can be realized by detecting the voltage on the PAD of the chip.
Once detecting that the current limiting resistor Ext _ R is shorted to the ground or is open, the open/short detection unit 112 may output a status signal to the control system module of the chip, and simultaneously turn off the delay time linear controllable circuit and related circuits, so as to save the system power consumption of the chip; meanwhile, the reliability of the system is improved, and misjudgment of delay setting caused by abnormal connection outside the chip is prevented.
In some embodiments, the open/short detection unit 112 and the voltage-to-current unit 111 are two independently designed circuit structures; in other embodiments, the open short detection unit 112 may be integrated into the voltage-to-current unit 111, multiplexing at least part of the current structure.
Fig. 4 is a schematic circuit diagram of the reference current generating module 110 according to an embodiment of the invention.
In this embodiment, the voltage-to-current unit 111 of the reference circuit generating module 110 includes an operational amplifier opa, a transistor NM0, and a current mirror composed of a transistor PM1 and a transistor PM 2.
Specifically, an input end of the operational amplifier opa is used for inputting a voltage Vref _ in, an output end of the operational amplifier opa is connected to a gate of the transistor NM0, a circuit path where the transistor PM1 is located in a current mirror formed by the transistor PM1 and the transistor PM2 is connected to a current input end of the transistor NM0, and a current output end of the transistor NM0 is connected to the current limiting resistor Ext _ R through a chip pin PAD. The other input terminal of the operational amplifier opa is connected to the current output terminal of the transistor NM0, forming a negative feedback, so that the voltage V at the chip pin PAD isPAD＝Vref_inThe current flowing through the current limiting resistor Ext _ R is of the magnitude
Figure BDA0003315167340000081
And is mirrored to the transistor PM2 through the transistor PM1 to output as a reference current IREFAnd thus, the method can obtain the product,
Figure BDA0003315167340000082
a is the proportionality coefficient of the current mirror.
In this embodiment, the transistor NM0 is an NMOS transistor, the current input terminal is a drain, and the current output terminal is a source; the transistor PM1 and the transistor PM2 are both PMOS transistors, with the source connected to the power supply VDD and the drain as the current output terminal.
In this embodiment, the open-short detection unit 112 includes a comparator comp1 and a comparator comp2, negative inputs of the comparator comp1 and the comparator comp2 are both connected to the chip pin PAD, a negative input of the comparator comp1 is connected to the first threshold Vref _ op, and a positive input of the comparator comp2 is connected to the second threshold Vref _ st. Terminal voltage V at chip pin PADPAD>Vref _ op, the comparator comp1 outputs the open circuit detection signal V _ open to high level, and determines that the PAD terminal of the chip pin is in open circuit state, for example, disconnected from Ext _ R, or PAD and Ext _ R are normally connected, but the Ext _ R ground terminal is floating, etc.; terminal voltage V at chip pin PADPAD< Vref _ st, the comparator comp2 outputs the short detection signal V _ st as high level, and determines that the PAD is in a ground short state, e.g., the PAD terminal is short-circuited.
When the open/short circuit signal V _ open/V _ st is at a high level, other modules of the circuit can be controlled to stand by, signal delay control is not performed any more, and the power consumption of the chip is reduced.
The above is only one specific circuit configuration example of the reference current generating module 110. In other embodiments, a person skilled in the art may also use other circuits to implement the specific functions of the reference current generating module 110, which is not limited herein.
In one implementation, the duty cycle of the clock control signal clk _ out is D, and the current source module 120 is coupled to the reference current IREFAfter the modulation of current integral control, the charging current I with the duty ratio D is outputREF_OAverage current I of current source module 120REF_AVG＝IREFD, it can be seen that as the duty cycle D decreases, the average current IREF_AVGWill also be linearly scaled down.
At the beginning of the timing, the charging current IREF_OCharging the capacitor int _ C according to the set duty ratio D, thereby generating a voltage V on the capacitor int _ CC(ii) a Voltage value V accumulated per charging cycleC_PeriodComprises the following steps: vC_Period＝IREF*D/int_C＝IREF_AVGInt _ C. Based on this, the capacitor voltage V can be easily obtained according to the number of charging cyclesC，VC＝VC_PeriodN, N is charging current IREF_OThe number of cycles to charge the capacitance int _ C.
Thus, when V isC＝VREFGenerating a time-delay signal of VREF＝IREF*D/int_C*TDCan obtain the single delay time TDComprises the following steps:
Figure BDA0003315167340000091
delay time TDAnd a reference voltage VREFThe capacitance int _ C and the current limiting resistance Ext _ R are proportional and inversely proportional to the reference voltage Vref _ in and the duty ratio D. At a reference voltage VREFUnder the condition that the capacitor int _ C and the input voltage Vref _ in are fixed, the delay time T can be adjusted by adjusting the resistance value of the current-limiting resistor Ext _ R and the duty ratio DD。
Please refer to fig. 5a and 5b, which are timing diagrams of signals according to an embodiment.
In this embodiment, the duty ratio D of the clock control signal clk _ out is fixed, and the delay time is adjusted by changing the resistance of the current limiting resistor Ext _ R.
Referring to FIG. 5a, when the resistance of Ext _ R is larger, the charging current I is largerREF_OPeak current I ofREFSmaller, correspondingly, the voltage rising slope of the capacitor int _ C is small, and more time is required for converting the capacitor voltage VCCharging to a reference voltage VREFThus delaying the time TDWill be larger.
Similarly, referring to FIG. 5b, when using the Ext _ R with smaller resistance, the charging current IREF_OPeak current I ofREFBecomes larger, correspondingly, the voltage rising slope of the capacitor int _ C is larger, so the delay time TDIt will be reduced.
Compared with the capacitance value of the adjusting capacitor, the current limiting resistor Ext _ R has more selectable resistance values, and particularly when the current limiting resistor Ext _ R is an off-chip resistor, the resistance values are easier to combine, and the cost is far lower than that of the capacitor. Furthermore, for a system with high requirement on delay time precision, an off-chip resistor with high precision can be selected.
On-chip reference voltage Vref _ in and reference voltage VREFThe clock modulation module 130 can be effectively modified, has good enough precision, and can be modified by the clock, thereby having good precision and linearity. Although the capacitance of the capacitor int _ C and the offset of the comparator CMP are susceptible to the manufacturing process, the delay time T is affected to a certain extentDThe accuracy of (2). However, the reference voltage V can be adjusted during circuit designREFThe secondary trimming is carried out to eliminate the influence caused by the process and ensure the delay time TDWith sufficiently high accuracy.
Fig. 6 is a schematic structural diagram of a delay time linear controllable circuit according to another embodiment of the present invention.
In this embodiment, the delay time linear controllable circuit may further include a delay control logic block 150. The delay control logic module 150 is connected to the output end of the delay module 130, and is configured to adjust the delay time of the delay signal Vo, so as to further increase flexibility of adjusting the delay time.
In some embodiments, the delay control logic 150 may include a counter. Because the delay signal Vo is a pulse signal, the counter is used for counting the delay signal, when the count value reaches a threshold value N, the extended delay signal is output, and the extended delay time between adjacent extended delay signals is single delay time TDThereby conveniently realizing the multiple expansion of the delay time.
The delay control logic module 150 can be implemented by a digital circuit, and occupies a small area of a chip.
An embodiment of the present invention further provides a chip, including the delay time linear controllable circuit in any of the above embodiments, where a current limiting resistor may be integrated in the chip, and the current limiting resistor may be disposed outside the chip.
An embodiment of the present invention further provides an electronic device, including the delay time linear controllable circuit in any of the above embodiments.
The above embodiments are merely examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are all included in the scope of the present application.

Claims (10)

1. A delay time linearly controllable circuit, comprising:
the reference current generating module is used for generating a reference current inversely proportional to the resistance value of the current-limiting resistor;
the current source module is connected with the output end of the reference current generation module and used for carrying out integral control on the reference current under the control of a clock control signal with a specific duty ratio and outputting pulse type charging current with the duty ratio changing along with the duty ratio of the clock control signal;
the time delay module comprises a capacitor and a time delay unit, wherein the first end of the capacitor is grounded, the second end of the capacitor is connected to the output end of the charging current of the current source module, the time delay unit is connected to the second end of the capacitor and used for outputting a time delay signal after the voltage of the capacitor reaches the reference voltage according to the voltage change of the capacitor, and the charging time when the voltage of the capacitor reaches the reference voltage at a single time corresponds to the delay time of the time delay signal output at a single time.
2. The delay time linear controllable circuit of claim 1, wherein the delay unit comprises a comparator, one input terminal of the comparator is connected to the second terminal of the capacitor, the other input terminal is connected to the reference voltage, the comparator is configured to compare the voltage of the capacitor with the reference voltage, and output the comparison result as the delay signal of a single cycle.
3. The delay time linearly controllable circuit according to claim 1, further comprising: the output end of the delay unit is further connected to the current source module, and when the delay unit outputs the delay signal of a single period, the delay signal is further used for controlling the current source module to discharge the capacitor and reset the voltage of the capacitor so as to enter the next charging period.
4. The delay time linearly controllable circuit of claim 1, wherein said reference current generating module comprises: the voltage-to-current unit is connected with the current limiting resistor and is used for applying reference voltage on the current limiting resistor so that the reference current generating module generates reference current inversely proportional to the resistance value of the current limiting resistor and outputs the reference current to the current source module; wherein the current limiting resistor is an off-chip variable resistor.
5. The delay time linearly controllable circuit according to claim 4, wherein the reference current generating module further comprises an open short detecting unit for detecting an electrical connection state of a connection terminal between the off-chip variable resistor and the voltage-to-current converting unit.
6. The delay time linear controllable circuit according to claim 5, wherein the open/short detection unit is configured to detect the voltage of the connection terminal, and compare the detected voltage with a first threshold and a second threshold to determine an open circuit or a short circuit state of the connection terminal, the first threshold is a connection terminal threshold voltage corresponding to the open circuit state, and the second threshold is a connection short threshold voltage corresponding to the short circuit state.
7. The delay time linearly controllable circuit of claim 1, further comprising a delay control logic module connected to an output of said delay module for adjusting a delay time of said delay signal.
8. The delay time linear controllable circuit of claim 7, wherein the delay control logic module comprises a counter, the counter is configured to count the received delay signal, and when the count value reaches a threshold value N, the delay control logic module outputs an extended delay signal, an extended delay time of the extended delay signal is N times of a single delay time, and N is an integer greater than or equal to 1.
9. A chip, comprising: the delay time linearly controllable circuit of any one of claims 1 to 8.
10. An electronic device, comprising:
a delay time linearly controllable circuit as claimed in claims 1 to 8.
CN202111228684.7A 2021-10-21 2021-10-21 Delay time linear controllable circuit, chip and electronic equipment Pending CN113839651A (en)

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CN202111228684.7A CN113839651A (en) 2021-10-21 2021-10-21 Delay time linear controllable circuit, chip and electronic equipment

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114825300A (en) * 2022-06-27 2022-07-29 深圳市芯卓微科技有限公司 Current-limiting delay circuit and current-limiting delay chip
CN115483820A (en) * 2022-09-20 2022-12-16 合肥工业大学 Adjustable dead time circuit
CN116248085A (en) * 2022-12-28 2023-06-09 无锡摩芯半导体有限公司 Implementation method of high-precision delay generating circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114825300A (en) * 2022-06-27 2022-07-29 深圳市芯卓微科技有限公司 Current-limiting delay circuit and current-limiting delay chip
CN114825300B (en) * 2022-06-27 2022-10-04 深圳市芯卓微科技有限公司 Current-limiting delay circuit and current-limiting delay chip
CN115483820A (en) * 2022-09-20 2022-12-16 合肥工业大学 Adjustable dead time circuit
CN115483820B (en) * 2022-09-20 2023-09-12 合肥工业大学 Adjustable dead time circuit
CN116248085A (en) * 2022-12-28 2023-06-09 无锡摩芯半导体有限公司 Implementation method of high-precision delay generating circuit

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