CN115482855A

CN115482855A - 10T-SRAM unit and data read-write method and circuit structure thereof

Info

Publication number: CN115482855A
Application number: CN202211158024.0A
Authority: CN
Inventors: 戴成虎; 杜园园; 高珊; 彭春雨; 赵强; 卢文娟; 郝礼才; 刘立; 蔺智挺; 吴秀龙; 黎轩; 郑好
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2022-06-08
Filing date: 2022-06-08
Publication date: 2022-12-16
Also published as: CN114822637B; CN114822637A

Abstract

The invention relates to a 10T-SRAM unit and a data reading and writing method and a circuit structure thereof. The 10T-SRAM cell includes NMOS transistors N0-N7 and PMOS transistors P0-P1. The storage node QB is connected with a word line WLL and a bit line BLB through N2; the storage node Q is connected with a word line WLR and a bit line BL through N3; p0 and N0 form an inverter, P1 and N1 form another inverter, and the two inverters form a cross-coupling structure; n2 and N3 are used as transmission pipes which are respectively positioned at the left side and the right side of the cross coupling structure and used as a left writing channel and a right writing channel; n4 and N6 constitute the left path, and N5 and N7 constitute the right path. The invention can realize that two rows of data are read in the same period, can simultaneously carry out horizontal and vertical bidirectional memory logical operation and BCAM data search operation, ensures the data independence during operation and improves the anti-interference capability and the calculation efficiency of the unit.

Description

10T-SRAM unit and data read-write method and circuit structure thereof

The application is a divisional application with the application number of CN202210638677.2 and the application date of 2020/06/08, and the invention name is a circuit structure, a chip and a module based on a 10T-SRAM unit.

Technical Field

The invention relates to the technical field of static random access memories, in particular to a 10T-SRAM unit and a data reading and writing method and a circuit structure thereof.

Background

As one of effective strategies for breaking through the von neumann architecture, memory computing (called CIM for short) attracts a great deal of attention, and the memory computing integrates a memory and an operation module, so that data movement is greatly reduced, and time and energy consumption overhead of the part is further saved.

The content addressable memory (abbreviated as BCAM) is used as a special application of memory calculation, and by comparing data input with stored data bit by bit, comparison operation is completed in the memory, so that the search efficiency is improved, and the power consumption is reduced. The existing BCAM research is mainly limited by unidirectional data search, some data are longitudinally input and compared with array storage words line by line, the structure is complex and solidified, the reusability of a module is poor, and the function is single; some data are transversely input, are compared with array storage words column by column, are contrary to SRAM data in a row writing mode, and are difficult to write data to be compared. According to the disclosure CN102024819A, the SRAM bit cell device and the CAM bit cell device have the advantages of lower standby leakage current Isb, improved Vcc, min for reducing standby power consumption, and improved access speed. But the column and column logic operations in the 10T-SRAM cell of the device cannot be performed simultaneously.

Disclosure of Invention

Based on this, it is necessary to provide a 10T-SRAM cell, a data read/write method thereof, a circuit structure, a module, and a chip, for solving the problem that it is not easy to write data to be compared in unidirectional data search.

A 10T-SRAM cell, comprising: NMOS transistors N0-N7, and PMOS transistors P0-P1.

The specific connection mode is as follows: the source of N0 is electrically connected to a voltage source VSS.

The grid electrode of the N1 is electrically connected with the drain electrode of the N0, the source electrode of the N1 is electrically connected with the source electrode of the N0, and the drain electrode of the N1 is electrically connected with the grid electrode of the N0.

The drain electrode of P0 is electrically connected with the drain electrode of N0, the grid electrode of P0 is electrically connected with the grid electrode of N0, and the source electrode of P0 is electrically connected with a voltage source VDD.

The drain of P1 is electrically connected to the drain of N1, the gate of P1 is electrically connected to the drain of P0, and the source of P1 is electrically connected to the source of P0.

The drain of N2 is electrically connected to the drain of N0, the gate of N2 is electrically connected to word line WLL, and the source of N2 is electrically connected to bit line BLB.

The drain of N3 is electrically connected with the gate of N0, the gate of N3 is electrically connected with a word line WLR, and the source of N3 is electrically connected with a bit line BL.

The gate of N4 is electrically connected to the drain of N0, and the source of N4 is electrically connected to bit line RBLB.

The gate of N5 is electrically connected to the drain of N1, and the source of N5 is electrically connected to bit line RBL.

The drain of N6 is electrically connected to the drain of N4, the gate of N6 is electrically connected to word line RWLL, and the source of N6 is electrically connected to voltage source VSS.

The drain of N7 is electrically connected to the drain of N5, the source of N7 is electrically connected to the source of N6, and the gate of N7 is electrically connected to the word line RWLR.

The storage node QB is connected with a word line WLL and a bit line BLB through N2; the storage node Q is connected with a word line WLR and a bit line BL through N3; p0 and N0 form an inverter, P1 and N1 form another inverter, and the two inverters form a cross-coupling structure; n2 and N3 are used as transmission pipes which are respectively positioned at the left side and the right side of the cross coupling structure and used as a left writing channel and a right writing channel; n4 and N6 constitute the left path, and N5 and N7 constitute the right path.

Further, when data is written into the 10T-SRAM cell, writing is performed through BL and BLB, and the word line WLL and the word line WLR are set to a high level.

Further, when data is read from the 10T-SRAM cell, the data is read through RBLB or RBL, and the word line RWLL or RWLR is set to high level.

The invention also comprises a data reading and writing method according to the 10T-SRAM unit, wherein the data reading and writing method writes data through BL and BLB when the data is written, and the word line WLL and the word line WLR are set to be high level; in the data reading and writing method, when data is read, the data is read out through RBLB or RBL, and a word line RWLL or a word line RWLR is set to be high level.

The invention also provides a circuit structure based on the memory Boolean logic operation and the bidirectional BCAM of the 10T-SRAM unit, which adopts the 10T-SRAM unit, and the circuit structure based on the memory Boolean logic operation and the bidirectional BCAM of the 10T-SRAM unit comprises 4 multiplied by 4 10T-SRAM units.

The 10T-SRAM units are positioned in the same row, the gates of all the unit transistors N2 are electrically connected with a word line WLL, the gates of all the unit transistors N3 are electrically connected with a word line WLR, the sources of all the unit transistors N4 are electrically connected with a bit line RBLB, the sources of all the unit transistors N5 are electrically connected with a bit line RBL, and each row shares the word lines WLL and WLR and the bit lines RBL and RBLB.

The 10T-SRAM cells are positioned in the same column, the sources of all the cell transistors N2 are electrically connected with a bit line BLB, the sources of all the cell transistors N3 are electrically connected with a bit line BL, the gates of all the cell transistors N6 are electrically connected with a word line RWLL, the gates of all the cell transistors N7 are electrically connected with a word line RWLR, and each column shares the bit lines BL and BLB and the word lines RWLL and RWLR.

When the circuit structure searches data row by row according to an array, word lines RWLL and RWLR are respectively used as data input lines, bit lines RBL and RBLB are used as matched lines, and matching results are read out through and gates by sense amplifiers at the tail ends of the bit lines RBL and RBLB. When data is searched column by column according to the array, word lines WLL and WLR are respectively used as data input lines, bit lines BL and BLB are used as matched lines, and matching results are read out through sense amplifiers at the tail ends of the bit lines BL and BLB and then an AND gate.

Further, during the data retention period of the 10T-SRAM cell, the write word line WLL, the write word line WLR, the read word line RWLL and the read word line RWLR are all kept at a low level, and N2, N3, N6 and N7 are all turned off.

Further, assuming that the storage node Q of the 10T-SRAM cell is high and QB is low before the write operation, i.e., storing data is "1", when writing data "0", the write operation word lines WLL and WLR are pulled to high selected cells, and at the same time, data "0" to be written is loaded on the write bit lines BL and BLB.

Further, suppose that before a read operation, the storage node Q of the 10T-SRAM cell is high, QB is low, i.e. the storage data is "1"; at the beginning of the read operation, the read bit lines RBL and RBLB are precharged to high, the read word line RWLL or RWLR is pulled high, and the NMOS transistor N6 or NMOS transistor N7 is turned on.

The invention also comprises a circuit module based on the memory Boolean logic operation and the bidirectional BCAM of the 10T-SRAM unit, which adopts the circuit structure based on the memory Boolean logic operation and the bidirectional BCAM of the 10T-SRAM unit, and the circuit module based on the memory Boolean logic operation and the bidirectional BCAM of the 10T-SRAM unit comprises:

the 10T-SRAM units are positioned on the same row, the grids of all the unit transistors N2 are electrically connected with a word line WLL, so that a first connection end is led out, the grids of all the unit transistors N3 are electrically connected with a word line WLR, so that a second connection end is led out, the sources of all the unit transistors N4 are electrically connected with a bit line RBLB, so that a third connection end is led out, and the sources of all the unit transistors N5 are electrically connected with a bit line RBL, so that a fourth connection end is led out; each row has a first link end, a second link end, a third link end and a fourth link end.

10T-SRAM cells located in the same column, the sources of all cell transistors N2 are electrically connected to bit line BLB, thereby leading out a fifth connection terminal, the sources of all cell transistors N3 are electrically connected to bit line BL, thereby leading out a sixth connection terminal, the gates of all cell transistors N6 are electrically connected to word line RWLL, thereby leading out a seventh connection terminal, and the gates of all cell transistors N7 are electrically connected to word line RWLR, thereby leading out an eighth connection terminal; there is one fifth, sixth, seventh and eighth connection end per column.

The invention also comprises a circuit chip based on the memory Boolean logic operation and the bidirectional BCAM of the 10T-SRAM unit, which is packaged by adopting the circuit structure based on the memory Boolean logic operation and the bidirectional BCAM of the 10T-SRAM unit.

The technical scheme provided by the invention has the following beneficial effects:

the 10T-SRAM unit adopts double-port arrangement and cross layout of double word lines and double bit lines to control the on and off of different word lines, can activate arrays of multiple rows and multiple columns in parallel, realizes vector logic operation in two directions, enables a storage array constructed by the 10T-SRAM unit to have good symmetry, can read two columns of data in the same period, can simultaneously perform horizontal and vertical bidirectional memory logic operation and BCAM data search operation, ensures data independence during operation, and improves the anti-interference capability and the calculation efficiency of the unit. Its symmetry provides column-wise or row-wise searching of data, which is easily adaptable to SRAM storage modes. These modes allow matrix transpose, logic operations, and Content Addressable Memory (CAM) data searches in memory computations without requiring additional data movement.

Drawings

FIG. 1 is a schematic diagram of a 10T-SRAM cell according to the present invention;

FIG. 2 is a schematic diagram of a structure for performing AND/OR NOT logic operation on data by rows or columns based on FIG. 1;

FIG. 3 is a diagram of row-wise or column-wise processing of data based on FIG. 1

And

a schematic diagram of a logical operation structure;

FIG. 4 is a schematic diagram of the structure of the exclusive OR and XOR operation performed on the data by rows or columns based on FIG. 1;

FIG. 5 is a schematic diagram of a 4 × 4 10T-SRAM cell based on the 10T-SRAM cell of FIG. 1;

FIG. 6 is a timing diagram illustrating the operation of the bi-directional BCAM search based on FIG. 5;

FIG. 7 is a schematic diagram of a circuit chip based on the 10T-SRAM cell memory Boolean logic operation and bidirectional BCAM based on 4 × 4 10T-SRAM cells in FIG. 5.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in FIG. 1, the present invention provides a 10T-SRAM cell, which comprises NMOS transistors N0-N7 and PMOS transistors P0-P1, wherein P0 and N0 form one inverter, P1 and N1 form another inverter, and the two inverters form a cross-coupled structure; n2 and N3 are used as transmission pipes which are respectively positioned at the left side and the right side of the cross coupling structure and used as a left writing channel and a right writing channel; n4 and N6 constitute the left path, and N5 and N7 constitute the right path.

The concrete connection mode is as follows: the gate of the NMOS transistor N1, N1 is electrically connected to the drain of N0, the source of N1 is electrically connected to the source of N0, and the drain of N1 is electrically connected to the gate of N0. The drains of the NMOS transistors N2 and N2 are electrically connected to the drain of N0 and the gate of N1, the gate of N2 is electrically connected to the word line WLL, and the source of the NMOS transistor N2 is electrically connected to the bit line BLB. The drains of the NMOS transistors N3, N3 are electrically connected to the gates of N0 and N1, the gate of N3 is electrically connected to the word line WLR, and the source of N3 is electrically connected to the bit line BL. The gates of the NMOS transistors N4 and N4 are electrically connected to the drain of N0, the gate of N1, and the drain of N2, and the source of N4 is electrically connected to the bit line RBLB. The gates of NMOS transistors N5, N5 are electrically connected to the drain of N1, the gate of N0, and the drain of N3, and the source of N5 is electrically connected to bit line RBL. The drains of NMOS transistors N6, N6 are electrically connected to the drain of N4, and the gate of N6 is electrically connected to word line RWLL. The drains of the NMOS transistors N7 and N7 are electrically connected to the drain of N5, the source of N7 is electrically connected to the source of N6, and the gate of N7 is electrically connected to the word line RWLR. The drains of the PMOS transistors P0 and P0 are electrically connected to the drain of N0, the drain of N2, the gate of N1, and the gate of N4, and the gate of P0 is electrically connected to the drain of N1, the drain of N3, the gate of N0, and the gate of N5. The drains of the PMOS transistors P1 and P1 are electrically connected to the drain of N1, the drain of N3, the gate of N0, the gate of N5, and the gate of P0, the gate of P1 is electrically connected to the drain of P0, the drain of N2, the gate of N1, and the gate of N4, and the source of P1 is electrically connected to the source of P0.

When data are written by using a 10T-SRAM unit, writing is carried out through BL and BLB, and a word line WLL and a word line WLR are set to be high level; when data is read by using the 10T-SRAM unit, the data is read through RBLB or RBL, RWL or RWLR is set to high level.

On the basis of the 10T-SRAM unit, a circuit structure based on the memory Boolean logic operation and bidirectional BCAM of the 10T-SRAM unit can be constructed, and the circuit structure comprises 4 x 4 10T-SRAM units.

For 4 × 4 10T-SRAM cells, the 10T-SRAM cells in the same row are electrically connected to a word line WLL at the gates of all cell transistors N2, a word line WLR at the gates of all cell transistors N3, a bit line RBLB at the sources of all cell transistors N4, a bit line RBL at the sources of all cell transistors N5, and word lines WLL and WLR and bit lines RBL and RBLB shared by each row. The 10T-SRAM cells are positioned in the same column, the sources of all the cell transistors N2 are electrically connected with a bit line BLB, the sources of all the cell transistors N3 are electrically connected with a bit line BL, the gates of all the cell transistors N6 are electrically connected with a word line RWLL, the gates of all the cell transistors N7 are electrically connected with a word line RWLR, and each column shares the bit lines BL and BLB and the word lines RWLL and RWLR. Each column shares a bit line BL, BLB and a word line RWLL, RWLR. BL and BLB are connected to two sense amplifiers SA at the end of each column, on the basis of which an and gate is connected for readout. RBL and RBLB are connected to two sense amplifiers SA at the end of each row, on the basis of which an and gate is connected for readout.

The specific operation is as follows: when data is searched Row by Row according to the array, word lines RWLL and RWLR are respectively used as data input lines, bit lines RBL and RBLB are used as matched lines, and matching results are read out through sense amplifiers at the tail ends of the bit lines RBL and RBLB and then through an AND gate, and are marked as Row Search. When data is searched Column by Column according to the array, word lines WLL and WLR are respectively used as data input lines, bit lines BL and BLB are used as matched lines, and matching results are read out through sense amplifiers at the tail ends of the bit lines BL and BLB and then an AND gate and are marked as Column Search.

The array structure can simultaneously realize horizontal and vertical bidirectional BCAM data search operation without increasing the number of transistors, not only can be well adapted to the writing mode of an SRAM, but also increases the reusability of the structure, greatly improves the anti-interference capability of data, and can be adapted to various complex application scenes.

Taking the SRAM mode as an example, the SRAM mode is performed on the basis of the 4 × 4 10T-SRAM cells, and the specific operation steps are as follows:

(1) Hold operation

During the period of holding data in the memory cell, the write word line WLL, the write word line WLR, the read word line RWLL, and the read word line RWLR are all kept low. At this time, the NMOS transistor N2, the NMOS transistor N3, the NMOS transistor N6, and the NMOS transistor N7 are all turned off, and the write bit lines BL and BLB and the read bit lines RBL and RBLB do not affect the storage node Q or QB. The latch structure composed of the PMOS transistor P0, the NMOS transistor N0, the PMOS transistor P1, and the NMOS transistor N1 latches data of the storage nodes Q and QB.

(2) Write operation

Assuming that before a write operation, storage node Q of the storage unit is at a high level and QB is at a low level, that is, data is stored as "1", when data "0" is written, word lines WLL and WLR of the write operation are pulled to a high-level selected unit, and at the same time, data "0" to be written is loaded on a write bit line, that is, BL is at a low level and BLB is at a high level. BL pulls down node Q through NMOS transistor N3, BLB pulls up node QB through NMOS transistor N2, and the feedback loop of the stored structure is broken, and data "0" is written into the memory cell. Writing data "1" is the same as the process described above.

(3) Read operation

Suppose before a read operation, the storage node Q of the memory cell is high and QB is low, i.e., the stored data is "1". At the beginning of the read operation, the read bit lines RBL and RBLB are precharged to high, the read word line RWLL or RWLR is pulled to high, and the NMOS transistor N6 or NMOS transistor N7 is turned on. If the NMOS transistor N6 is turned on, since the storage node QB is low, the NMOS transistor N4 is turned off, the read bit line RBLB remains high, and the read result is "1" after being amplified by the sense amplifier SA. If the QB node is high, the same procedure as above is performed.

The truth table for implementing the SRAM mode is shown in the following table, where a denotes an a-th column, B denotes a B-th column, L denotes a low level, H denotes a high level, read denotes a Read operation, write denotes a Write operation, and Hold denotes a Hold state.

SRAM truth table

Taking the memory calculation mode as an example, the memory calculation mode is performed on the basis of the 4 × 4 10T-SRAM cells.

The following is a Boolean logic operation in memory computing mode, and is implemented as follows:

as shown in fig. 2, the 1-bit logical and operation is used as an example to describe the implementation of two or more rows of logical and operations between the same columns via BL and BLB.

And controlling the on and off of WLL and WLR between the same columns, and realizing two or more rows of logical AND operation and/or NOT operation through BL and BLB. And the RWLL and the RWLR are controlled to be switched on and off between the same rows, and two or more columns of logic AND operation or AND operation is realized through the RBL and the RBLB. The cell storage data of the first row of the first column is marked as Q3, the word lines are marked as WLL1 and WLR1, the bit lines are marked as BLB1 and BL1, the cell storage data of the second row of the first column is marked as Q1, the word lines are marked as WLL0 and WLR0, the bit line BLB1 is provided with a single-ended Sense Amplifier (SA), the bit line BL1 is also provided with a single-ended sense amplifier, and the output ends of the two sense amplifiers are connected with an AND gate to serve as logic output. Bit lines BLB1 and BL1 are precharged to a high level, word lines WLL1 and WLL0 are set to a low level, word lines WLR1 and WLR0 are set to a high level, data 0 exists at any node of Q3 and Q1, and discharge occurs in the bit line BL 1; only nodes Q3 and Q1 are simultaneously 1, bit line BL1 is kept at a high level, and since word line WLL1 and word line WLL0 are both at a low level, BLB1 is kept at a high level all the time, and the logical and operation of Q3 and Q1 can be realized by SA and gate.

As shown in fig. 3, with 1-bit logic

Operation as an example to introduce the implementation of two columns of logic between the same row via RBL and RBLB

And (6) operation.

Between the same column, the WLL and the WLR are controlled to be switched on and off, and two rows of logic are realized through the BL and the BLB

Or

And (6) operation. Controlling the RWLL and the RWLR to be turned on and off between the same rows, and realizing two-column logic through the RBL and the RBLB

Or

And (6) operation. The cell memory data of the first column in the first row is denoted as Q3, the word lines are denoted as RWLL1 and RWLR1, the bit lines are denoted as RBLB1 and RBL1, and the cell memory of the second column in the first row is denoted as RBLB1 and RBL1The store data is denoted as Q2 and the word lines are denoted as RWL 0 and RWLR0. Bit line RBLB1 is provided with a single-ended Sense Amplifier (SA), bit line RBL1 is also provided with a single-ended sense amplifier, and the output ends of the two sense amplifiers are connected with an AND gate to be used as logic output. Bit lines RBLB1 and RBL1 are precharged to high level, word lines RWLR1 and RWLL0 are set to low level, word lines RWLR1 and RWLR0 are set to high level, only when at least one of QB3 and Q2 is 1, at least one of RBL1 and RBLB1 is discharged, and low level is obtained by output of sense amplifier and AND gate, thus realizing logic

And (6) operation.

As shown in fig. 4, the same column is described as an example of the logical exclusive-or operation, and two rows of the logical exclusive-or operation are implemented by BL and BLB.

And between the same column, WLL and WLR of a certain two rows are simultaneously started, and logical OR, AND XOR operation of the two rows is realized through BL and BLB. RWLL and RWLR of a certain two columns are simultaneously opened between the same rows, and logic exclusive OR and exclusive OR operation of the two columns is realized through RBL and RBLB. The cell storage data of the first row of the first column is marked as Q3, the word lines are marked as WLL1 and WLR1, the bit lines are marked as BLB1 and BL1, the cell storage data of the second row of the first column is marked as Q1, the word lines are marked as WLL0 and WLR0, the bit line BLB1 is provided with a single-ended Sense Amplifier (SA), the bit line BL1 is also provided with a single-ended sense amplifier, and the output ends of the two sense amplifiers are connected with an AND gate to serve as logic output. Bit lines BLB1 and BL1 are precharged high, word line WLL1, word line WLL0, word lines WLR1 and WLR0 are all set high, since Q3Q1 has four states: 00. 01, 10, 11, so that the bit line discharge voltages will be different accordingly, the logic OR operation and logic can be implemented using the reference voltages of the sense amplifiers

And performing operation, and then performing an AND gate to realize the logical XOR operation of the Q3 and the Q1.

The following is a specific implementation of the bidirectional BCAM in the memory computing mode as follows:

as shown in fig. 5, before data search, memory cells store binary data to be searched, match lines BL, BLB, RBL, and RBLB are precharged to a high level, and data input lines WLL, WLR, RWLL, and RWLR are set to a high level or a low level according to the search data. If the search data is 1, WLR and RWLL are set to high level, WLL and RWLR are set to low level; if the lookup data is 0, WLR and RWLL are set low, and WLL and RWLR are set high.

In order to more clearly show the technical solution and the technical effects provided by the present invention, taking 4-bit binary data "0110" as an example, RWLL3, RWLR2, RWLR1 and RWLL0 are set to low level, and RWLL2, RWLR3, RWLR0 and RWLL1 are set to high level. The array has a total of four rows, and each row of memory cells from left to right are respectively stored with '0110', '0101', '1100' and '1110'. Analyzing the data comparison process, when the search data is "0", RWLR is high, and only when the storage node is "1", the corresponding RBL is discharged, which represents that the search data does not match. Because RWLL is low, RBLB remains high, and then RBL and RBLB pass through two sense amplifiers and an and gate, and finally output whether the result matches. RWL is high when the search data is "1", and only when the storage node is "0", the corresponding RBLB will discharge, indicating that the searched data does not match. Because RWLR is low, RBL remains high, and then RBL and RBLB pass through two sense amplifiers and an and gate, and finally output whether the result matches. And finally outputting high level if the search data is completely matched with the stored data. And finally outputting low level if the search data and the stored data are not completely matched.

For example, if Column Search is performed on 4-bit binary data "1001", WLL3, WLR2, WLR1, and WLL0 are set to low level, and WLL2, WLR3, WLR0, and WLL1 are set to high level. WLL is high when the searched data is "0", and the corresponding BLB is discharged only when the storage node is "1", indicating that the searched data does not match. Since WLR is low, BL remains high, and BL and BLB pass through two sense amplifiers and an and gate, and finally output whether the result matches. WLR is high when the search data is "1", and the corresponding BL is discharged only when the storage node is "0", indicating that the searched data does not match. Since WLL is low, BLB remains high, and BL and BLB pass through two sense amplifiers and an and gate, and finally output whether the result matches. And finally outputting high level if the search data is completely matched with the stored data. And finally outputting low level if the search data and the stored data are not completely matched.

The truth table for implementing the CIM mode is shown in the following table, wherein A denotes the A-th row (column), B denotes the B-th row (column), L denotes the low level, H denotes the high level ^A Indicating that the corresponding word line in row A is high, L ¹ Indicating that if the search data is 1, the corresponding word line should be set to low.

Truth table for internal Boolean logic operation and bidirectional BCAM function

In summary, the 10T-SRAM cell adopts a dual-port arrangement and a cross layout of a dual word line and a dual bit line, so that the memory array constructed by the 10T-SRAM cell has good symmetry, not only can two rows of data be read in the same period, but also can perform horizontal and vertical bidirectional memory logic operation and BCAM data search operation simultaneously, ensure data independence during operation, and improve the anti-interference capability and the calculation efficiency of the cell.

As shown in fig. 7, on the basis of the 4 × 4 10T-SRAM cells, a circuit chip based on memory boolean logic operation and bidirectional BCAM of the 10T-SRAM cell is further provided, which is packaged by the 4 × 4 10T-SRAM cells, and is packaged into a chip mode, so that the popularization and application of the 4 × 4 10T-SRAM cell circuit are easier.

The pins of the circuit chip based on the memory Boolean logic operation and the bidirectional BCAM of the 10T-SRAM unit comprise: four 10T-SRAM cells positioned in the first row, wherein the gates of all the cell transistors N2 are electrically connected with a word line WLL, so that a first pin is led out; the grids of all the unit transistors N3 are electrically connected with a word line WLR, so that a second pin is led out; the sources of all the unit transistors N4 are electrically connected with a bit line RBLB, so that a third pin is led out; the source electrodes of all the unit transistors N5 are electrically connected with a bit line RBL, so that a fourth pin is led out; one of the first pin, the second pin, the third pin, and the fourth pin is present in a first row. Four 10T-SRAM cells positioned in the second row, wherein the grids of all the cell transistors N2 are electrically connected with a word line WLL, so that a fifth pin is led out; the grids of all the unit transistors N3 are electrically connected with a word line WLR, so that a sixth pin is led out; the source electrodes of all the unit transistors N4 are electrically connected with a bit line RBLB, so that a seventh pin is led out; the source electrodes of all the unit transistors N5 are electrically connected with a bit line RBL, so that an eighth pin is led out; one of the fifth pin, the sixth pin, the seventh pin, and the eighth pin exists in the second row. Four 10T-SRAM cells in the third row, wherein the gates of all the cell transistors N2 are electrically connected to a word line WLL, so that a ninth pin is led out; the grids of all the unit transistors N3 are electrically connected with a word line WLR, so that a tenth pin is led out; the sources of all the cell transistors N4 are electrically connected to a bit line RBLB, thereby leading out an eleventh pin; the sources of all the cell transistors N5 are electrically connected with a bit line RBL, so that a twelfth pin is led out; there is one of the ninth pin, the tenth pin, the eleventh pin, and the twelfth pin in a third row. Four 10T-SRAM cells positioned in the fourth row, wherein the gates of all the cell transistors N2 are electrically connected with a word line WLL, so that a thirteenth pin is led out; the grids of all the unit transistors N3 are electrically connected with a word line WLR, so that a fourteenth pin is led out; the sources of all the cell transistors N4 are electrically connected to a bit line RBLB, thereby drawing a fifteenth pin; the sources of all the cell transistors N5 are electrically connected to a bit line RBL, thereby leading out a sixteenth pin; there is one of the thirteenth pin, the fourteenth pin, the fifteenth pin, and the sixteenth pin in a fourth row.

The 10T-SRAM unit is positioned in the first column, the sources of all the unit transistors N2 are electrically connected with a bit line BLB, so that a seventeenth pin is led out, the sources of all the unit transistors N3 are electrically connected with a bit line BL, so that an eighteenth pin is led out, the gates of all the unit transistors N6 are electrically connected with a word line RWLL, so that a nineteenth pin is led out, and the gates of all the unit transistors N7 are electrically connected with a word line RWLR, so that a twentieth pin is led out; there is one of the seventeen, eighteen, nineteen, and twenty pins in the first column. In the 10T-SRAM cell located in the second column, the sources of all the cell transistors N2 are electrically connected to the bit line BLB, thereby leading out a twenty-first pin, the sources of all the cell transistors N3 are electrically connected to the bit line BL, thereby leading out a twenty-second pin, the gates of all the cell transistors N6 are electrically connected to the word line RWLL, thereby leading out a twenty-third pin, and the gates of all the cell transistors N7 are electrically connected to the word line RWLR, thereby leading out a twenty-fourth pin; there is one of the twenty-one pins, the twenty-two pins, the twenty-three pins, and the twenty-four pins in a second column. A 10T-SRAM cell located in the third column, sources of all the cell transistors N2 being electrically connected to a bit line BLB, thereby drawing a twenty-fifth pin, sources of all the cell transistors N3 being electrically connected to a bit line BL, thereby drawing a twenty-sixth pin, gates of all the cell transistors N6 being electrically connected to a word line RWLL, thereby drawing a twenty-seventh pin, and gates of all the cell transistors N7 being electrically connected to a word line RWLR, thereby drawing a twenty-eighth pin; a third column has one of the twenty-five pins, the twenty-six pins, the twenty-seven pins, and the twenty-eight pins. In the 10T-SRAM cell located in the fourth column, the sources of all the cell transistors N2 are electrically connected to the bit line BLB, thereby leading out a twenty-ninth pin, the sources of all the cell transistors N3 are electrically connected to the bit line BL, thereby leading out a thirtieth pin, the gates of all the cell transistors N6 are electrically connected to the word line RWLL, thereby leading out a thirty-eleventh pin, and the gates of all the cell transistors N7 are electrically connected to the word line RWLR, thereby leading out a thirty-second pin; a fourth column has one of the twenty-nine pins, the thirty-pin, the thirty-one pin, and the thirty-two pin.

On the basis of the 4 x 4 10T-SRAM units, a circuit module based on the memory Boolean logic operation and bidirectional BCAM of the 10T-SRAM unit is also provided, and comprises: the 10T-SRAM unit is positioned in the same row, the grids of all the unit transistors N2 are electrically connected with a word line WLL, so that a first connecting end is led out, the grids of all the unit transistors N3 are electrically connected with a word line WLR, so that a second connecting end is led out, the sources of all the unit transistors N4 are electrically connected with a bit line RBLB, so that a third connecting end is led out, and the sources of all the unit transistors N5 are electrically connected with a bit line RBL, so that a fourth connecting end is led out; there is one of the first, second, third and fourth link ends per row. 10T-SRAM cells located in the same column, the sources of all cell transistors N2 are electrically connected to bit line BLB, thereby leading out a fifth connection terminal, the sources of all cell transistors N3 are electrically connected to bit line BL, thereby leading out a sixth connection terminal, the gates of all cell transistors N6 are electrically connected to word line RWLL, thereby leading out a seventh connection terminal, and the gates of all cell transistors N7 are electrically connected to word line RWLR, thereby leading out an eighth connection terminal; there is one of the fifth, sixth, seventh and eighth connection ends per column.

The circuit structure based on the memory Boolean logic operation of the 10T-SRAM unit and the bidirectional BCAM is designed into a circuit module, so that the memory Boolean logic operation based on the 10T-SRAM unit and the circuit structure based on the bidirectional BCAM can be conveniently popularized and applied in the market, the circuit module is convenient for technicians in the field to use quickly, and the circuit module can be connected by lines only by facing to a product specification.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A 10T-SRAM cell, comprising: NMOS transistors N0 to N7, PMOS transistors P0 to P1;

the source electrodes of the NMOS transistors N0 and N0 are electrically connected with a voltage source VSS;

the grid electrode of the NMOS transistor N1, N1 is electrically connected with the drain electrode of N0, the source electrode of N1 is electrically connected with the source electrode of N0, and the drain electrode of N1 is electrically connected with the grid electrode of N0;

the drain electrode of the PMOS transistor P0 is electrically connected with the drain electrode of the N0, the grid electrode of the P0 is electrically connected with the grid electrode of the N0, and the source electrode of the P0 is electrically connected with a voltage source VDD;

the drain electrode of the PMOS transistor P1, the drain electrode of the P1 is electrically connected with the drain electrode of the N1, the grid electrode of the P1 is electrically connected with the drain electrode of the P0, and the source electrode of the P1 is electrically connected with the source electrode of the P0;

it is characterized in that the preparation method is characterized in that,

the drain electrode of the NMOS transistor N2 and N2 is electrically connected with the drain electrode of the N0, the grid electrode of the N2 is electrically connected with a word line WLL, and the source electrode of the N2 is electrically connected with a bit line BLB;

the drain electrode of the NMOS transistor N3 and N3 is electrically connected with the grid electrode of N0, the grid electrode of N3 is electrically connected with a word line WLR, and the source electrode of N3 is electrically connected with a bit line BL;

the grid electrode of the NMOS transistor N4 and N4 is electrically connected with the drain electrode of the N0, and the source electrode of the N4 is electrically connected with a bit line RBLB;

the grid electrode of the NMOS transistor N5 and the grid electrode of the N5 are electrically connected with the drain electrode of the N1, and the source electrode of the N5 is electrically connected with a bit line RBL;

the drain electrode of the NMOS transistor N6 and the drain electrode of the N6 are electrically connected with the drain electrode of the N4, the grid electrode of the N6 is electrically connected with the word line RWLL, and the source electrode of the N6 is electrically connected with the voltage source VSS;

the drain of the NMOS transistor N7 and the drain of the N7 are electrically connected with the drain of the N5, the source of the N7 is electrically connected with the source of the N6, and the grid of the N7 is electrically connected with the word line RWLR;

2. The 10T-SRAM cell of claim 1, wherein when data is written to the 10T-SRAM cell, the data is written through BL and BLB, and word line WLL and word line WLR are set to high level.

3. The 10T-SRAM cell of claim 1, wherein during data read of the 10T-SRAM cell, read is performed via RBLB or RBL, and word line RWLL or RWLR is set high.

4. A data read-write method of the 10T-SRAM cell according to claim 1, wherein the data read-write method writes data by BL and BLB at the time of data writing, and the word line WLL and the word line WLR are set to high level; in the data reading and writing method, when data is read, the data is read through RBLB or RBL, and the word line RWLL or RWLR is set to be high level.

5. A circuit structure based on the memory boolean logic operation and bidirectional BCAM of a 10T-SRAM cell, characterized in that it employs the 10T-SRAM cell according to claim 1, 2 or 3, said circuit structure based on the memory boolean logic operation and bidirectional BCAM of a 10T-SRAM cell comprising 4 x 4 10T-SRAM cells;

the 10T-SRAM units are positioned on the same row, the grids of all the unit transistors N2 are electrically connected with a word line WLL, the grids of all the unit transistors N3 are electrically connected with a word line WLR, the sources of all the unit transistors N4 are electrically connected with a bit line RBLB, the sources of all the unit transistors N5 are electrically connected with a bit line RBL, and each row shares the word lines WLL and WLR and the bit lines RBL and RBLB;

6. The circuit structure of claim 5, wherein during the data retention period of the 10T-SRAM cell, the write word line WLL, the write word line WLR, the read word line RWLL, and the read word line RWLR are all kept low, while N2, N3, N6, and N7 are all turned off.

7. The circuit structure of 10T-SRAM cell based memory Boolean logic operation and bidirectional BCAM of claim 5, wherein assuming that storage node Q of the 10T-SRAM cell is high and QB is low before a write operation, i.e. storing data is "1", when writing data "0", write operation word lines WLL and WLR are pulled to high selected cells, and simultaneously data "0" to be written is loaded on write bit lines BL and BLB.

8. The circuit structure of memory Boolean logic operation and bidirectional BCAM based on 10T-SRAM cell of claim 5, wherein storage node Q of the 10T-SRAM cell is assumed to be high and QB is assumed to be low before a read operation, i.e. storing data is "1"; at the beginning of the read operation, the read bit lines RBL and RBLB are precharged to high, the read word line RWLL or RWLR is pulled to high, and the NMOS transistor N6 or NMOS transistor N7 is turned on.

9. A circuit module based on the memory boolean logic operation and bidirectional BCAM of a 10T-SRAM cell, characterized in that it adopts the circuit structure based on the memory boolean logic operation and bidirectional BCAM of a 10T-SRAM cell according to any one of claims 5 to 8, and the circuit module based on the memory boolean logic operation and bidirectional BCAM of a 10T-SRAM cell comprises:

the 10T-SRAM unit is positioned in the same row, the grids of all the unit transistors N2 are electrically connected with a word line WLL, so that a first connecting end is led out, the grids of all the unit transistors N3 are electrically connected with a word line WLR, so that a second connecting end is led out, the sources of all the unit transistors N4 are electrically connected with a bit line RBLB, so that a third connecting end is led out, and the sources of all the unit transistors N5 are electrically connected with a bit line RBL, so that a fourth connecting end is led out; one of the first, second, third and fourth connection ends exists in each row;

10T-SRAM cells located in the same column, the sources of all cell transistors N2 are electrically connected to bit line BLB, thereby leading out a fifth connection terminal, the sources of all cell transistors N3 are electrically connected to bit line BL, thereby leading out a sixth connection terminal, the gates of all cell transistors N6 are electrically connected to word line RWLL, thereby leading out a seventh connection terminal, and the gates of all cell transistors N7 are electrically connected to word line RWLR, thereby leading out an eighth connection terminal; there is one of the fifth, sixth, seventh and eighth connection ends per column.

10. A circuit chip based on the memory boolean logic operation and bidirectional BCAM of a 10T-SRAM cell, characterized in that it is packaged by using the circuit structure based on the memory boolean logic operation and bidirectional BCAM of a 10T-SRAM cell according to any one of claims 5 to 8.