TWI264726B - Integrated content addressable memory architecture - Google Patents

Abstract

A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM) cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.

Description

1264726 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention provides an integrated circuitizable content addressable memory (CAM) structure, especially one based on a plurality of novel 10 - crystals The content of the content-addressable memory unit can be addressed to the memory structure. Prior Art Most memory elements access data at specific memory addresses. As a result, such processing methods often become a limiting factor in systems that rely on fast memory access. If a material can be accessed based on its content rather than its storage address, the time required to find a stored data in memory can be significantly reduced. The memory accessed by this processing method is called Content Addressable Memory (CAM). Briefly, the basic characteristics of content-addressable memory can be viewed as a standard storage system, such as a combination of random access memory (RAM) and a comparison device. Therefore, content addressable memory is a natural development of random access memory technology and provides an advantage over other memory search structures. Content addressable memory can be used to accelerate any area that requires fast search, such as databases, catalogs or graphics, graphics, sound recognition, or computer and communication design. In addition, content-addressable memory is also suitable for several other functions, including data processing of computer central processing unit (CPU), Ethernet address query, data compression, search engine, image recognition for encryption and decryption, and compression/decompression. Application and more.

1264726 V. INSTRUCTIONS (2) Conventional content addressable memory cells are arranged in a row and column using static random access memory (SRAM). The content addressable memory unit implemented using static random access memory is the fast access speed and static characteristics of the static random access memory unit. Based on the foregoing content of the addressable memory, and the function of the SRAM to read and store data, the content addressable memory is also used to search and compare the stored data for confirming the memory. Whether the data matches a set of comparative data (search materials). When the comparison data (search data) matches the data already stored in the memory, a matching result is displayed; when the comparison data (search data) does not match the data already stored in the memory, an unqualified result is displayed. . Referring to Figure 1, Figure 1 is a schematic diagram of a conventional content addressable memory structure arranged in a plurality of memory columns 1 Ο A 〜 1 Ο K. As shown in FIG. 1, each memory bank (1 Ο A~1 Ο K ) is coupled to a corresponding matching line 1 2 (1 2 A~1 2 K ), and the corresponding matching line 1 2 can be used. Shows whether the comparison data matches the data already stored in the memory column. In this example, the comparison data and the pre-stored data are all N-digit data. Taking the memory column 1 Ο A as an example, when the N-bit comparison data is identical to the N-bit data stored in the memory column 1 Ο A of the content addressable memory structure 10, the corresponding matching line is output. A logic high level. Conversely, when any data bit of the N-bit comparison data is different from the corresponding N-bit data stored in the memory column 1 Ο A of the content-addressable memory structure 10, the corresponding matching line is converted to The output is a low logic level.

1264726 V. INSTRUCTIONS (3:) Referring to FIG. 1, the memory column of the addressable memory structure 10 used as the content of the data comparison includes a mask unit 1 5 (1 5 A~1 5 K ) Coupled to a plurality of related content addressable memory cells. The mask unit 1 5 (1 5 A to 1 5 K) can turn on or off the alignment of the content addressable memory cells. For example, the mask unit 15A in the memory column 10A connects the related content addressable memory units 1 〇A ( 2 ) and 1 0 A ( 3 ), and the content addressable memory Units 1 0 A ( 2 ) and 1 0 A ( 3 ) can be masked by mask unit 15 5 A. The example implemented by this method also appears in the US Patent 6,1 5 4,3 8 4 "Ternary content addressable memory cell", and the U.S. Patent 6,108,22, filed by Voelkel. No. ''Content addressable memory having binary and ternary modes of operation'. In general, when the mask unit is set to operate, the content-addressable memory unit will be masked in the comparison operation; and when the mask unit is set to be inactive, it will not Masked in the comparison job. Each memory bank (1 0 A~1 0 K ) contains a plurality of (binary) content addressable memory cells. For example, the memory bank 10 A contains N content addressable memory cells 10A(1) to 10A(N). Each content addressable memory unit can store a digital data value having two information states, a logical state and a logical zero. As shown in FIG. 1, the N bit data stored in each memory column (10 A~1 0 K ) is stored in the corresponding n (binary) content addressable memory cells. It consists of N digit data values. 2 is a schematic diagram of one of the conventional content addressable memory cells 20. content

1264726 V. DESCRIPTION OF THE INVENTION (4) The addressable memory unit 20 (using binary static random access memory) is used in a memory bank of the content addressable memory structure 10 of Fig. 1. Taking the memory column 1 Ο A in FIG. 1 as an example, the content addressable memory unit 20 in FIG. 2 can be used for each content addressable memory unit 10 A in the memory column 1 Ο A ( 1) ~1 0 A ( N ). The content addressable memory unit 20 includes a static random access memory unit 26, a comparator module 2 4, and a matching line 2 2 . The comparator module 24 can be used to compare digital data values and an input data value stored in the static random access memory unit 26. When the input data value is the same as the digital data value stored in the SRAM cell 26, the matching line 2 2 will remain at the pre-charged high level. When the input data value is opposite to the digital data value stored in the SRAM cell 26, the matching line 2 2 is pulled down to a low level. The content addressable memory unit 20 further includes a word line 2 8 , a first bit line 3 0 and a second bit line 3 2 , wherein the static random access memory unit 26 and the comparator module 2 4 share the first and second bit lines 30, 32. Referring again to FIG. 1 and FIG. 2, if the addressable memory unit 20 is used in the memory column 10 A and connected to the mask unit 1 5 A as shown in FIG. 1, the content addressable memory unit 20 becomes a maskable content addressable memory unit 20 that can effectively store three information states, which are logical 壹, logical zero, and ignore comparison job status. The content of the maskable content addressable memory unit allows the user to follow the mask bits to perform the alignment. Figure 3 is a detailed implementation of one of the conventional content addressable memory units in Figure 2.

1264726 V. Illustration of the invention (: 5). Figure 3 details the implementation of the content addressable memory unit 20. The content addressable memory unit 20 is a 10-O-crystal content addressable memory unit, wherein the SRAM cell 26 is a 6-transistor SRAM cell, and the comparator mode is Group 2 4 is a 4-transistor comparator module. In practical applications, the matching line 2 2 is pre-charged to a preset high level before comparing the input data value with the digital data value stored in the 6-transparent SRAM cell 26. . However, since the 6-transistor SRAM cell 26 and the 4-transistor comparator module 24 share the same first and second bit lines 10, 3 2, the precharge potential of the line 2 2 is assigned. It may be disturbed by the initial state of the 6-transistor SRAM cell 26 or any other point in the 4-transistor comparator module 24 (e.g., the NI point). In addition, the pre-charging potential of the matching line 2 2 is pulled down by the charge distribution between the matching line 2 2 and the internal contact (for example, the NI point), and the voltage drop of the matching line 2 2 depends on the matching line. 2 2 and the capacitance value between the internal contacts. The results of all of the above-described prior art techniques will be detrimental to the use of content addressable memory in low power operations. In addition, in order to conform to the trend of integrating multiple functions into one electronic device, it is desirable to maintain the powerful function of the content addressable memory structure as much as possible without increasing the size of each unit. Therefore, a content retaining the characteristics of using static random access memory while having high efficiency and sufficient selectivity, and having a better protection mechanism than conventional techniques, greater flexibility of alignment, and faster operation speed can be addressed. Memory unit, will become relevant

1264726 V. INSTRUCTION DESCRIPTION (6) The main needs of the industry. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a 1 〇-transistor content addressable memory unit and an integrated circuitizable content addressable memory structure, Solving the problem of the above-mentioned conventional signal interference, and providing an integrated function to solve the aforementioned conventional problems. According to the patent application scope of the present invention, a 10-crystal content addressable memory unit and an integrated circuitized content are disclosed. Addressing memory structure. In the implementation process, according to the 10-crystal content of the present invention, the memory unit can be addressed, and a pre-charge potential of a matching line of the addressable memory unit combined with the 10 - transistor content is not 1 〇. - The contents of the transistor can interfere with the initial state of other contacts in the address memory unit. In addition, the overall weight of each memory column (1 Ο A~ 1 0K) in the memory structure can be addressed in the integrated circuit. A function is provided to provide a valid bit unit and a protection bit unit to fully ensure the correctness of the comparison operation. The known masking operation, using the 10 - transistor content addressable memory cell, the integrated circuitizable addressable memory structure can provide an integrated and diverse function to fully exploit the content addressable memory characteristics. The object is to provide a 10 - transistor content addressable memory unit 5 comprising a word line first bit line and a second bit

Page 10 1264726 V. Invention Description (τ) Line, a 6-Opto SRAM cell, a matching line, a third bit line, a fourth bit line, and a 4-cell Comparator module. The 6-epoxy SRAM cell is coupled to the word line, the first bit line, and the second bit line are used to store a digital data value; the matching line is used to provide a The 4-channel transistor comparator module is coupled to the symmetrical line, the third bit line, the fourth bit line, and the 6-transistor SRAM cell for comparison The digital data value stored in the 6-transistor SRAM cell and an input data value provided by the third bit line or the fourth bit line. Another object of the present invention is to provide an integrated circuit addressable addressable memory comprising a plurality of matching lines, a plurality of memory columns, a significant bit unit, and a protection bit unit. The plurality of matching lines are used to provide a plurality of corresponding matching signals; the plurality of memory columns are coupled to the corresponding matching lines, and the corresponding matching lines are coupled to the plurality of content addressable memory units; The effective bit cell is coupled to the matching line for storing a valid bit, wherein the valid bit is used to indicate whether the memory column of the integrated circuitizable addressable memory contains valid data; the protection bit The meta cell is coupled to the effective bit cell for setting the effective bit to zero when the protection bit cell is set to be inactive, and maintaining the valid bit when the protection bit cell is set to be active constant. Another object of the present invention is to provide an integrated circuitizable content addressable

1264726 V. INSTRUCTIONS (8) Memory structure, which includes a plurality of matching lines and a plurality of memory columns. Each memory bank includes a plurality of 10 - transistor content addressable memory cells, a valid bit cell, a guard bit cell, and at least one mask cell, each of the 10 - transistor content addressable memories The body unit includes a word line, a first bit line, a second bit line, a 6-transistor static random access memory unit, a first input line, a second input line, and a 4- Transistor comparator module. Wherein a plurality of matching lines are used to provide a plurality of corresponding matching signals; a plurality of memory columns each coupled to a corresponding matching line; a plurality of 10-0-crystal content addressable memory unit couplings Connecting to the corresponding matching line; the first bit line and the second bit line are complementary bit line pairs; the 6-transistor SRAM cell is coupled to the word line, the first a bit line and the second bit line are used to store a digital data value; the first input line and the second input line are complementary input line pairs; the 4-transistor comparator module is coupled to the a matching line, the first input line, the second input line, and the 6-transistor SRAM cell for comparing digital data values stored in a 6-transistor SRAM cell And an input data value provided by the first input line or the second input line; the effective bit unit is configured to store a valid bit, the valid bit is used to indicate that the integrated circuitized content is addressable Whether the memory column of the memory contains valid data, in which The data of the memory column of the addressable memory structure is composed of the digital data value stored in the 6-transistor SRAM cell; the protection bit cell is consumed To the effective bit cell, when the protection bit cell is used

Page 12 1264726 V. Invention Description (9:) When set to not operate, the error is set to zero by an overall effective bit reset step, and when the protected bit element is set to be active, The effective bit remains unchanged by an overall effective bit resetting step; the mask unit is coupled to a plurality of selected one-turn crystal content addressable memory cells for setting the mask unit to be When the operation is performed, the selected 10 - transistor content addressable memory unit is masked, and the selected 10 - transistor content addressable memory is not selected when the mask unit is set to be inactive The body unit is covered. Embodiment FIG. 4 is a schematic diagram of a 10-O-crystal content addressable memory cell 40 of the present invention. The 10 - transistor content addressable memory 40 includes a word line 4 8 , a first bit line 5 0 , a second bit line 5 2 , and a 6 - transistor static random access memory The body unit 4 6 is coupled to the word line 4 8 , the first bit line 5 0 , and the second bit line 5 2 , and is used for the 6 - transistor SRAM cell 4 6 Store a digital data value. The first bit line 50 and the second bit line 5 2 are first complementary bit line pairs. The 6-transistor SRAM cell 46 includes two PMOS type load transistors P1 and P2 each performing a load element function, and two NMOS type drive transistors N 1 and N2 each performing a driver function, and Two NMOS type access transistors N3 and N4 for accessing the data of the 6-transistor SRAM cell 46. Taking a digital data value π 1 ’' as an example, in the data storage process, the first bit line 5 0 is lost.

Page 13 1264726 V. INSTRUCTION DESCRIPTION no) At a higher potential, the second bit line 5 2 is input to a lower potential. Therefore, 'the load transistor P1 and the drive transistor N 2 are turned on' and the load transistor P2 and the drive transistor N1 are turned off. As a result, part of the current in the BF point flows into the power supply terminal via the turned-on drive transistor N 2 . V ss, but the drive transistor N 1 whose current at the BT point is turned off is blocked from the power supply terminal V ss . Therefore, the BT point is at a higher potential state and the BF point is at a lower potential state. Finally, the word line 48 is turned off so that the BT and BF points remain in the same state, and the digital data values are stored at the BT and BF points (the BT point and the BF point can be regarded as a pair of complementary points). 1 0 - transistor content addressable memory 40 further includes a matching line 4 2 for providing a matching signal, a third bit line 5 4, a fourth bit line 5 6 , and a 4 - a transistor comparator module 44. The third bit line 5 4 having the DB point and the fourth bit line 56 having the D point are the second complementary bit line pair. In the present embodiment, the 4-transistor comparator module 44 forms a mutually exclusive or (XN0R) circuit for performing a comparison operation, and the 4-transistor comparator module 44 includes a pair of first NM0S type electrical The crystals N5 and N6, and a pair of second NMOS type transistors N7 and N8, and each pair of NM0S type transistors are coupled between the matching line 42 and the ground GND. The 4-transistor comparator module 44 is coupled to the matching line 4 2, the third bit line 5 4 , the fourth bit line 5 6 , and the 6 - transistor static random access memory unit 4 6 The digital data value stored in the 6-transistor SRAM cell 46 is compared with an input data value provided by the third bit line 454 or the fourth bit line 5.6. The matching signal provided by the matching line 4 2 is stored in the 6-electrode static

Page 14 1264726 V. Description of the Invention (The digital data value in the in-state random access memory unit 46 is the same as the input data value. The input data values are compared and stored in the 6-transparent static random access memory. When pre-charging to a pair of jobs, if the memory unit is determined to be at the low potential south potential V cx. The static random access is the potential of the BT point before the digital data value in the preset souther electric unit 46 The line 42 will have a preset high potential V cc. As shown in Fig. 4, when the input data value is the same as the digital data value stored in the 6-electrode static cancer random memory, for example, BT point and D When the point status (BT = D = 0), the matching signal remains at the opposite of the preset. If the input data value is opposite to the digital data value stored in the 6-plasma memory unit 46, the status is not equal. At the potential state of point D, the matching signal position Vc is pulled down to a low potential because of the second complementary bit line pair coupled to the 4-transistor comparator module 44 (third bit line 5 4 and fourth bit lines 5 6 ) and coupled to 6-transistor static random access memory The first complementary bit line pair (the first bit line 50 and the second bit line 5 2 ) of the unit 46 are separated, and each is connected to the third bit line 5 4 and the fourth bit line 5 The N Μ 0 S type transistors N 7 and N 8 of 6 are connected to the ground GND, so the precharge potential of the matching line 42 is not affected by the 6-transistor SRAM 46 or 4- The initial state of any other point in the crystal comparator module 44 is disturbed. The voltage drop on the nominal line 42 and any mismatched signal that can be erroneous can also be avoided by this method. In addition, after using the software simulation confirmation Separating the bit lines can reduce the bit line load of the 10 - transistor content addressable memory 40 for faster performance.

Page 15 1264726 V. INSTRUCTION DESCRIPTION (12) FIG. 5 is a schematic diagram of an integrated addressable memory bank 60 in accordance with a first preferred embodiment of the present invention. The integrated circuitizable addressable memory bank 60 includes a matching line 6 for providing a corresponding matching signal. 2. A plurality of contents addressable memory unit 7 0 (7 0 (1)~7 0 (N )), a valid bit unit 64, and a protection bit unit 6 8 每一 Figure 5 Each of the addressable memory cells 70 can use the 10 - transistor content addressable memory in Figure 4 Unit 40 or other types of content can be addressed by addressing the memory unit. If the 10 - transistor content addressable memory 40 unit in FIG. 4 is applied to the content addressable memory unit 70 of FIG. 5, the integrated circuitized content of FIG. 5 can address the memory column 6 0. There will be all of the aforementioned advantages of the 10 - transistor content addressable memory 40 unit of the present invention, such as low bit line load and prevention of interference. The main feature of this embodiment is that the effective bit unit 64 is combined with the protection bit unit 68. The valid bit cell 64 is used to store a valid bit that shows whether the integrated circuitizable addressable memory bank 60 contains valid data. The protection bit cell unit 6 8 is coupled to the effective bit cell unit 6 4 for setting the effective bit element to zero when the protection bit cell unit 6 8 is set to be inactive, and when the protection bit cell unit 6 8 is set to When active, the valid bit is set to remain unchanged. In the integrated circuit addressable memory bank 60, when the valid bit is logic π 0 f', the memory column is displayed to contain invalid data. Conversely, when the effective bit is logic π 1π, it is displayed that the memory column contains valid data. In addition, when the effective bit is logic π 1π, a comparison operation is allowed, which is used to compare the data and store it in the integrated circuit.

Page 16 1264726 V. INSTRUCTIONS (13) The information in the memory column of the addressable memory. Similar to the prior art of FIG. 1, the comparison data and the previously stored data in this embodiment are all N-digit data. Before the comparison operation, the matching signal of the matching line 6 2 is pre-charged to A preset high potential. When the (N-bit) comparison data is identical to the (N-bit) data stored in the memory column 60 of the content-programmable content addressable memory, the corresponding matching signal will remain at a preset high. Potential. When any data bit of the (N-bit) comparison data is opposite to the data bit of the (N-bit) data stored in the memory column 60 of the content-programmable content addressable memory, the corresponding data bit The signal will change from a preset high level to a low level. Figure 6 is a schematic diagram of another embodiment of Figure 5 showing the architecture of a combination of protection bit unit 68 and effective bit unit 64. The effective bit cell 64 is composed of a typical 6-transistor SRAM cell 6 6 (shown in FIG. 3) and a valid reset module 70 coupled to the protection bit cell 6 8 . . The protection bit unit 6 8 is also composed of a 6-transistor static random access memory unit 7 6 and a protection reset input module 7 2 for receiving an overall signal GS2. Therefore, the protection bit unit 6 8 Can be set to be inactive by the overall signal GS2. As shown in FIG. 6, in the case of a storage bit on a PT point of the protection bit unit 68, when a high level overall signal GS2 is input to the protection reset input module 7 2, the storage can be performed. The bit population is reset to logic "0''. Similarly, when the protection bit cell 68 is set to be inactive (the storage bit at the PT point is 'f Ο π, the storage bit on the PF point) For π 1π ), a high level overall signal GS 1 is input to the effective reset module 70, and the effective bits stored at a VT point of the effective bit unit 64 can be reset to logic “Ο π”. If

Page 17 1264726 V. INSTRUCTIONS (15) The NMOS type transistor N10 will be turned off, so the effective bit cell unit 64 will maintain its previous state after the total weight setting. Figure 8 is a schematic illustration of a second embodiment of an integrated addressable memory bank 80 of the integrated circuit of the present invention. The main difference between this embodiment and the aforementioned embodiment of Fig. 5 is the arrangement of the mask unit 85. The integrated circuitizable addressable memory bank 80 includes a matching line 8 for providing a corresponding matching signal. 2. A plurality of content addressable memory cells 9 0 (9 0 (1)~9 0 (N )), a valid bit unit 8 4, a protection bit unit 8 8 , and a mask unit 8 5 . The mask unit 85 is connected to a plurality of content addressable memory units for masking the related content addressable memory units when the mask unit 85 is set to be activated, and When the mask unit 85 is set to be inactive, the related content addressable memory cells are not masked. In the present embodiment, two content addressable memory cells 90 (1) and 90 (2) are coupled to the mask unit 85. Please note that in this embodiment, the number of addressable memory cells connected to the mask unit 85 is not limited. The related content addressable memory cells 9 0 ( 1 ) and 90 ( 2 ) in this embodiment can be regarded as a maskable content addressable memory unit, and effectively store three kinds of information states, logic 壹, logic zero And ignore the comparison job status. Referring to FIG. 9, an embodiment of the mask unit 85 of FIG. 8 and the associated content addressable memory unit 90 (90 (1) or 9 0 (2)) connected to the mask unit 85 is shown. . When the related content addressable memory unit 90 is a 10-0-crystal content addressable memory unit in the present invention (as shown in FIG. 3), the mask unit 85 is composed of one

Page 19 1264726 V. INSTRUCTION DESCRIPTION (16) 6 - A transistor static random access memory cell 8 6 wherein the 10 - transistor content addressable memory cell contains a 6-transistor static random access memory The body unit 96 and the 4-transistor comparator module 94, and the 6-transistor SRAM unit 86 and a 4-electrode coupled to the associated content addressable memory unit 90 The NMOS type transistor N11 of the crystal comparator module 94 is combined. When the mask unit 85 is fed a logic π 1π (the mask unit 85 is set to operate, the storage bit of the ΜT point is logic π 1 '', and the storage bit of the MF point is logic π (Γ) The NMOS type transistor Ν 1 1 is turned off. The matching line 8 2 of the corresponding content addressable memory unit 90 (the maskable content addressable memory unit) is always maintained at a predetermined high level. This is called ignoring the comparison job status, and the related content can address the memory unit 90 - it will be masked. When the mask unit 85 is sent into a logic '' (Γ (mask unit 8 5 When it is set to be inactive, the storage bit of the defect is logic π 0 π and the storage bit of the MF point is logic π 1π ), the NMOS type transistor Nl 1 acts as a virtual ground. The correlation in Figure 8 and Figure 9 The content addressable memory unit 90 performs general content addressable memory related functions. Again, the number of masking units 85 and related content addressable memory unit 90 (connected to the mask unit 8 5 ) is not limited. Figure 10 is an integrated circuitizable content addressable memory The third embodiment of 80 continues the characteristics of the embodiment of Fig. 8. In the present embodiment, the number of mask units 85 is set to two, so the integrated circuitizable content addressable memory column 8 0 includes two mask units 8 5 ( 1 ) and 8 5 ( 2 ), and each mask unit 85 is coupled to two content addressable memory units for addressing the two contents. Memory unit is covered

Page 20 1264726 V. INSTRUCTIONS (14) The protector unit 6 8 stores “ Γ (the storage bit on the PF point is "0 "), an NMOS type transistor of the active reset module 70 N9 will be turned off, so the effective bit cell 64 will maintain its previous state after the overall reset. The dual protection design previously described (combining the effective bit cell 6 4 with the protection bit cell 6 8) and the overall weight A mechanism can be used to fully ensure the correctness of the operation and make the comparison work more flexible. Figure 7 is a schematic diagram of another embodiment. This embodiment combines the effective bit unit 64 and the protection bit unit 6 8 The reference numerals of all the components in the seventh are the same as those in Fig. 6, and the same operation is performed. The effective bit cell 6 4 is also coupled by a 6-transistor static random access memory cell 6 6 and a coupled to the protection bit cell 6 8 The effective reset module 70 is composed of a 6-transistor static random access memory unit 7 6 and a protection reset input module 7 2 for receiving a total Signal GS 2, so protect the bit unit 6 8 can be set to be inactive by the overall signal GS 2, as shown in the embodiment of Figure 6. According to the unique circuit design of the present embodiment, the storage bit at a PT point of the protection bit unit 68 is input. When a high level overall signal GS2 to the protection reset input module 72, the storage bit element can be reset to logic π 0 π. Further, when the protection bit unit 6 8 is set to be inactive (ΡΤ The storage bit at the point is “0 π”, and inputting a low level overall signal GS 1 to the effective reset module 70 can weight the effective bit stored at a VT point of the effective bit unit 64. Set to logic ''0''. As in the foregoing embodiment of FIG. 6, if the protection bit unit 6 8 stores π 1 n (the storage bit on the PF point is “(Γ), one of the effective reset modules 7 0

Page 18 1264726 V. Description of the Invention (17) (Mask unit 8 5 ( 1 ) is coupled to two content addressable memory cells 9 0 (: 1 ) and 9 0 ( 2 ), mask unit 8 5 ( 2) coupled to two content addressable memory cells 9 0 ( 3 ) and 9 0 ( 4 )). However, an overall signal G S can generally set the two mask units 85(1) and 8 5 ( 2 ) to be inactive. Broadly speaking, according to the embodiments of FIG. 5 to FIG. 10, in an integrated circuit addressable addressable memory column, combining a valid bit cell, a protection bit cell, and at least one mask unit may be Improve safety and increase flexibility in use. The following embodiment is a novel integrated circuitizable content addressable memory structure 100 that continues the characteristics of the foregoing embodiments of Figures 4 through 10, and is composed of a plurality of novel 10 - transistor content addressable memories. Forming, the 10-O crystal content addressable memory unit comprises a valid bit unit, a protection bit unit, and at least one mask unit (the at least one mask unit is coupled to each memory) The column consists of a plurality of related 10 - transistor content addressable memory cells. Referring to Fig. 11, there is shown a schematic diagram of a content-addressable memory structure 100 of the integrated circuit of the present invention. The contents of the integrated circuit can be addressed to the memory structure 1 0 0 including the complex memory column 1 Ο Ο A~1 Ο Ο K and the corresponding complex memory column 1 Ο Ο A~1 Ο 的 K multiple number matching line 1 0 2 ( 1 0 2 A~1 0 2 K ), used to provide a plurality of corresponding matching signals. Each of the memory columns coupled to the corresponding matching line 1 0 2 includes a plurality of 10 - transistor content addressable memory cells 1 1 0 in FIG. 4 coupled to the corresponding matching line 1 0 2 a valid bit cell 1 0 4 (1 0 4 A~1 0 4 K ), a protection bit cell 1 0 8 (1 0 8 A~1 0 8 K ), and at least one mask list

Page 21 1264726 V. Invention Description (18) Yuan 1 0 5 (1 0 5 A~1 0 5 K ) 详细 Detailed description of memory column 1 〇〇A: mask unit 1 0 5 A coupled to memory Two related 1 〇-transistor contents in the body array 1 0 〇A can address the memory cells 1 1 0 A ( 2 ) and 1 1 〇A ( 3 ) for setting the mask unit 1 0 5 A When the action is made, the associated 1 〇-transistor content addressable memory cells 1 1 0 A ( 2 ) and 1 1 0 A ( 3 ) are masked. In addition, the mask unit 1 0 5 A in the memory column 1 Ο Ο A is connected to the associated 10 - transistor content addressable memory unit in a plurality of other memory columns (such as 1 0 in FIG. 11) - The transistor contents address the memory cells 11 Ο B ( 2 ) and 11 Ο B (3)). The valid bit cell 1〇4 (104Α~104K) in each memory column is used to store whether the data stored in the memory column of the integrated addressable memory structure 100 of the integrated circuit is valid. The valid bit, wherein the data stored in the memory column of the integrated circuit addressable memory structure is stored in the 1 0-transistor content addressable memory unit 1 1 0 - The crystal static random access memory unit 1 〇6 is composed of digital data values. In each memory column of the integrated circuit-addressable memory structure 100, the protection bit cell 1 0 8 (1 0 8^108]() is coupled to the effective bit cell 1 0 4 ( 1 0 4A~104K), used to protect the bit unit 1 when the protection bit number is 1 〇8 (1 〇8 A~1 0 8 K) is set to be inactive. 〇8 (108Α~108K) is set to be active 'set the effective bit to remain unchanged. Finally, note that in the integrated circuitizable addressable memory structure 1 〇〇 of the present invention, a plurality of masks The single 105 (1〇5Α~105K), the plurality of valid bit units 1〇4 (1〇4Α~104K), and the plurality of protection bit units 1 0 8 (1 0 8A~108K) can be plural The signal GS is reset overall.

Page 22 1264726 V. INSTRUCTION DESCRIPTION (19) In accordance with the present invention, a novel 1 电-transistor content addressable memory unit and an integrated circuitizable content addressable memory structure are disclosed. The novel 10-O crystal content addressable memory cell prevents interference and charge sharing on the nominal line and avoids low bit line loading to improve fast and low power performance. Further, the present invention provides a valid bit cell, a protection bit cell, and a mask unit having a general reset function to sufficiently ensure correctness and flexibility in the alignment work. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made to the patent scope of the present invention should fall within the scope of the present invention.

Page 23 1264726 Schematic description of the diagram Early description between the diagrams Figure 1 is a schematic diagram of a conventional content-addressable memory structure. FIG. 2 is a schematic diagram of a conventional content addressable memory unit. Figure 3 is a schematic illustration of a detailed description of a conventional content addressable memory unit. Figure 4 is a schematic illustration of a 1-turn-transistor content addressable memory cell of the present invention. Figure 5 is a schematic diagram of a first embodiment of an integrated circuit addressable memory bank according to the present invention. Figure 6 is a schematic diagram of a valid bit cell of the present invention. Figure 7 is a schematic diagram of another effective bit cell of the present invention. Figure 8 is a schematic diagram of a second embodiment of an integrablely addressable addressable memory bank of the present invention. Figure 9 is a schematic illustration of the mask unit of Figure 8 and corresponding content addressable memory cells connected to the mask unit. Figure 10 is a schematic diagram of a second embodiment of an addressable memory array of an integrated circuitized circuit of the present invention. Figure 11 is a schematic diagram showing the structure of an addressable memory of an integrated circuitized circuit of the present invention. Symbol description of the schema 10, 1 0 0 content addressable memory structure

Page 24 1264726 Schematic description 2 0, 4 0, 6 6 , 7 0, 7 6 , 9 0, i 1 0 Content addressable memory unit 1 Ο A 〜1 Ο K, 6 0, 8 0, 1 Ο Ο A 〜1 Ο Ο K Memory column 1 2 A ~1 2 K, 2 2, 4 2, 6 2, 8 2, 1 0 2 Matching line 24 > 44, 94 Comparator module 26 ^ 46 ^ 86 ^ 96 SRAM unit 28 > 48 word line 30 ^ 32, 50 ^ 5 2, 5 4, 5 6 bit line 64, 84, 104 Effective bit unit 68 ^ 88, 108 protection bit Unit 7 2 protection reset input module 85, 105 mask unit

Page 25

Claims (1)

1264726 Case No. 2 is the scope of application for patents 0~T) Content can be addressed to CAM) Unit 3 is package 1 ·, a type of 10 - transistor (1 0 - tr a. ns 1 st 〇r memory) Content addressable memor contains: a word line; a first bit line; a second bit line of the grave; a 6-transistor (6-T) static random access memory (static random access memory, SRAM) unit,; ^ $ The ή ίΦ A:. character line, the first bit line and the second bit line, in digital data values; for storing • matching line 5 for providing a match The signal is called the third bit line; έ the fourth original line of the original test η; and the 4-transistor (4-transistor, & 1 i J compares the cry according to the comparator modu 1 e), including - from the emperor: Supply, and: 'a third transistor and a fourth electric brother, a ^ electric crystal. body' - second electric crystal a the third transistor is not connected to the matching name = version f - electricity a gate of the crystal and the third transistor is coupled to the first transistor and the drain of the transistor and the first transistor=aa body SRAM cell The gate of the second crystal is electrically connected to the third bit line, the second electrode is grounded, the drain of the fourth transistor is electrically connected to the source of the second transistor, and the fourth The gate of the transistor is connected to the source of the fourth transistor of the three transistors, and the source of the fourth transistor is grounded. The f = bit line is electrically connected, and the comparison is stored in the 6-transistor SRAM. The module is used to = '...the number of data values in the '... 1264726 Case No. 921261Π Year. Month Day Amendment 6. The third-digit line of the patent application scope i or the input data value provided by the fourth-order line c 丨2 β as in the patent scope 1 item 1 - transistor The content addressable memory I body unit, wherein when the input data value is the same as the digital data value stored in the 6_transistor SRAM unit, the matching signal stays at a pre-set south level, when When the input metric value is opposite to the digital data value stored in the 6-transistor SRAM I unit, the registration signal changes to a low | level. I 丨3. The 0-transistor content addressable memory unit of claim 2, further comprising a pre-charging circuit coupled to the matching line for comparing the input data value and storing Before the digital data value in the 6-transistor SRAM cell, the matching signal of the matching line is pre-charged to the preset high level. 4 - 10 - The transistor content addressable memory unit according to claim 1 of the patent scope, wherein the first bit line and the second bit line are a first complementary bit line pair, the third bit The meta line and the fourth bit line are a second complementary bit line pair. 5) The 0-transistor content addressable memory unit of claim 1 wherein the 4-transistor comparator module is an exclusive NOR circuit comprising a first pair And a second pair of transistors, wherein each pair of electro-crystal systems is connected to the distribution line and a ground terminal Page 27 1264726 _ Case No. 92126117 VI. Scope of application for patents. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; When the cover unit is confirmed to be executed, the registration signal is maintained at a high level and the address-addressable memory is masked. 7 - an integrated circuitizable content addressable memory (CAM), comprising: a plurality of matching lines for providing a plurality of corresponding matching signals; and a plurality of columns, each column coupled to a corresponding matching line The method includes: a plurality of content addressable memory units coupled to the matching line; a valid bit unit for storing a valid bit, the effective bit indicating that the integrated circuitized content is addressable Whether the column of the memory contains a valid tributary, and a protection bit unit coupled to the effective bit cell for setting the effective bit to zero when the protection bit cell is not confirmed to be executed, and when The guard bit unit is held unchanged when it is confirmed to be executed. 8. The content of the integrated circuitizable memory of claim 7 of claim patent, wherein in each column of the integrated circuit addressable memory, when the effective bit is zero, the display is displayed The column contains invalid data; when the valid bit is 壹, the column is displayed with valid data. 1264726 Case No. 92126117 Revised on the day of the month............ VI. Patent application scope 9 · The content of the circuitized circuit of item 8 of the patent application scope can be addressed to the memory, where The integrated circuit can be located in each column of the memory. When the effective bit is 壹, a comparison operation is allowed to compare the data with the I and the content of the circuitized data stored in the integrated circuit. : Information on the list of memory. I |10· The content of the circuitized circuit of item 9 of the patent application scope can address the I memory, wherein in the column of each of the contents of the integrated circuit addressable memory, when the comparison data is stored in The integrated circuit can be: when the data of the address memory is the same, the corresponding matching signal remains at a predetermined high level. 111. The content of the circuitized circuit of item 9 of the patent application scope can be addressed! * Memory, in which each of the comparison data is in each column of the addressable memory of the integrated circuitized content When the data bit is opposite to a corresponding data bit of the data stored in the column of the integrated circuitizable content addressable memory, the corresponding matching signal is changed from the preset high level to a low level. 1212. The content of the circuitized circuit of claim 9 may address the memory, wherein each of the content addressable memory cells includes one in each column of the integrated circuit addressable memory. 6-Crystal Static Random Access Memory (SRAM) cell and a 4-transistor comparator modulo j ° 1264726 Case No. 9212611 Revised 7th, 7th, and the scope of patent application|ΐ3· The content of the circuitized circuit of the 12th item of the patent application can address the memory, where the content of the integrated circuit can address the memory. In each column, each data bit of the data stored in the column of the integrated circuit addressable memory is stored in each 6-transistor SRAM | cell. 1 4 - The addressable memory of the integrated circuit circuit of claim 12, wherein the 4-channel transistor comparator module is used to perform each of the integrated circuitizable addressable memory blocks Comparison of homework. 1 5 · The content of the integrated circuit can be addressed as described in item 7 of the patent application scope. In each column of the content addressable memory of the integrated circuit, the protection bit unit can be set by an overall signal. The execution was not confirmed. 1 6 · The content of the integrated circuit can be addressed as described in Item 15 of the patent application, wherein in the column of the integrated circuit addressable memory, when the associated protection bit cell When the execution is not confirmed, the valid bit of the valid bit cell can be reset to zero by the overall signal, and when the associated protection bit cell confirms execution, the effective bit of the valid bit cell is in an overall reset step. Will remain unchanged after that. |ΐ7·The content of the circuitized circuit of item 7 of the patent application scope can be addressed. Page 30 1264726 Case No. 921261Π Π 、 、 申请 申请 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 a memory unit configured to address the plurality of selected contents when the mask is i-line, and to not address the content-addressable memory unit mask when the mask unit is not confirmed to be executed stand up. 1 8 · The integrated circuit of the patent application category 17th, wherein the mask unit can be set by an overall signal in each column of the integrated circuit. 1 9. An integrated circuitizable content addressable memory includes: a plurality of matching lines for providing a plurality of corresponding matching plural columns, each column coupled to a corresponding matching line, the plurality of 1 0 - The transistor content can address the memory unit matching line, each 10 - transistor content can address the memory f word line; a first bit line; a second bit line, wherein the first bit line And the sixth complementary bit line pair; a 6-transistor static random access memory (SRAM) single word line, the first bit line, and each of the second bit line modified address memory are selected The unit is confirmed that the memory unit masks the plurality of selected contents to determine the fixed memory (CAM) structure of the address memory, the packet signal; and includes: the connection to the corresponding I unit includes: two bits The line is one dollar, coupled to the one for storing a number 1264726 Case No. 92126117 Revised on the sixth day, the patented range i-bit data value; i a first input line; a second input line, wherein the first input line and the second input line|the complementary input line pair; And a 1-4-transistor comparator module coupled to the symmetrical line 'the first i-line, the second input line, and the 6-transistor SRAM cell for storing in the 6-electrode a digital data value in the SRAM unit and an input data value provided by the I | an input line or the second input line; i a valid bit unit for storing a valid bit: the valid bit: The integrated circuit can be used to address whether the data of the memory structure is valid, and the data stored in the column of the integrated circuit address memory structure is stored in the 6-electrode unit. The digital data value is grouped into a protection bit unit coupled to the effective bit unit for setting the effective bit to zero by an overall effective bit when the guard unit is not confirmed to perform. And when the protection bit unit confirms the execution, borrow An overall effective bit resetting step maintains the effective bit; and at least one mask unit coupled to the plurality of selected 10-transistor r; the addressed memory unit for confirming that the mask unit is The selected 10 - transistor content addressable memory cell mask is executed during execution. ^ When the mask unit is not confirmed to be executed, the selected 10 content addressable memory unit is not masked. For an input comparison, the first element shows that the SRAM can be set to SRAM. The save step is not 3, and the ^ can be 匕 crystal 1264726 Case No. 92126117 J J. Amendment: VI. Patent application scope 20. The content of the circuitization of the 19th item of the patent application scope can be determined as: address memory structure, in which the content of the integrated circuit can be addressed. In each column of the i-body structure, when the effective bit is zero, the data stored in the column of the addressable memory structure of the circuitized body of the product I is invalid; 1 when the valid bit is 壹, the storage The data of the integrated circuit can be determined to be valid for the data of the memory structure. II | |21· The content of the circuitized circuit of item 20 of the patent application scope can be defined as an i-memory memory structure in which each of the columns of the integrated circuitizable addressable memory|body structure is valid. When the bit is zero, a comparison operation performed by the 4-transistor comparator module is allowed, and the comparison operation compares a comparison data with a content-addressable memory structure stored in the integrated circuit The information in this column. 2. 2 2. The content of the integrated circuit can be addressed as described in claim 21, wherein the comparison data consists of input data values provided by the first input line or the second input line. 2 3 · The content of the integrated circuit can be determined as in the case of the circuitized circuit of the second paragraph of the patent application, in which the comparison data is in each column of the integrated circuitizable addressable memory structure. When the data stored in the column of the content-addressable memory structure of the integrated circuit is the same, the corresponding matching signal is maintained at a preset high level; when any data bit of the comparison data is stored and stored The addressable memory of the integrated circuit Page 33 1264726 ; Case No. y2U6Ui Feng Yue u Repair I VI. Patent Application Scope When the corresponding data bit of the data of the column structure is opposite, the corresponding i S signal is changed to a preset low level. [24] The contents of the integrated circuitization of claim 19 can be defined as an i-memory memory structure in which each of the columns of the integrated circuit-addressable memory carcass structure includes a plurality of a mask unit, each of the mask units coupled to the plurality of selected content addressable memory units, with | a plurality of selected inner addressable memory in the same column when the mask unit is confirmed to be executed The unit is masked, and when the mask unit does not confirm the execution of the line, the plurality of selected content addressable memory units are not masked. i 25 · The content of the integrated circuit can be determined as in the 24th item of the patent application scope, wherein the plurality of masks are arranged in each column of the integrated circuitizable memory |body structure of the integrated circuit The unit can be set to an unacknowledged execution by an overall signal i. Page 34