CN115473523A - Multi-bit-width counter signal clock-crossing synchronization circuit and method - Google Patents

Abstract

The invention discloses a multi-bit wide counter signal clock-crossing synchronization circuit and a method, which comprises the following steps: (1) Four quarter-frequency clock signals with time difference are generated in a slow clock domain CLK1 by means of a shift register; (2) Beating the four-frequency-division clock signals and the counting enable signal into 3-beat running water to obtain synchronized frequency-division clock signals and beat enable signals; (3) Corresponding each bit of the two synchronized frequency division clock signals, respectively carrying out logic processing, and generating four counting enabling signals; (4) And when the enable signal after beating is high and any bit of the counting enable signal is high, enabling the counter +1 of the fast clock domain to obtain a synchronized counter signal. The invention has the application range of any phase relation from any slow clock domain to a fast clock domain, avoids the generation of a metastable state phenomenon, ensures the correctness of data synchronization and improves the stability of system operation.

Description

Multi-bit-width counter signal clock-crossing synchronization circuit and method

Technical Field

The invention relates to a multi-bit wide counter signal clock-crossing synchronization circuit and a method, belonging to the technical field of electronics.

Background

When the multi-bit wide counter signal is used across clock domains, clock domain crossing synchronization needs to be carried out, otherwise, a metastable state phenomenon can be caused. The metastable state phenomenon means that the flip-flop cannot reach an identifiable state within a certain specified time period, and in a synchronous system, if the setup time/hold time of the flip-flop is not satisfied, a metastable state may be generated, at this time, the output end Q of the flip-flop is in an uncertain state for a relatively long time after an effective clock edge, and a glitch, oscillation and a fixed certain voltage value at the Q end are not equal to the value of the data input end D in the time. This time is called a resolution time. After the resolution time, the Q terminal will be stable to 0 or 1, but whether it is 0 or 1 is random, and there is no necessary relationship with the input.

In view of the above, the present application provides a multi-bit wide counter signal clock-crossing synchronization circuit and method for solving the problem of generating a metastable state phenomenon when multi-bit wide counter signals are synchronized across clock domains.

Disclosure of Invention

The invention aims to provide a multi-bit wide counter signal clock-crossing synchronization circuit and a method thereof, which avoid the generation of a metastable state phenomenon.

In order to achieve the purpose, the invention provides the following technical scheme: a multi-bit wide counter signal clock-crossing synchronous circuit comprises a slow clock domain CLK1, a fast clock domain CLK2, an enable signal ENB, a reset signal RST _ N, a shift frequency dividing module, a beat synchronous module, an enable signal superposition module and a counting module, wherein the output ends of the slow clock domain CLK1, the enable signal ENB and the reset signal RST _ N are all connected with the corresponding input ends of the shift frequency dividing module, the output ends of the shift frequency dividing module, the enable signal ENB and the fast clock domain CLK2 are all connected with the corresponding input ends of the beat synchronous module, the output end of the reset signal RST _ N is connected with the input end of the beat synchronous module, and a first NOT circuit is arranged between the reset signal RST _ N and the beat synchronous module, the beat synchronization module is provided with a first output port ENBB03, a second output port SFTB02 and a third output port SFTB03, the output end of the third output port SFTB03 is connected with the input end of a second NOT gate circuit, the output end of the second NOT gate circuit and the output end of the second output port SFTB02 are connected to the input end of an AND gate circuit, the output end of the AND gate circuit is connected with the input end of an enable signal superposition module, the output ends of the enable signal superposition module, the first output port ENBB03 and the fast clock domain CLK2 are connected with the corresponding input ends of the counting module, the output end of a reset signal RST _ N is connected with the input end of the counting module, a third NOT gate circuit is arranged between the reset signal RST _ N and the counting module, and the output end of the counting module outputs a required counting signal.

Further, the multi-bit width counter signal is synchronized across clocks, wherein: the output end of the AND gate circuit is provided with four output ports, correspondingly, the enabling signal superposition module is provided with four input ports, and the AND gate circuit is correspondingly connected with each port of the enabling signal superposition module.

The invention also discloses a multi-bit wide counter signal cross-clock synchronization method, which adopts the multi-bit wide counter signal cross-clock synchronization circuit to synchronize the counter signal from a slow clock domain CLK1 to a fast clock domain CLK2 and specifically comprises the following steps:

(1) When the count enable signal ENB is high, 4 time-difference clock signals SFTCNT [3 ];

(2) Synchronizing 4 four-frequency-division clock signals SFTCNT [3 ] and a count enable signal ENB into a clock domain CLK2, namely, beating 3 beats of water on the 4 four-frequency-division clock signals SFTCNT [3 ] and the count enable signal ENB to obtain 3 frequency-division clock signals SFTB [3 ] after four-bit synchronization and 3 beat enable signals ENBB 01-03;

(3) Selecting a synchronized frequency division clock signal SFTB02 and a synchronized frequency division clock signal SFTB03 in the 3 synchronized frequency division clock signals SFTB [3 ] obtained in the step (2), corresponding each bit in the synchronized frequency division clock signal SFTB02 and the synchronized frequency division clock signal SFTB03, respectively performing logic processing, and generating 4 new counting enabling signals SFTBGN [3 ] which accord with the pulse width of a fast clock domain CLK2, wherein the logic processing formula is SFGN = SFTB02 & -SFTB 03;

(4) When the enable signal ENBB03 after the beat in step (2) is high and when any one of the bits of the count enable signal SFTBGN [3 ] is high, the counter +1 of the fast clock domain CLK2 is set to obtain the synchronized counter signal CNT [ 24.

Further, the multi-bit width counter signal cross-clock synchronization method includes: the frequency-division clock signal SFTB [3 ] in the step (2) is a four-bit frequency-division clock signal.

The invention has the beneficial effects that: the invention synchronizes the counter signal from the slow clock domain CLK1 to the fast clock domain CLK2, has the application range of any phase relation from any slow clock domain to any fast clock domain, avoids the generation of a metastable state phenomenon, ensures the correctness of data synchronization and improves the stability of system operation.

Drawings

FIG. 1 is a circuit diagram of the multi-bit wide counter signal synchronization of the present invention;

FIG. 2 is a graphical representation of the multi-bit width counter signal synchronization method after step 1;

FIG. 3 is a graphical representation of the multi-bit width counter signal synchronization method after step 2;

FIG. 4 is a graph showing waveforms after step 3 of the multi-bit width counter signal synchronization method;

FIG. 5 is a waveform diagram after step 4 of the multi-bit width counter signal synchronization method.

Detailed Description

For further understanding of the contents, features and effects of the present invention, the following detailed description is given in conjunction with the accompanying drawings.

Referring to fig. 1 to 5, a multi-bit wide counter signal cross-clock synchronization circuit and method according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, the multi-bit wide counting signal cross clock synchronization circuit according to the present invention includes a slow clock domain CLK1, a fast clock domain CLK2, an enable signal ENB, a reset signal RST _ N, a shift frequency division module, a beat synchronization module, an enable signal superposition module, and a counting module, wherein output ends of the slow clock domain CLK1, the enable signal ENB, and the reset signal RST _ N are all connected to corresponding input ends of the shift frequency division module, output ends of the shift frequency division module, the enable signal ENB, and the fast clock domain CLK2 are all connected to corresponding input ends of the beat synchronization module, an output end of the reset signal RST _ N is connected to an input end of the beat synchronization module, and a first not-gate circuit is disposed between the reset signal RST _ N and the beat synchronization module, the beat synchronization module is provided with a first output port ENBB03, a second output port SFTB02 and a third output port SFTB03, the output end of the third output port SFTB03 is connected with the input end of a second NOT gate circuit, the output end of the second NOT gate circuit and the output end of the second output port SFTB02 are connected to the input end of an AND gate circuit, the output end of the AND gate circuit is connected with the input end of an enable signal superposition module, the output ends of the enable signal superposition module, the first output port ENBB03 and the fast clock domain CLK2 are connected with the corresponding input ends of the counting module, the output end of a reset signal RST _ N is connected with the input end of the counting module, a third NOT gate circuit is arranged between the reset signal RST _ N and the counting module, and the output end of the counting module outputs a required counting signal.

The output end of the AND gate circuit is provided with four output ports, correspondingly, the enabling signal superposition module is provided with four input ports, and the AND gate circuit is correspondingly connected with each port of the enabling signal superposition module.

As shown in fig. 2 to 5, the multi-bit wide count signal cross-clock synchronization method of the present invention synchronizes the counter signal from the slow clock domain CLK1 to the fast clock domain CLK2, comprising the following steps:

(1) When the count enable signal ENB is high, 4 time-difference clock signals SFTCNT [3 ]; specific output waveforms can be found in fig. 2: for example, if CLK1=8M, the initial value of the shift register may be set to 4' b0011, which corresponds to dividing CLK1 by four to generate 4 clock signals of 2M;

(2) Synchronizing 4 four-frequency-division clock signals SFTCNT [3 ] and a count enable signal ENB into a clock domain CLK2, namely, beating 3 beats of water on the 4 four-frequency-division clock signals SFTCNT [3 ] and the count enable signal ENB to obtain 3 frequency-division clock signals SFTB [3 ] after four-bit synchronization and 3 beat enable signals ENBB 01-03; referring to fig. 3, the specific output waveform of the fast clock domain CLK2 is HCLK in fig. 3;

(3) Selecting a synchronized frequency division clock signal SFTB02 and a synchronized frequency division clock signal SFTB03 in the 3 synchronized frequency division clock signals SFTB [3 ] obtained in the step (2), enabling each bit of the four-bit synchronized frequency division clock signal SFTB02 and the four-bit synchronized frequency division clock signal SFTB03 to correspond to each other, and performing logic processing respectively to generate 4 new counting enable signals SFTBGN [3 0] which accord with the pulse width of the fast clock domain CLK2, wherein the logic processing formula is SFTBGN = SFTB02 & -SFTB 03, the specific output waveform can refer to FIG. 4, the formula corresponds to that the output end of a third output port SFTB03 of the circuit in FIG. 1 is connected with the input end of a second NOT gate circuit, the output end of the second NOT gate circuit and the output end of the second output port SFTB02 are connected to the input end of an AND gate circuit, and the output end of the AND gate circuit is connected with the input end of an enable signal superposition module;

(4) When the enable signal ENBB03 after the beat in step (2) is high and when any one of the bits of the count enable signal SFTBGN [3 ] is high, the counter +1 of the fast clock domain CLK2 is set to be the one having the synchronized counter signal CNT [ 24.

The invention can be seen from the above description that the application range of the invention lies in any phase relation from any slow clock domain to a fast clock domain (the frequency of the fast clock domain is more than or equal to that of the slow clock domain), the generation of the metastable state phenomenon is avoided, the correctness of data synchronization is ensured, and the stability of system operation is improved.

It is understood that the above are only exemplary embodiments of the present invention, and other embodiments of the present invention may be made by using equivalent or equivalent alternatives, which fall within the scope of the present invention.

Claims (4)

1. A multi-bit wide counter signal clock-crossing synchronization circuit, characterized by: the circuit comprises a slow clock domain CLK1, a fast clock domain CLK2, an enable signal ENB, a reset signal RST _ N, a shift frequency dividing module, a beat synchronization module, an enable signal superposition module and a counting module, wherein the output ends of the slow clock domain CLK1, the enable signal ENB and the reset signal RST _ N are all connected with the corresponding input ends of the shift frequency dividing module, the output ends of the shift frequency dividing module, the enable signal ENB and the fast clock domain CLK2 are all connected with the corresponding input ends of the beat synchronization module, the output end of the reset signal RST _ N is connected with the input end of the beat synchronization module, a first NOT circuit is arranged between the reset signal RST _ N and the beat synchronization module, the beat synchronization module is provided with a first output port ENBB03, a second output port SFTB02 and a third output port SFTB03, the output end of the third output port SFTB03 is connected with the input end of a second NOT gate circuit, the output end of the second NOT gate circuit and the output end of the second output port SFTB02 are connected to the input end of an AND gate circuit, the output end of the AND gate circuit is connected with the input end of an enable signal superposition module, the output ends of the enable signal superposition module, the first output port ENBB03 and the fast clock domain CLK2 are connected with the corresponding input ends of the counting module, the output end of a reset signal RST _ N is connected with the input end of the counting module, a third NOT gate circuit is arranged between the reset signal RST _ N and the counting module, and the output end of the counting module outputs a required counting signal.

2. The multi-bit wide counter signal lockstep circuit of claim 1, wherein: the output end of the AND gate circuit is provided with four output ports, correspondingly, the enabling signal superposition module is provided with four input ports, and the AND gate circuit is correspondingly connected with each port of the enabling signal superposition module.

3. A method for cross-clock synchronization of a multi-bit wide counter signal, using the multi-bit wide counter signal cross-clock synchronization circuit of claim 2, to synchronize the counter signal from a slow clock domain CLK1 to a fast clock domain CLK2, comprising the steps of:

(1) When the count enable signal ENB is high, 4 time-difference clock signals SFTCNT [3 ];

(2) Synchronizing 4 four-frequency-division clock signals SFTCNT [3 ] and a count enable signal ENB into a clock domain CLK2, namely, beating 3 beats of water on the 4 four-frequency-division clock signals SFTCNT [3 ] and the count enable signal ENB to obtain 3 frequency-division clock signals SFTB [3 ] after four-bit synchronization and 3 beat enable signals ENBB 01-03;

(3) Selecting a synchronized frequency division clock signal SFTB02 and a synchronized frequency division clock signal SFTB03 in the 3 synchronized frequency division clock signals SFTB [3 ] obtained in the step (2), corresponding each bit in the synchronized frequency division clock signal SFTB02 and the synchronized frequency division clock signal SFTB03, respectively performing logic processing, and generating 4 new count enable signals SFTBGN [3 ] which accord with the pulse width of the fast clock domain CLK2, wherein the logic processing formula is SFTBGN = SFTB02 & -SFTB 03;

(4) When the enable signal ENBB03 after the beat in step (2) is high and when any one of the bits of the count enable signal SFTBGN [3 ] is high, the counter +1 of the fast clock domain CLK2 is set to obtain the synchronized counter signal CNT [ 24.

4. A method of multi-bit wide counter signal synchronization across clocks according to claim 3, wherein: the frequency-division clock signal SFTB [3 ] in the step (2) is a four-bit frequency-division clock signal.

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