CN115469711B - Sine and cosine signal generator, memory and quantum computer control system - Google Patents
Sine and cosine signal generator, memory and quantum computer control system Download PDFInfo
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Abstract
The invention discloses a sine and cosine signal generator, a memory and a quantum computer control system. The sine and cosine signal generator comprises an address acquisition module and a memory, wherein the memory stores sine values and cosine values of a first number of preset frequencies: the address acquisition module is used for sequentially acquiring table lookup addresses which are increased by a preset step size under the action of a working clock and sending the table lookup addresses into the memory; the memory is configured to output a second number of current sine values and current cosine values for forming the sine signals and the cosine signals respectively in parallel each time a table lookup address is sent; the phase of the sine value and the cosine value output each time is increased by a preset phase increment, the sine value and the cosine value output by two adjacent times are continuous in phase, and the preset phase increment is determined according to a preset frequency, a first quantity, a second quantity and the frequency of the working clock. Through the mode, the method and the device can generate the sine and cosine signals with higher frequency in the FPGA, and can reduce resource consumption and cost.
Description
Technical Field
The invention relates to the field of quantum computation, in particular to a sine and cosine signal generator, a memory and a quantum computer control system.
Background
The quantum computer control system mainly aims at controlling a quantum computer, and more particularly, controlling quantum bits. The essence of controlling the qubit is to apply various control signals to the qubit, which are mostly generated from basic sine and cosine signals. Because the frequency of the qubit is relatively high, the control signal needs to have a relatively high frequency, and the corresponding sine and cosine signal also needs to have a relatively high frequency.
However, sine and cosine signals are generally generated by using an NCO (numerically controlled oscillator), which may be implemented in devices such as FPGA. The higher the frequency of the sine and cosine signals, the higher the required sampling rate, but most FPGAs have limited highest working frequency, so the frequency of the generated sine and cosine signals is lower. In order to improve the frequency of sine and cosine signals, the prior art generates sine and cosine signals with lower frequency in parallel through a plurality of FPGAs, and synthesizes the frequencies of the sine and cosine signals. But doing so requires multiple FPGAs, which greatly increases resource consumption and cost.
Disclosure of Invention
The invention aims to provide a sine and cosine signal generator, a memory and a quantum computer control system, so as to solve the problem of low frequency of sine and cosine signals generated in an FPGA in the prior art, and can generate sine and cosine signals with high frequency in the FPGA.
In order to solve the technical problems, the invention provides a sine and cosine signal generator which is used for an FPGA and comprises an address acquisition module and a memory, wherein the memory stores sine values and cosine values of a first number of preset frequencies:
the address acquisition module is used for sequentially acquiring table lookup addresses which are increased by a preset step length under the action of a working clock and sending the table lookup addresses into the memory;
the memory is configured to output a second number of current sine values and current cosine values for forming a sine signal and a cosine signal respectively in parallel each time a table lookup address is sent;
The phase of the sine value and the cosine value output each time is increased by a preset phase increment, the sine value and the cosine value output by two adjacent times are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock.
Preferably, the memory provides two identical lookup tables, the two lookup tables respectively store sine values and cosine values, the number of lookup address bits of the lookup table is a first number of bits a, the number of data bits of the lookup table is a second number of bits B, and the sine values and the cosine values of the second number with continuous phases correspond to the same lookup address, wherein the product of 2 A and the second number is equal to 2 B.
Preferably, the lookup table has a second number of sub-tables, each sub-table stores a number of sine values or cosine values of 2 B, the same data bit of each sub-table corresponds to the same lookup address, the sine values or cosine values stored in the same data bit are continuous in phase, and the phases of the sine values or cosine values stored in two adjacent data bits in the same sub-table differ by a second number of preset phase increment.
Preferably, the preset phase increment is:
Wherein N represents the first number, the value range is [1,2 B ], c represents the second number, f out represents the preset frequency, and f S represents the frequency of the working clock.
Preferably, the sinusoidal signal is:
The cosine signal is:
wherein n represents the value of the table lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset.
Preferably, the amplitude, the initial phase and the offset of the sine signal and the cosine signal are the same.
Preferably, the address obtaining module is specifically configured to sequentially receive externally input table lookup addresses increasing in a preset step size under the action of a working clock, and send the table lookup addresses to the memory.
Preferably, the system further comprises an address pre-storing module, wherein the address pre-storing module is used for pre-storing the table lookup addresses which are increased by a preset step.
Preferably, the device further comprises an address generation module, wherein the address generation module is used for generating a table lookup address which is increased by a preset step size.
Preferably, the address generation module is specifically configured to perform accumulation from zero to generate a table lookup address that is incremented by a preset step size.
In order to solve the technical problem, the present invention further provides a memory, where the memory stores a first number of sine values and cosine values of a preset frequency, and the memory is configured to output, in parallel, a second number of current sine values and current cosine values for forming a sine signal and a cosine signal, respectively, when each table lookup address is sent into the memory;
the table lookup address is sent in under the action of a working clock, the table lookup address sent in each time is increased by a preset step length, the phase of the sine value and the cosine value output each time is increased by a preset phase increment, the sine value and the cosine value output two adjacent times are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock.
Preferably, the memory provides two identical lookup tables, the two lookup tables respectively store sine values and cosine values, the number of lookup address bits of the lookup table is a first number of bits a, the number of data bits of the lookup table is a second number of bits B, and the sine values and the cosine values of the second number with continuous phases correspond to the same lookup address, wherein the product of 2 A and the second number is equal to 2 B.
Preferably, the lookup table has a second number of sub-tables, the number of sine values or cosine values stored in each sub-table is 2 B, the same data bit of each sub-table corresponds to the same lookup address, the sine values or cosine values stored in the same data bit are continuous in phase, and the phase difference between the sine values or cosine values stored in two adjacent data bits in the same sub-table is a second number of preset phase increment.
Preferably, the preset phase increment is:
Wherein N represents the first number, the value range is [1,2 B ], c represents the second number, f out represents the preset frequency, and f S represents the frequency of the working clock.
Preferably, the sinusoidal signal is:
The cosine signal is:
wherein n represents the value of the table lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset.
Preferably, the amplitude, the initial phase and the offset of the sine signal and the cosine signal are the same.
In order to solve the technical problems, the invention also provides a quantum computer control system which comprises any one of the sine and cosine signal generator or any one of the memories.
Compared with the prior art, the sine and cosine signal generator sequentially acquires the table lookup addresses under the action of the working clock and sends the table lookup addresses into the memory, the memory stores sine values and cosine values of a first number of preset frequencies, the memory is configured to respectively output the sine values and the cosine values of a second number in parallel when each table lookup address is sent in, the output sine values and cosine values are used for respectively forming sine signals and cosine signals, the preset frequencies are the frequencies of sine and cosine signals, and because the product of the frequency of the working clock and the second number is equivalent to the sampling frequency, the theoretical preset frequencies can reach half of the sampling frequency according to the Nyquist sampling law, so that sine and cosine signals with higher frequencies can be generated in the FPGA, and the resource consumption and the cost can be reduced.
The memory and the quantum computer control system provided by the invention belong to the same invention conception as the sine and cosine signal generator, so that the memory and the quantum computer control system have the same beneficial effects, and the sine and cosine signal generator provided by the invention is not repeated here.
Drawings
Fig. 1 is a schematic structural diagram of a sine and cosine signal generator according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of a data structure of a lookup table provided by a memory of a sine and cosine signal generator according to a first embodiment.
Fig. 3 is a schematic diagram of a data structure of storing sine values in each sub-table of the lookup table in the first embodiment.
Fig. 4 is a schematic structural diagram of a sine and cosine signal generator according to a second embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a sine and cosine signal generator according to a third embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Referring to fig. 1, a first embodiment of the present invention provides a sine and cosine signal generator for an FPGA, which is capable of generating a sine and cosine signal with a higher frequency in the FPGA. The sine and cosine signal generator comprises an address acquisition module 10 and a memory 20, wherein the memory 20 stores a first number of sine values and cosine values of a preset frequency.
The address acquisition module 10 is configured to sequentially acquire the table lookup addresses incremented by a preset step size under the action of the working clock, and send the table lookup addresses to the memory 20. The table lookup address is usually represented in binary, and the value of the table lookup address acquired for the first time is preferably 0. The difference between the table lookup address obtained each time and the table lookup address obtained last time is a preset step length, and the preset step length can be set according to actual needs, for example, 1.
The memory 20 is configured to output in parallel a second number of current sine values and current cosine values for forming a sine signal and a cosine signal, respectively, each time a table lookup address is entered; the phase of the sine value and the cosine value output each time is increased by a preset phase increment, the sine value and the cosine value output by two adjacent times are continuous in phase, and the preset phase increment is determined according to a preset frequency, a first quantity, a second quantity and the frequency of the working clock.
In which, taking the sine value of each output as an example, their frequencies are all preset frequencies, but their phases are continuous. When the first table lookup address is sent, the memory 20 may sequentially read the second number of sine values from the sine value with the smallest phase in the order of from the smaller phase to the larger phase, the difference between the phases of the sine values read in two adjacent times is the preset phase increment, and then the memory 20 outputs the read second number of sine values in parallel. This is then done for each look-up table, and the difference between the phase of the first sine value of the last read and the last sine value of the last read is also the predetermined phase increment.
Similarly, the frequency of the cosine value output each time is a preset frequency, and the phase is continuous. The second number of sine values forms a digitized sine signal and the second number of cosine values forms a digitized cosine signal, which are continuously generated as long as the lookup address is continuously fed into the memory 20.
The preset frequency, the first quantity, the second quantity and the frequency of the working clock are set according to actual needs. The preset frequency is the frequency of the sine signal and the cosine signal. The first number is a total number of sine or cosine values stored by the memory and the second number is a fraction of the total number of sine or cosine values, and therefore the second number is less than or equal to the first number. The frequency of the operating clock should not exceed the maximum operating frequency of the FPGA. The frequency of the operating clock and the value of the second number are related to the sampling rate, the product of the two being equivalent to the sampling rate, e.g. when the sampling rate is 1.6GHz, the frequency of the operating clock is set to 200MHz, and then the second number is 8. The sampling rate is determined by the control requirements of the qubit. According to the nyquist sampling law, the ratio of the preset frequency to the sampling frequency is at most 1:2, that is to say, the preset frequency can reach 800MHz theoretically, thereby realizing the sine and cosine signals with higher frequency in the FPGA.
Referring to fig. 2, the memory 20 provides two identical look-up tables LUT, wherein the two look-up tables LUT store sine values and cosine values respectively, the number of bits of the look-up address of the look-up table LUT is a first number of bits a, the number of bits of the data of the look-up table LUT is a second number of bits B, and the second number of sine values and cosine values with continuous phases correspond to the same look-up address, wherein the product of 2 A and the second number is equal to 2 B. The lookup address is incremented from 0.
Wherein one look-up table LUT stores a first number of sine values and the other look-up table LUT stores a first number of cosine values, the first number being equal to 2 A.2A sine values or cosine values requiring addressing by 2 B look-up addresses, and the second number B being smaller than the first number a, then one look-up address is required to address the second number of sine values or cosine values simultaneously. The phases of the sine value and the cosine value of the second number corresponding to each table lookup address are continuous, so that the phase difference between the adjacent sine value and the adjacent cosine value in the sine value and the cosine value of the second number corresponding to the same table lookup address is a preset phase increment, and the phase difference between the sine value and the cosine value with the largest phase in the sine value and the cosine value of the second number corresponding to the former table lookup address and the phase difference between the sine value and the cosine value with the smallest phase in the sine value and the cosine value of the second number corresponding to the latter table lookup address is also a preset phase increment.
The storage locations of the first number of sine values or cosine values in the look-up table LUT can be flexibly adjusted. In an application scenario of the embodiment of the present invention, the lookup table LUT has a second number of sub-tables, the number of sine values or cosine values stored in each sub-table is 2 B, the same data bit of each sub-table corresponds to the same lookup address, and the sine values or cosine values stored in the same data bit are continuous in phase, and the phases of the sine values or cosine values stored in two adjacent data bits in the same sub-table differ by a second number of preset phase increment.
Wherein the number of sub-tables is also equal to the second number, so that each sub-table only needs to store a number of sine values or cosine values of 2 B, and thus the total number of the sine values or cosine values stored in all sub-tables is equal to the first number. Each sine value or cosine value in the sub-table occupies a data bit, the number of table lookup address bits corresponding to the data bits in the sub-table is the second bit number B, the 1 st table lookup address corresponds to the 1 st data bit of each sub-table, namely corresponds to the sine value or cosine value stored in the 1 st data bit, the 2 nd table lookup address corresponds to the 2 nd data bit of each sub-table, the 3 rd table lookup address corresponds to the 3 rd data bit of each sub-table, and the like, and the 2 nd B table lookup address corresponds to the 2 nd B data bits of each sub-table.
And the sine or cosine values stored by the same data bits of each sub-table are consecutive in phase, i.e. the difference in phase is a preset phase increment. The phase difference of the sine value or the cosine value stored by two adjacent data bits in the same sub-table is a preset phase increment of a second quantity, namely the product of the second quantity and the preset phase increment.
In this embodiment, the preset phase increment is:
Wherein, N represents the first quantity, the value range is [1,2 B ], c represents the second quantity, f out represents the preset frequency, and f S represents the frequency of the working clock.
Further, the sinusoidal signal is:
The cosine signal is:
wherein n represents the value of the lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset. In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offset of the sine signal and the cosine signal are the same.
Each sub-table will be described in detail below with reference to fig. 3. Referring to fig. 3, each sine value of the sine signal expressed by the above formula is stored in 8 sub-tables of a lookup table LUT. The number of sine values, namely the first number N is equal to 2 17, the number of sub-tables, namely the second number 8,c, is in the value range of [0,7], 8 sub-tables are respectively corresponding, the number of bits of the table lookup address is 14, the value range of the table lookup address is [0,2 14 -1], for the convenience of calculation, a is 1,And b takes 0. The sine values stored in each sub-table are as follows:
The sine value stored in each data bit of the 1 st sub-table is in turn sin[0*2π*PINC/N]、sin[8*2π*PINC/N]、sin[16*2π*PINC/N]、…、sin[8*(214-2)*2π*PINC/N]、sin[8*(214-1)*2π*PINC/N];
The sine value stored in each data bit of the 2 nd sub-table is in turn sin[1*2π*PINC/N]、sin[9*2π*PINC/N]、sin[17*2π*PINC/N]、…、sin[(8*(214-2)+1)*2π*PINC/N]、sin[(8*(214-1)+1)*2π*PINC/N];
The sine value stored in each data bit of the 3 rd sub-table is in turn sin[2*2π*PINC/N]、sin[10*2π*PINC/N]、sin[18*2π*PINC/N]、…、sin[(8*(214-2)+2)*2π*PINC/N]、sin[(8*(214-1)+2)*2π*PINC/N];
Similarly, the sine value stored in each data bit of the 8 th sub-table is in turn sin[7*2π*PINC/N]、sin[15*2π*PINC/N]、sin[23*2π*PINC/N]、…、sin[(8*(214-2)+7)*2π*PINC/N]、sin[(8*(214-1)+7)*2π*PINC/N].
It can be seen that the sine values stored in adjacent two data bits in each sub-table are out of phase by 8 x PINC.
The process of generating the sinusoidal signal is as follows:
When the 1 st table lookup address is sent, i.e. n=0, 8 sub-tables output sin [0*2 pi ] PINC/N, sin [1*2 pi ] PINC/N, sin [2 pi ] PINC/N, …, sin [7*2 pi ] PINC/N;
When the 2 nd table lookup address is sent, i.e. n=1, 8 sub-tables output sin [8*2 pi ] PINC/N, sin [9*2 pi ] PINC/N, sin [10 pi ] PINC/N, …, sin [15 pi ] PINC/N;
When the 3 rd table lookup address is sent, i.e. n=2, 8 sub-tables output sin [16 x 2 pi ] PINC/N, sin [17 x 2 pi ] PINC/N, sin [18 x 2 pi ] PINC/N, …, sin [23 x 2 pi ] PINC/N respectively;
By analogy, when the 2 14 th lookup address is input, namely n= 14 -1, 8 sub-tables output respectively sin[8*(214-1)*2π*PINC/N]、sin[(8*(214-1)+1)*2π*PINC/N]、sin[(8*(214-1)+2)*2π*PINC/N]、…、sin[(8*(214-1)+7)*2π*PINC/N].
It can be seen that the phase of the 8 sine values output by the 8 sub-tables each time is incremented by PINC, the last sine value output in the previous time being out of phase with the first sine value output in the next time by PINC.
The lookup address may be generated by internal pre-storage, internal generation, or external input.
If the external input is an external input, in this embodiment, the address acquisition module 10 is specifically configured to sequentially receive, under the action of the working clock, the externally input table lookup addresses that are incremented by a preset step size, and send the table lookup addresses to the memory 20.
In case of internal pre-storage, please refer to fig. 4, a second embodiment of the present invention provides a sine and cosine signal generator, which includes all the technical features of the first embodiment, wherein the sine and cosine signal generator of the present embodiment further includes an address pre-storage module 30, and the address pre-storage module 30 is configured to pre-store a table lookup address incremented by a preset step size. The address acquisition module 10 acquires the lookup address from the address pre-storing module 30.
In case of internal generation, please refer to fig. 5, a third embodiment of the present invention provides a sine and cosine signal generator, which includes all the technical features of the first embodiment, except that the sine and cosine signal generator of the present embodiment further includes an address generation module 40, and the address generation module 40 is configured to generate a table lookup address incremented by a preset step size. The address acquisition module 10 acquires the lookup address from the address generation module 40. Further, the address generating module 40 is specifically configured to perform accumulation from zero to generate a table lookup address that is incremented by a preset step size.
By means of the mode, the sine and cosine signal generator sequentially obtains the table lookup addresses under the action of the working clock and sends the table lookup addresses to the memory, the memory stores the sine value and the cosine value of the first number of preset frequencies, the memory is configured to output the current sine value and the current cosine value of the second number in parallel when each table lookup address is sent, the output sine value and the output cosine value are used for forming the sine signal and the cosine signal respectively, the preset frequencies are the frequencies of the sine and cosine signals, the product of the frequency of the working clock and the second number is equivalent to the sampling frequency, and according to the Nyquist sampling law, the preset frequencies can reach half of the sampling frequency theoretically, so that sine and cosine signals with higher frequencies can be generated in the FPGA.
The embodiment of the invention also provides a memory, which stores a first number of sine values and cosine values of preset frequencies, and is configured to respectively output a second number of current sine values and current cosine values for respectively forming sine signals and cosine signals in parallel when each table lookup address is sent into the memory; the table lookup address is sent in under the action of the working clock, the table lookup address sent in each time is increased by a preset step length, the phase of the sine value and the cosine value output each time is increased by a preset phase increment, the sine value and the cosine value output two adjacent times are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock.
In some embodiments, the memory provides two identical lookup tables, where the two lookup tables store sine values and cosine values, respectively, the number of lookup address bits of the lookup table is a first number of bits a, the number of data bits of the lookup table is a second number of bits B, and the second number of sine values and cosine values with consecutive phases corresponds to the same lookup address, where the product of 2 A and the second number is equal to 2 B.
In some embodiments, the lookup table has a second number of sub-tables, each sub-table stores a sine value or a cosine value of 2 B, the same data bit of each sub-table corresponds to the same lookup address, and the sine value or the cosine value stored in the same data bit is continuous in phase, and the phases of the sine value or the cosine value stored in two adjacent data bits in the same sub-table differ by a second number of preset phase increments.
In some embodiments, the preset phase increment is:
Wherein, N represents the first quantity, the value range is [1,2 B ], c represents the second quantity, f out represents the preset frequency, and f S represents the frequency of the working clock.
Further, the sinusoidal signal is:
The cosine signal is:
wherein n represents the value of the lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset. In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offset of the sine signal and the cosine signal are the same.
For the description of the memory, reference can be made to the description of the sine and cosine signal generator in the previous embodiment, and the memory has the same technical features as the memory 20 of the sine and cosine signal generator in the previous embodiment, and will not be repeated here.
The embodiment of the invention also provides a quantum computer control system which comprises the sine and cosine signal generator provided by the previous embodiment or the memory provided by the previous embodiment.
It should be noted that, the sine and cosine generator provided by the foregoing embodiment or the memory provided by the foregoing embodiment is also applicable to any other application scenario with sine and cosine signal generation requirements besides being applied to the quantum computer control system, which is not limited in this invention.
In the description of the present specification, a description of the terms "one embodiment," "some embodiments," "examples," or "particular examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (17)
1. The sine and cosine signal generator is used for an FPGA and is characterized by comprising an address acquisition module and a memory, wherein the memory stores sine values and cosine values of a first number of preset frequencies:
the address acquisition module is used for sequentially acquiring table lookup addresses which are increased by a preset step length under the action of a working clock and sending the table lookup addresses into the memory;
the memory is configured to output a second number of current sine values and current cosine values for forming a sine signal and a cosine signal respectively in parallel each time a table lookup address is sent;
The phase of the sine value and the cosine value output each time is increased by a preset phase increment, the sine value and the cosine value output by two adjacent times are continuous in phase, and the preset phase increment is determined according to the product of the ratio of the preset frequency to the frequency of the working clock and the ratio of the first quantity to the second quantity.
2. The sine and cosine signal generator of claim 1, wherein the memory provides two identical lookup tables, the two lookup tables respectively storing sine and cosine values, the lookup table having a first number of bits a, the lookup table having a second number of bits B, the sine and cosine values of a second number of consecutive phases corresponding to the same lookup address, wherein a product of 2 A and the second number equals 2 B.
3. The sine and cosine signal generator of claim 2, wherein the lookup table has a second number of sub-tables, each sub-table stores a number of sine or cosine values of 2 B, the same data bit of each sub-table corresponds to the same lookup address, the sine or cosine values stored in the same data bit are consecutive in phase, and the phases of the sine or cosine values stored in adjacent two data bits in the same sub-table differ by a second number of preset phase increments.
4. A sine and cosine signal generator according to claim 3, wherein the predetermined phase increment is:
wherein N represents the first number and the value range is [1,2 B ], c represents the second number, Representing the preset frequency,/>Representing the frequency of the operating clock.
5. The sine and cosine signal generator of claim 4, wherein the sine signal is:
The cosine signal is:
Wherein n represents the value of the table lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset.
6. The sine and cosine signal generator of claim 5, wherein the sine and cosine signals are identical in magnitude, phase and offset.
7. The sine and cosine signal generator according to claim 1, wherein the address acquisition module is specifically configured to sequentially receive externally input table lookup addresses with increasing preset step sizes under the action of a working clock, and send the table lookup addresses to the memory.
8. The sine and cosine signal generator of claim 1, further comprising an address pre-storing module for pre-storing a table lookup address incremented by a preset step size.
9. The sine and cosine signal generator of claim 1, further comprising an address generation module for generating a lookup address incremented by a preset step size.
10. The sine and cosine signal generator of claim 9, wherein the address generation module is specifically configured to accumulate from zero to generate a table lookup address incremented by a preset step size.
11. A memory, wherein the memory stores a first number of sine values and cosine values of a predetermined frequency, the memory being configured to output a second number of current sine values and current cosine values for forming a sine signal and a cosine signal, respectively, in parallel each time a table lookup address is entered;
The table lookup address is sent in under the action of the working clock, the table lookup address sent in each time is increased by a preset step length, the phase of the sine value and the cosine value output each time is increased by a preset phase increment, the sine value and the cosine value output two adjacent times are continuous in phase, and the preset phase increment is determined according to the product of the ratio of the preset frequency to the frequency of the working clock and the ratio of the first quantity to the second quantity.
12. The memory of claim 11, wherein the memory provides two identical look-up tables, the two look-up tables storing sine and cosine values, respectively, the look-up table having a first number of bits a, the look-up table having a second number of bits B, the second number of sine and cosine values being consecutive in phase corresponding to the same look-up table address, wherein the product of 2 A and the second number is equal to 2 B.
13. The memory of claim 12, wherein the lookup table has a second number of sub-tables, each of the sub-tables storing a number of sine or cosine values of 2 B, the same data bit of each of the sub-tables corresponds to the same table lookup address, and the sine or cosine values stored in the same data bit are consecutive in phase, and the phase of the sine or cosine values stored in adjacent two of the data bits in the same sub-table differ by a second number of preset phase increments.
14. The memory of claim 13, wherein the predetermined phase increment is:
wherein N represents the first number and the value range is [1,2 B ], c represents the second number, Representing the preset frequency,/>Representing the frequency of the operating clock.
15. The memory of claim 14, wherein the sinusoidal signal is:
The cosine signal is:
Wherein n represents the value of the table lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset.
16. The memory of claim 15, wherein the sine signal and cosine signal are the same in amplitude, phase and offset.
17. A quantum computer control system comprising the sine and cosine signal generator of any one of claims 1 to 10 or the memory of any one of claims 11 to 16.
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