CN115469711A - Sine and cosine signal generator, memory and quantum computer control system - Google Patents
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Abstract
The invention discloses a sine and cosine signal generator, a memory and a quantum computer control system. The sine and cosine signal generator comprises an address acquisition module and a memory, wherein the memory stores sine values and cosine values of a first number of preset frequencies: the address acquisition module is used for sequentially acquiring the table lookup addresses increased by the preset step length under the action of a working clock and sending the table lookup addresses into the memory; the memory is configured to output a second number of current sine values and current cosine values for forming the sine signal and the cosine signal, respectively, in parallel, each time a lookup address is sent in; the phase of the sine value and the phase of the cosine value output each time are increased progressively by a preset phase increment, the sine value and the cosine value output twice in the adjacent time are continuous in phase, and the preset phase increment is determined according to a preset frequency, the first number, the second number and the frequency of the working clock. By the mode, the high-frequency sine and cosine signals can be generated in the FPGA, and the resource consumption and the cost can be reduced.
Description
Technical Field
The invention relates to the field of quantum computation, in particular to a sine and cosine signal generator, a memory and a quantum computer control system.
Background
The quantum computer control system mainly functions to control a quantum computer, and more particularly, to control quantum bits. The essence of controlling the qubits is to apply various control signals to the qubits, which are mostly generated from the underlying sine and cosine signals. Because the frequency of the qubit is relatively high, the control signal needs to have a relatively high frequency, and the corresponding sine and cosine signal also needs to have a relatively high frequency.
However, the sine and cosine signals are generally generated by NCO (numerically controlled oscillator), which can be implemented in FPGA or other devices. The higher the frequency of sine and cosine signals is, the higher the sampling rate is required, but the maximum working frequency of most FPGAs is limited, so that the frequency of the generated sine and cosine signals is lower. In order to increase the frequency of the sine and cosine signals, the conventional method is to generate the sine and cosine signals with lower frequency in parallel by a plurality of FPGAs, and then synthesize the frequencies of the sine and cosine signals. But this requires multiple FPGAs, and the resource consumption and cost increase significantly.
Disclosure of Invention
The invention aims to provide a sine and cosine signal generator, a memory and a quantum computer control system, which are used for solving the problem of low frequency of sine and cosine signals generated in an FPGA (field programmable gate array) in the prior art and can generate sine and cosine signals with high frequency in the FPGA.
In order to solve the technical problem, the invention provides a sine and cosine signal generator, which is used for an FPGA and comprises an address acquisition module and a memory, wherein the memory stores sine values and cosine values of a first number of preset frequencies:
the address acquisition module is used for sequentially acquiring the table look-up addresses increased by a preset step length under the action of a working clock and sending the table look-up addresses into the memory;
the memory is configured to output a second number of current sine values and current cosine values for forming the sine signal and the cosine signal, respectively, in parallel, each time a lookup address is sent in;
the phase of the sine value and the phase of the cosine value output each time are increased progressively by a preset phase increment, the sine value and the cosine value output twice in a neighboring mode are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first number, the second number and the frequency of the working clock.
Preferably, the memory provides two identical lookup tables, the two lookup tables respectively store sine values and cosine values, and the lookup address bit number of the lookup table is the secondA digit A, a second digit B, a second number of sine and cosine values with continuous phases corresponding to a same lookup address, 2 A The product with the second number being equal to 2 B 。
Preferably, the look-up table has a second number of sub-tables, each of which stores a number of sine or cosine values of 2 B The same data bit of each sub-table corresponds to the same table look-up address, the sine value or the cosine value stored in the same data bit is continuous in phase, and the phase difference of the sine value or the cosine value stored in two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
Preferably, the preset phase increment is:
wherein N represents the first quantity and has a value range of [1,2 ] B ]C represents said second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock.
Preferably, the sinusoidal signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
Preferably, the amplitudes, initial phases and offset distances of the sine signal and the cosine signal are the same.
Preferably, the address obtaining module is specifically configured to receive, under the action of a working clock, externally input table lookup addresses incremented by a preset step length in sequence, and send the table lookup addresses to the memory.
Preferably, the mobile terminal further comprises an address pre-storing module, wherein the address pre-storing module is used for pre-storing the table look-up address increased by the preset step length.
Preferably, the device further comprises an address generating module, wherein the address generating module is configured to generate the table lookup address incremented by a preset step size.
Preferably, the address generating module is specifically configured to accumulate from zero to generate the table lookup address incremented by a preset step size.
In order to solve the above technical problem, the present invention further provides a memory, where the memory stores a first number of sine values and cosine values of a preset frequency, and the memory is configured to output a second number of current sine values and current cosine values used for forming sine signals and cosine signals respectively in parallel every time a lookup address is sent in;
the table lookup address is sent under the action of a working clock, the table lookup address sent each time is increased in a preset step length, the phase of the sine value and the phase of the cosine value output each time are increased in a preset phase increment, the sine value and the cosine value output in two adjacent times are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first number, the second number and the frequency of the working clock.
Preferably, the memory provides two identical lookup tables, the two lookup tables store sine values and cosine values respectively, the lookup address bits of the lookup tables are a first bit a, the data bits of the lookup tables are a second bit B, and the sine values and cosine values of a second number with continuous phases correspond to the same lookup address, wherein 2 A The product of which is equal to 2 B 。
Preferably, the look-up table has a second number of sub-tables, each of which stores a number of sine or cosine values of 2 B Identical data bits of each of said sub-tablesThe phase difference between the sine value or the cosine value stored by two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
Preferably, the preset phase increment is:
wherein N represents the first number and has a value range of [1,2 B ]C represents said second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock.
Preferably, the sinusoidal signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
Preferably, the amplitudes, initial phases and offset distances of the sine signal and the cosine signal are the same.
In order to solve the above technical problem, the present invention further provides a quantum computer control system, including any one of the sine and cosine signal generators described above or any one of the memories described above.
Different from the situation of the prior art, the sine and cosine signal generator provided by the invention sequentially acquires the table lookup addresses under the action of the working clock and sends the table lookup addresses to the memory, the memory stores the sine values and the cosine values of the first quantity of preset frequencies, the memory is configured to output the sine values and the cosine values of the second quantity in parallel respectively when one table lookup address is sent, the output sine values and cosine values are used for forming sine signals and cosine signals respectively, the preset frequency is the frequency of the sine and cosine signals, and the product of the frequency of the working clock and the second quantity is equivalent to the sampling frequency.
The memory and the quantum computer control system provided by the invention belong to the same inventive concept with the sine and cosine signal generator, so the memory and the quantum computer control system have the same beneficial effects, and the sine and cosine signal generator provided by the invention is not repeated.
Drawings
Fig. 1 is a schematic structural diagram of a sine-cosine signal generator according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of a data structure of a lookup table provided in a memory of the sine and cosine signal generator in the first embodiment.
Fig. 3 is a diagram illustrating a data structure of the first embodiment in which each sub-table of the lookup table stores a sine value.
Fig. 4 is a schematic structural diagram of a sine and cosine signal generator according to a second embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a sine and cosine signal generator according to a third embodiment of the present invention.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Referring to fig. 1, a first embodiment of the present invention provides a sine and cosine signal generator for an FPGA, which is capable of generating a sine and cosine signal with a higher frequency in the FPGA. The sine and cosine signal generator comprises an address acquisition module 10 and a memory 20, wherein the memory 20 stores sine values and cosine values of a first number of preset frequencies.
The address obtaining module 10 is configured to sequentially obtain the lookup table addresses incremented by a preset step length under the action of the working clock, and send the lookup table addresses into the memory 20. The lookup table address is usually represented by binary, and the value of the first acquired lookup table address is preferably 0. The difference between the lookup address obtained each time and the lookup address obtained last time is a preset step size, and the preset step size may be set according to actual needs, for example, 1.
The memory 20 is configured to output a second number of current sine values and current cosine values for forming the sine signal and the cosine signal, respectively, in parallel, each time a look-up table address is entered; the phase of the sine value and the phase of the cosine value output each time are increased progressively by a preset phase increment, the sine value and the cosine value output twice in the adjacent time are continuous in phase, and the preset phase increment is determined according to a preset frequency, the first number, the second number and the frequency of the working clock.
In this case, for example, the sine value of each output is a preset frequency, but the phase is continuous. When the first lookup address is sent, the memory 20 may sequentially read the second number of sine values from the sine value with the smallest phase in the order from small to large, where the phase difference between the sine values read in two adjacent times is a preset phase increment, and then the memory 20 outputs the read second number of sine values in parallel. The memory 20 then does this every time a look-up table address is entered, and the phase difference between the first sine value of the subsequent read and the last sine value of the previous read is also a predetermined phase increment.
Similarly, the frequency of the cosine value output each time is a preset frequency, and the phase is continuous. The second number of sine values forms a digitized sine signal and the second number of cosine values forms a digitized cosine signal, which are continuously generated as long as the table lookup address is continuously fed into the memory 20.
The preset frequency, the first number, the second number and the frequency of the working clock are set according to actual needs. The preset frequencies are the frequencies of the sine signal and the cosine signal. The first number is the total number of sine or cosine values stored by the memory and the second number is a fraction of the total number of sine or cosine values, and thus the second number is less than or equal to the first number. The frequency of the operating clock should not exceed the maximum operating frequency of the FPGA. The frequency of the operating clock and the value of the second number are related to the sampling rate, the product of which is equivalent to the sampling rate, e.g. the frequency of the operating clock is set to 200MHz at a sampling rate of 1.6GHz, and the second number is 8. The sampling rate is determined by the control requirements of the qubit. According to the Nyquist sampling law, the ratio of the preset frequency to the sampling frequency is at most 1:2, that is, the preset frequency can theoretically reach 800MHz, so that a sine and cosine signal with a higher frequency is realized in the FPGA.
Referring to fig. 2, the memory 20 provides two identical lookup tables LUT, which respectively stores sine value and cosine value, wherein the lookup address bit number of the lookup table LUT is a first bit number a, the data bit number of the lookup table LUT is a second bit number B, and the phase of the lookup table LUT is continuousThe sine and cosine values of the number correspond to the same look-up address, where 2 A The product of which is equal to 2 B . The lookup address is incremented from 0.
Wherein one look-up table LUT stores a first number of sine values and the other look-up table LUT stores a first number of cosine values, the first number being equal to 2 A 。2 A The sine or cosine value is required to pass 2 B The addressing of a single lookup address is complete and the second number of bits B is less than the first number of bits a, then a lookup address is required to address a second number of sine or cosine values simultaneously. The phase difference between the phases of the two sine values and the phases of the cosine values adjacent to the phases of the second number of sine values and the cosine values corresponding to the same lookup address is a preset phase increment, and the phase difference between the sine value and the cosine value with the largest phase in the second number of sine values and cosine values corresponding to the previous lookup address and the phase difference between the sine value and the cosine value with the smallest phase in the second number of sine values and cosine values corresponding to the next lookup address are also preset phase increments.
The storage location of the first number of sine or cosine values in the look-up table LUT may be flexibly adjusted. In an application scenario of the embodiment of the invention, the look-up table LUT has a second number of sub-tables, each storing a number of sine or cosine values of 2 B The same data bit of each sub-table corresponds to the same table look-up address, the sine value or the cosine value stored by the same data bit is continuous in phase, and the phase difference of the sine value or the cosine value stored by two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
Wherein the number of sub-tables is also equal to the second number, so that each sub-table only needs to store a number of 2 B Such that the total number of sine or cosine values stored by all the sub-tables equals the first number. Each sine value or cosine value in the sub-table occupies one data bit, the number of table look-up address bits corresponding to the data bits in the sub-table is a second number B, the 1 st table look-up address corresponds to the 1 st data bit of each sub-table, namely, the 1 st numberAccording to sine value or cosine value stored in the data bit, the 2 nd table lookup address corresponds to the 2 nd data bit of each sub-table, the 3 rd table lookup address corresponds to the 3 rd data bit of each sub-table, and so on, the 2 nd table lookup address B Each table lookup address corresponds to the 2 nd of each sub-table B And a data bit.
And the sine or cosine values stored for the same data bit of each sub-table are consecutive in phase, i.e. the difference in phase is a preset phase increment. The phase difference between the sine value and the cosine value stored in two adjacent data bits in the same sub-table is a preset phase increment of a second quantity, namely the product of the second quantity and the preset phase increment.
In this embodiment, the preset phase increment is:
wherein N represents a first number with a value range of [1,2 B ]C denotes a second number, f out Representing a predetermined frequency, f S Representing the frequency of the operating clock.
Further, the sinusoidal signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset. In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offsets of the sine signal and the cosine signal are the same.
Each sub-table is now described with reference to FIG. 3And (6) detailed description. Referring to fig. 3, each sine value of the sine signal expressed by the above formula is stored in 8 sub-tables of a look-up table LUT. The number of sine values, i.e. the first number N, is equal to 2 17 The number of sub-tables, i.e. the second number 8,c, is a value in the range of [0,7]Respectively corresponding to 8 sub-tables, the number of bits of the table lookup address is 14, and the value range of the table lookup address is [0,2 ] 14 －1]For the convenience of calculation, a is 1,
and b is taken to be 0. The sine values stored for each sub-table are as follows:
the sine value stored by each data bit of the 1 st sub-table is sin [0*2 pi × PINC/N]、sin[8*2π*PINC/N]、sin[16*2π*PINC/N]、…、sin[8*(2 14 -2)*2π*PINC/N]、sin[8*(2 14 -1)*2π*PINC/N]；
The sine value stored by each data bit of the 2 nd sub-table is sin [1*2 pi × PINC/N]、sin[9*2π*PINC/N]、sin[17*2π*PINC/N]、…、sin[(8*(2 14 -2)+1)*2π*PINC/N]、sin[(8*(2 14 -1)+1)*2π*PINC/N]；
The sine value stored by each data bit of the 3 rd sub-table is sin [2*2 pi × PINC/N]、sin[10*2π*PINC/N]、sin[18*2π*PINC/N]、…、sin[(8*(2 14 -2)+2)*2π*PINC/N]、sin[(8*(2 14 -1)+2)*2π*PINC/N]；
By analogy, each data bit of the 8 th sub-table stores sin values in turn sin [7*2 pi × PINC/N]、sin[15*2π*PINC/N]、sin[23*2π*PINC/N]、…、sin[(8*(2 14 -2)+7)*2π*PINC/N]、sin[(8*(2 14 -1)+7)*2π*PINC/N]。
It can be seen that the sine values stored in two adjacent data bits in each sub-table differ in phase by 8 p PINC.
The sinusoidal signal is generated as follows:
when the 1 st lookup table address is fed, namely N =0, the 8 sub-tables respectively output sin [0*2 pi × PINC/N ], sin [1*2 pi × PINC/N ], sin [2*2 pi × PINC/N ], … and sin [7*2 pi × PINC/N ];
when the 2 nd lookup address is sent, namely N =1, the 8 sub-tables respectively output sin [8*2 pi × PINC/N ], sin [9*2 pi × PINC/N ], sin [10 × 2 pi × PINC/N ], … and sin [15 × 2 pi × PINC/N ];
when the 3 rd lookup address is sent, namely N =2, the 8 sub-tables respectively output sin [16 × 2 pi × PINC/N ], sin [17 × 2 pi × PINC/N ], sin [18 × 2 pi × PINC/N ], … and sin [23 × 2 pi × PINC/N ];
by analogy, when sending into the 2 nd 14 Individual table look-up addresses, i.e. n =2 14 When the output signal is-1, 8 sub-tables respectively output sin [8 x (2) 14 -1)*2π*PINC/N]、sin[(8*(2 14 -1)+1)*2π*PINC/N]、sin[(8*(2 14 -1)+2)*2π*PINC/N]、…、sin[(8*(2 14 -1)+7)*2π*PINC/N]。
It can be seen that the phase of the 8 sine values output by each of the 8 sub-tables is incremented by PINC, and the phase of the last sine value output by the previous time differs from the phase of the first sine value output by the next time by PINC.
The lookup address may be generated by internal pre-storage, internal generation, or external input.
If the input is external input, in this embodiment, the address obtaining module 10 is specifically configured to sequentially receive externally input table lookup addresses that are incremented by a preset step size under the action of the working clock, and send the table lookup addresses to the memory 20.
Referring to fig. 4, if the signal is pre-stored internally, a second embodiment of the present invention provides a sine and cosine signal generator, which includes all the technical features of the first embodiment, but the difference is that the sine and cosine signal generator of the present embodiment further includes an address pre-storing module 30, and the address pre-storing module 30 is configured to pre-store a table lookup address incremented by a preset step size. The address obtaining module 10 obtains the table lookup address from the address pre-storing module 30.
Referring to fig. 5, if the internal generation is performed, a third embodiment of the present invention provides a sine and cosine signal generator, which includes all the technical features of the first embodiment, but the difference is that the sine and cosine signal generator of the present embodiment further includes an address generating module 40, and the address generating module 40 is configured to generate a table lookup address that is incremented by a preset step length. The address obtaining module 10 obtains the table lookup address from the address generating module 40. Further, the address generating module 40 is specifically configured to perform accumulation from zero to generate a lookup table address incremented by a preset step size.
Through the mode, the sine and cosine signal generator sequentially acquires the table lookup addresses under the action of the working clock and sends the table lookup addresses to the memory, the memory stores the sine values and the cosine values of the first quantity of preset frequencies, the memory is configured to output the current sine values and the current cosine values of the second quantity in parallel when one table lookup address is sent, the output sine values and the output cosine values are used for forming sine signals and cosine signals respectively, the preset frequency is the frequency of the sine and cosine signals, and the product of the frequency of the working clock and the second quantity is equivalent to the sampling frequency.
The embodiment of the invention also provides a memory, wherein the memory stores a first number of sine values and cosine values of preset frequency, and the memory is configured to respectively output a second number of current sine values and current cosine values which are used for respectively forming sine signals and cosine signals in parallel when a table look-up address is sent in each table look-up address; the table lookup address is sent under the action of a working clock, the table lookup address sent each time is increased in a preset step length, the phase of the sine value and the cosine value output each time is increased in a preset phase increment, the sine value and the cosine value output two adjacent times are continuous in phase, and the preset phase increment is determined according to preset frequency, the first number, the second number and the frequency of the working clock.
In some embodiments, the memory provides two identical lookup tables, the two lookup tables respectively store sine values and cosine values, the number of lookup address bits of the lookup tables is a first number a, the number of data bits of the lookup tables is a second number B, and the sine values and cosine values of the second number with continuous phases correspond to the same lookup address, wherein 2 A The product of which is equal to 2 B 。
In some embodiments, the look-up table has a second number of sub-tables, each sub-table storing a number of sine or cosine values of 2 B The same data bit of each sub-table corresponds to the same table look-up address, the sine value or the cosine value stored in the same data bit is continuous in phase, and the phase difference of the sine value or the cosine value stored in two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
In some embodiments, the preset phase increment is:
wherein N represents a first number with a value range of [1,2 B ]C denotes a second number, f out Representing a predetermined frequency, f S Representing the frequency of the operating clock.
Further, the sinusoidal signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset. In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offsets of the sine signal and the cosine signal are the same.
For the description of the memory, reference may be made to the description of the sine and cosine signal generator in the foregoing embodiment, and the memory has the same technical features as the memory 20 of the sine and cosine signal generator in the foregoing embodiment, which is not described herein again.
The embodiment of the invention also provides a quantum computer control system, which comprises the sine and cosine signal generator provided by the embodiment or the memory provided by the embodiment.
It should be noted that, besides being applied to a quantum computer control system, the sine and cosine generator provided in the foregoing embodiment or the memory provided in the foregoing embodiment is also applicable to any other application scenarios with sine and cosine signal generation requirement, and the present invention is not limited to this.
In the description herein, references to the description of "one embodiment," "some embodiments," "an example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (17)
1. The sine and cosine signal generator is used for an FPGA and is characterized by comprising an address acquisition module and a memory, wherein the memory stores sine values and cosine values of a first number of preset frequencies:
the address acquisition module is used for sequentially acquiring the table look-up addresses increased by a preset step length under the action of a working clock and sending the table look-up addresses into the memory;
the memory is configured to output a second number of current sine values and current cosine values for forming the sine signal and the cosine signal, respectively, in parallel, each time a lookup address is sent in;
the phase of the sine value and the phase of the cosine value output each time are increased progressively by a preset phase increment, the sine value and the cosine value output twice in a neighboring mode are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first number, the second number and the frequency of the working clock.
2. The sine-cosine signal generator of claim 1, wherein the memory provides two identical lookup tables, the two lookup tables respectively store sine values and cosine values, the lookup address bits of the lookup tables are a first number of bits a, the data bits of the lookup tables are a second number of bits B, and the sine values and cosine values of a second number of consecutive phases correspond to the same lookup address, wherein 2 A The product of which is equal to 2 B 。
3. Sine-cosine signal generator according to claim 2, characterized in that the look-up table has a second number of sub-tables, each storing a number of sine or cosine values of 2 B The same data bit of each sub-table corresponds to the same table look-up address, the sine value or the cosine value stored in the same data bit is continuous in phase, and the phase difference of the sine value or the cosine value stored in two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
4. The sine-cosine signal generator of claim 3, wherein the predetermined phase increment is:
wherein N represents the first number and has a value range of [1,2 B ]C represents said second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock.
5. The sine-cosine signal generator of claim 4, wherein the sine signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
6. The sine-cosine signal generator of claim 5, wherein the amplitude, initial phase and offset of the sine signal and the cosine signal are the same.
7. The sine-cosine signal generator of claim 1, wherein the address obtaining module is specifically configured to sequentially receive externally input lookup table addresses incremented by a preset step length under the action of a working clock, and send the lookup table addresses to the memory.
8. The sine-cosine signal generator of claim 1, further comprising an address pre-storing module, wherein the address pre-storing module is configured to pre-store a table look-up address that is incremented by a preset step size.
9. The sine-cosine signal generator of claim 1, further comprising an address generation module for generating a lookup table address that is incremented by a preset step size.
10. The sin-cos signal generator of claim 9, wherein the address generation module is specifically configured to accumulate from zero to generate the lookup table address increased by a preset step size.
11. A memory, wherein the memory stores a first number of sine values and cosine values of a preset frequency, and the memory is configured to output a second number of current sine values and current cosine values for forming a sine signal and a cosine signal, respectively, in parallel, each time a lookup address is entered;
the table lookup address is sent under the action of a working clock, the table lookup address sent each time is increased in a preset step length, the phase of the sine value and the cosine value output each time is increased in a preset phase increment, the sine value and the cosine value output two adjacent times are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first number, the second number and the frequency of the working clock.
12. The memory of claim 11, wherein the memory provides two identical lookup tables, the two lookup tables respectively store sine values and cosine values, the lookup address bits of the lookup tables are a first number of bits a, the data bits of the lookup tables are a second number of bits B, and the phase-sequential second number of sine values and cosine values correspond to the same lookup address, wherein 2 A The product of which is equal to 2 B 。
13. The memory of claim 12 wherein said lookup table has a second number of sub-tables, each of said sub-tables storing a number of sine or cosine values of 2 B The same data bit of each sub-table corresponds to the same table look-up address and is storedThe sine values or the cosine values are continuous in phase, and the phase difference of the sine values or the cosine values stored in two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
14. The memory of claim 13, wherein the predetermined phase increment is:
wherein N represents the first number and has a value range of [1,2 B ]C represents said second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock.
15. The memory of claim 14, wherein the sinusoidal signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
16. The memory of claim 15, wherein the sine signal and the cosine signal have the same amplitude, initial phase and offset.
17. A quantum computer control system comprising a sine-cosine signal generator as claimed in any one of claims 1 to 10 or a memory as claimed in any one of claims 11 to 16.
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| PCT/CN2023/073345 WO2023143447A1 (en) | 2022-01-27 | 2023-01-20 | Device for generating qubit control signal and quantum computer control system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023143447A1 (en) * | 2022-01-27 | 2023-08-03 | 本源量子计算科技（合肥）股份有限公司 | Device for generating qubit control signal and quantum computer control system |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997018623A1 (en) * | 1995-11-15 | 1997-05-22 | Samsung Electronics Co., Ltd. | System, method and program product for generating a sine or cosine waveform utilizing combined look-up tables |
| US5954787A (en) * | 1996-12-26 | 1999-09-21 | Daewoo Electronics Co., Ltd. | Method of generating sine/cosine function and apparatus using the same for use in digital signal processor |
| JP2000076667A (en) * | 1998-09-01 | 2000-03-14 | Sony Corp | Phase difference detection circuit and its method, phase comparator having the phase difference detection circuit, phase locked loop circuit having the phase difference comparation circuit and optical disk drive servo device using the phase locked loop circuit |
| CN101017383A (en) * | 2006-11-01 | 2007-08-15 | 王文华 | High speed arbitrary waveform generator based on FPGA |
| US20080109503A1 (en) * | 2006-09-29 | 2008-05-08 | Teradyne, Inc. | Sine wave generator with dual port look-up table |
| CN101190137A (en) * | 2006-11-27 | 2008-06-04 | 深圳迈瑞生物医疗电子股份有限公司 | Real time digital quadrature demodulation method and device used in ultrasonic imaging system |
| US20090157783A1 (en) * | 2007-12-17 | 2009-06-18 | Electronics And Telecommunications Research Institute | Numerically-controlled oscillator capable of generating cosine signal and sine signal only using cosine look up table and operating method of the numerically-controlled oscillator |
| CN103117731A (en) * | 2013-01-22 | 2013-05-22 | 上海航天测控通信研究所 | Sinusoidal signal generator implementation method based on field programmable gate array (FPGA) and sinusoidal signal generator implementation device |
| CN206193081U (en) * | 2016-11-29 | 2017-05-24 | 武汉大学 | Signal source, oscilloscope , universal meter all -in -one based on FPGA |
| WO2019192196A1 (en) * | 2018-04-02 | 2019-10-10 | 广州数控设备有限公司 | Pseudo-random code channel grating ruler and reading method therefor |
-
2022
- 2022-01-27 CN CN202210103517.8A patent/CN115469711A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997018623A1 (en) * | 1995-11-15 | 1997-05-22 | Samsung Electronics Co., Ltd. | System, method and program product for generating a sine or cosine waveform utilizing combined look-up tables |
| US5954787A (en) * | 1996-12-26 | 1999-09-21 | Daewoo Electronics Co., Ltd. | Method of generating sine/cosine function and apparatus using the same for use in digital signal processor |
| JP2000076667A (en) * | 1998-09-01 | 2000-03-14 | Sony Corp | Phase difference detection circuit and its method, phase comparator having the phase difference detection circuit, phase locked loop circuit having the phase difference comparation circuit and optical disk drive servo device using the phase locked loop circuit |
| US20080109503A1 (en) * | 2006-09-29 | 2008-05-08 | Teradyne, Inc. | Sine wave generator with dual port look-up table |
| CN101017383A (en) * | 2006-11-01 | 2007-08-15 | 王文华 | High speed arbitrary waveform generator based on FPGA |
| CN101190137A (en) * | 2006-11-27 | 2008-06-04 | 深圳迈瑞生物医疗电子股份有限公司 | Real time digital quadrature demodulation method and device used in ultrasonic imaging system |
| US20090157783A1 (en) * | 2007-12-17 | 2009-06-18 | Electronics And Telecommunications Research Institute | Numerically-controlled oscillator capable of generating cosine signal and sine signal only using cosine look up table and operating method of the numerically-controlled oscillator |
| CN103117731A (en) * | 2013-01-22 | 2013-05-22 | 上海航天测控通信研究所 | Sinusoidal signal generator implementation method based on field programmable gate array (FPGA) and sinusoidal signal generator implementation device |
| CN206193081U (en) * | 2016-11-29 | 2017-05-24 | 武汉大学 | Signal source, oscilloscope , universal meter all -in -one based on FPGA |
| WO2019192196A1 (en) * | 2018-04-02 | 2019-10-10 | 广州数控设备有限公司 | Pseudo-random code channel grating ruler and reading method therefor |
Non-Patent Citations (2)
| Title |
|---|
| Z. NOUMAN 等: "Design and Implementation A Digital Sine-Cosine Generator Based FPGA", 《INTERNATIONAL JOURNAL OF ENGINEERING AND ADVANCED TECHNOLOGY》, 30 June 2013 (2013-06-30), pages 304 - 307 * |
| 张旭炜 等: "基于FPGA的幅度和相位可调信号发生器", 《光通信技术》, no. 1, 18 March 2014 (2014-03-18), pages 9 - 11 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023143447A1 (en) * | 2022-01-27 | 2023-08-03 | 本源量子计算科技（合肥）股份有限公司 | Device for generating qubit control signal and quantum computer control system |
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