CN115456182A - Device for generating quantum bit control signal and quantum computer control system - Google Patents
Device for generating quantum bit control signal and quantum computer control system Download PDFInfo
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Abstract
The invention discloses a device for generating a quantum bit control signal and a quantum computer control system. The device includes: the sine and cosine signal generator is used for respectively outputting sine signals and cosine signals with the same frequency of a preset path number in parallel under the action of a working clock; the envelope generator is used for determining the envelope of a target control signal from a pre-stored corresponding table according to the target single-bit revolving door, respectively outputting envelope in-phase components and envelope orthogonal components of a preset path number in parallel under the action of a working clock, and the corresponding table stores control signals corresponding to different single-bit revolving doors; and the signal mixer is used for multiplying the sine signal with the preset path number with the envelope in-phase component and the cosine signal with the preset path number with the envelope orthogonal component under the action of a working clock, and adding the two multiplication results to obtain the target control signal, so that the phase difference between the target control signal and the local oscillator signal is consistent. The invention can automatically compensate the phase of the control signal when the same single-bit revolving door is realized.
Description
Technical Field
The present invention relates to the field of quantum computing, and in particular, to a device for generating a qubit control signal and a quantum computer control system.
Background
The single-bit revolving gate operation on the Qubit (Qubit) is realized by applying a steering signal to the Qubit, the phase of the steering signal determines the angle of the rotation axis of the Qubit state vector in the bloch sphere in the XY plane, and the amplitude of the steering signal determines the rotation angle of the state vector around the rotation axis. Since the signal applied to the qubit is a radio frequency signal (RF) and the initially generated steering signal is an intermediate frequency signal (IF), the intermediate frequency steering signal needs to be mixed with a local oscillator signal (LO) to obtain the radio frequency steering signal.
However, the inventor of the present application found in long-term research that, when a plurality of identical single-bit revolving doors are continuously implemented, a situation may occur where a phase difference between a steering signal and a local oscillator signal of intermediate frequencies of two preceding and following single-bit revolving doors is inconsistent, resulting in that the two preceding and following single-bit revolving doors are different. In order to obtain the same single-bit revolving gate, it is conventional to change the phase of the intermediate frequency control signal of the following single-bit revolving gate. However, different control signals are generated to realize the same single-bit revolving gate, which causes that the control of the qubit is difficult in units of single-bit revolving gates.
Disclosure of Invention
The invention aims to provide a device for generating a quantum bit control signal and a quantum computer control system, which are used for solving the problem that different control signals are generated when the same single-bit revolving gate is realized in the prior art, and can automatically compensate the phase of the control signal when the same single-bit revolving gate is realized, so that the control of quantum bits by taking the single-bit revolving gate as a unit is realized.
To solve the above technical problem, the present invention provides an apparatus for generating a qubit steering signal, wherein the steering signal is mixed with a local oscillator signal, and the mixed signal is changed from an intermediate frequency to a radio frequency, and then acts on a qubit to implement a single-bit revolving gate, comprising:
the sine and cosine signal generator is used for respectively outputting sine signals and cosine signals with the same frequency of a preset path number in parallel under the action of a working clock;
the envelope generator is used for determining the envelope of a target control signal from a pre-stored corresponding table according to the target single-bit revolving gate, and respectively outputting envelope in-phase components and envelope quadrature components of a preset path number in parallel under the action of the working clock, wherein the corresponding table stores control signals corresponding to different single-bit revolving gates;
and the signal mixer is used for multiplying the sine signal with the preset path number by the envelope in-phase component and the cosine signal with the preset path number by the envelope orthogonal component under the action of the working clock, and adding the two multiplication results to obtain the target control signal, so that the phase difference between the target control signal and the local oscillator signal is consistent.
Preferably, the device further comprises a parallel-serial conversion module:
the signal mixer is also used for dividing the target control signal into at least one path of parallel output;
the parallel-serial conversion module is used for converting at least one path of parallel output target control signals into serial signals under the action of a serial clock, wherein the frequency of the serial clock is not lower than that of the working clock.
Preferably, the sine and cosine signal generator includes an address acquisition module and a memory, where the memory stores sine values and cosine values of a first number of preset frequencies:
the address acquisition module is used for sequentially acquiring the table lookup addresses increased by the preset step length under the action of a working clock and sending the table lookup addresses into the memory;
the memory is configured to output a second number of current sine values and current cosine values for forming the sine signal and the cosine signal, respectively, in parallel, each time a lookup address is sent in;
the second quantity is the preset number, the phase of the sine value and the phase of the cosine value output each time are increased in a preset phase increment, the sine value and the cosine value output twice in adjacent times are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock.
Preferably, the memory provides two identical lookup tables, the two lookup tables store sine values and cosine values respectively, the lookup address bits of the lookup tables are a first bit a, the data bits of the lookup tables are a second bit B, and the sine values and cosine values of a second number with continuous phases correspond to the same lookup address, wherein 2 A The product of which is equal to 2 B 。
Preferably, the look-up table has a second number of sub-tables, each of which stores a number of sine or cosine values of 2 B The same data bit of each sub-table corresponds to the same table look-up address, the sine value or the cosine value stored in the same data bit is continuous in phase, and the phase difference of the sine value or the cosine value stored in two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
Preferably, the preset phase increment is as follows:
wherein N represents the first number and has a value range of [1,2 B ]C represents said second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock.
Preferably, the sinusoidal signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
Preferably, the sine and cosine signal generator includes an address acquisition module and a memory storing trigonometric function values of at least one quarter cycle, the number of the trigonometric function values of one cycle is a first number, and the number of the memory is a second number;
the address acquisition module is used for sequentially acquiring a plurality of paths of table lookup addresses under the action of a working clock and respectively sending the table lookup addresses into a second number of memories, wherein the table lookup addresses of two adjacent paths at the same moment differ by a preset phase increment, and the two adjacent table lookup addresses of the same path differ by a second number multiple of the preset phase increment;
the memory is configured to output a current sine value and a current cosine value to respectively form a sine signal and a cosine signal of a preset frequency when a table look-up address is sent in each time;
and the second quantity is the preset number of paths, and the preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock.
Preferably, the memory stores trigonometric values that are at least a quarter cycle sine value, at least a quarter cycle cosine value or at least a quarter cycle sine value and cosine value.
Preferably, the memory is configured to check whether a corresponding sine value or cosine value is stored in a current lookup address every time a lookup address is sent in, output a stored current sine value and a stored current cosine value when the corresponding sine value or cosine value is stored, respectively form a sine signal and a cosine signal of a preset frequency, and calculate a corresponding sine value or cosine value according to the periodicity of the sine value or cosine value when the corresponding sine value or cosine value is not stored, output the calculated current sine value and current cosine value, and respectively form a sine signal and a cosine signal of a preset frequency.
Preferably, the memory provides a lookup table, the lookup table stores a sine value of a quarter cycle, and the lookup address bit number of the lookup table is a first bit number a, wherein 2 A Equal to the first number.
Preferably, the preset phase increment is as follows:
wherein N represents the first number and c represents the second numberAmount f out Representing said predetermined frequency, f S Representing the frequency of the operating clock, round () representing a rounding function.
Preferably, the sinusoidal signal is:
the cosine signal is:
wherein n × PINC represents the value of the lookup table address, and the value range of n is [0,2 A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
Preferably, the current sine value output by the memory is:
the current cosine value output by the memory is:
wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 ] A －1]。
Preferably, the amplitudes, initial phases and offset distances of the sine signal and the cosine signal are the same.
In order to solve the above technical problem, the present invention further provides a qubit control system including any one of the foregoing devices for generating qubit control signals.
Preferably, the mobile terminal further comprises a mixer, and the mixer is configured to mix the target steering signal with the local oscillator signal, so that the target steering signal is changed from an intermediate frequency to a radio frequency.
Preferably, the target steering system further comprises a digital-to-analog converter, and the digital-to-analog converter is configured to perform digital-to-analog conversion on the target steering signal before the target steering signal is mixed.
Different from the situation of the prior art, the device for generating the qubit control signal provided by the invention respectively outputs the sine signal and the cosine signal with the same frequency of the preset path number in parallel under the action of the working clock, determines the envelope of the target control signal according to the target single-bit revolving door, respectively outputs the envelope in-phase component and the envelope orthogonal component of the preset path number in parallel, multiplies the sine signal with the envelope in-phase component and the cosine signal with the preset path number with the envelope orthogonal component, and adds the two multiplication results to obtain the target control signal, so that the phase difference between the target control signal and the local oscillator signal is consistent, the phase of the control signal can be automatically compensated when the same single-bit revolving door is realized, the qubit is controlled by taking the single-bit revolving door as a unit, and the control signal stored in the corresponding table cannot change, so that the compiling and pre-storing of the control signal are facilitated, and the operation complexity of the qubit is simplified.
The quantum computer control system provided by the invention and the device for generating the quantum bit control signal belong to the same inventive concept, so that the quantum computer control system has the same beneficial effects, and the description is omitted.
Drawings
Fig. 1 is a schematic structural diagram of an apparatus for generating a qubit steering signal according to a first embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an apparatus for generating a qubit steering signal according to a second embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a sine-cosine signal generator of an apparatus for generating a qubit steering signal according to a third embodiment of the present invention.
Fig. 4 is a schematic diagram of a data structure of a lookup table provided in a memory of the sine and cosine signal generator in the third embodiment.
Fig. 5 is a diagram showing a data structure of the third embodiment in which each sub-table of the lookup table stores a sine value.
Fig. 6 is a schematic structural diagram of a sine-cosine signal generator of an apparatus for generating a qubit steering signal according to a fourth embodiment of the present invention.
Fig. 7 is a diagram illustrating a data structure of a lookup table provided in a memory of a sine and cosine signal generator in the fourth embodiment.
Fig. 8 is a schematic structural diagram of a quantum computer control system according to a fifth embodiment of the present invention.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Referring to fig. 1, a first embodiment of the present invention provides an apparatus for generating a qubit manipulation signal. The frequency mixing of the control signal and the local oscillator signal is changed from intermediate frequency to radio frequency, and then the control signal and the local oscillator signal act on the qubit to realize the single-bit revolving door. The apparatus of the present embodiment comprises a sine-cosine signal generator 1, an envelope generator 2 and a signal mixer 3.
The sine and cosine signal generator 1 is used for respectively outputting sine signals and cosine signals with the same frequency of a preset path number in parallel under the action of a working clock. The clock of each path of sine signal in the preset path number of sine signals is a working clock, and the clock of each path of cosine signal in the preset path number of cosine signals is a working clock.
The envelope generator 2 is used for determining the envelope of the target control signal from a pre-stored corresponding table according to the target single-bit revolving door, and respectively outputting envelope in-phase components and envelope quadrature components of a preset path number in parallel under the action of a working clock, wherein the corresponding table stores control signals corresponding to different single-bit revolving doors. The clock of each path of envelope in-phase component in the envelope in-phase components of the preset path number is a working clock, and the clock of each path of envelope orthogonal component in the envelope orthogonal components of the preset path number is a working clock. The mapping table can store parameters of the control signal of the single-bit turnstile, which form the control signal, from which the envelope of the control signal can be determined. In this embodiment, the single bit revolving gate is preferably a single bit X gate or a single bit Y gate.
The signal mixer 3 is configured to multiply the sine signal of the preset number of paths by the envelope in-phase component and the cosine signal of the preset number of paths by the envelope orthogonal component under the action of the working clock, and add the two multiplication results to obtain a target control signal, so that the phase difference between the target control signal and the local oscillator signal is consistent. The sine signals of the preset number of paths are multiplied by the envelope in-phase component of the preset number of paths, the cosine signals of the preset number of paths are multiplied by the envelope orthogonal component of the preset number of paths, the conversion from envelope to wave packet is realized, the two multiplication results are added to realize the phase compensation of the control signals, so that the phase difference of the target control signals and the local oscillation signals is consistent, and the same single-bit revolving door can be continuously realized.
Wherein, the control signal that single bit revolving door corresponds is:
IF＝ε’ I (t)cos(ω IF t)+ε’ Q (t)sin(ω IF t)
wherein is epsilon' I (t) represents the envelope in-phase component, ε ', of the steering signal' Q (t) represents the envelope quadrature component of the steering signal, ω IF Representing the phase, sin (ω), of the steering signal IF t) represents a sinusoidal signal, cos (ω) IF t) represents a cosine signal.
The envelope in-phase component of the steering signal is:
ε’ I (t)＝ε I (t)cos(φ 0 +δt)+ε Q (t)sin(φ 0 +δt)
the envelope quadrature component of the steering signal is:
ε’ Q (t)＝ε Q (t)cos(φ 0 +δt)-ε I (t)sin(φ 0 +δt)
wherein epsilon I (t)、ε Q (t)、φ 0 Delta denotes the parameter phi of the control signal 0 Determines the angle and direction of the rotation axis in the bloch sphere about which the qubit state vector needs to be rotated. Epsilon I (t) and ε Q (t) are respectively represented as follows:
in a specific application, the parameters of the control signal of the single-bit revolving door are as follows: omega IF Phi of 0-20 × 2 π MHz, and 600 × 2 π MHz, delta 0 The values of (A) are respectively 0, pi,
A I The values of (a) are respectively 0.3 and 1,T are 20ns, eta = -240 multiplied by 2 pi MHz, and alpha is 1. Phi is a unit of 0 When =0, the axis of rotation is the X-axis in the Bloch sphere and the direction is the X-axisPositive direction, phi 0 Where = pi, the axis of rotation is the X-axis in a bloch sphere, and the direction is the X-axis negative direction,
when the rotation axis is the Y axis of the Bloch sphere, and the direction is the positive direction of the Y axis,
when the axis of rotation is the Y axis in a Bloch sphere, and the direction is the negative Y axis direction. A. The I When =0.3, the rotation angle of the qubit state vector is 90 degrees, a I And =1, the rotation angle of the qubit state vector is 180 degrees.
When the single-bit revolving door needs to be realized, only the parameters corresponding to the target single-bit revolving door need to be determined according to actual needs, and the envelope of the target control signal can be determined according to the determined parameters. The envelope in-phase component and the envelope orthogonal component are multiplied by the sine signal and the cosine signal respectively, and the two multiplication results are added to obtain a wave packet signal, namely a target control signal, wherein the phase difference of the target control signal is consistent with that of the local oscillator signal, so that a plurality of same target single-bit revolving doors can be continuously realized. Because the control signal stored in the corresponding table can not be changed, the compiling and the pre-storing of the control signal are facilitated, and the operation complexity of the quantum bit is simplified.
Referring to fig. 2, a second embodiment of the present invention provides an apparatus for generating a qubit steering signal. The frequency mixing of the control signal and the local oscillator signal is changed from intermediate frequency to radio frequency, and then the control signal and the local oscillator signal act on the qubit to realize the single-bit revolving door. The apparatus of this embodiment has all the technical features of the apparatus of the first embodiment, except that the apparatus of this embodiment further includes a parallel-to-serial conversion module 4, and the signal mixer 3 is further configured to divide the target control signal into at least one path of parallel output; the parallel-serial conversion module 4 is configured to convert at least one path of target control signals output in parallel into a serial signal under the action of a serial clock, where the frequency of the serial clock is not lower than the frequency of the working clock.
The sine signal and the cosine signal generated by the sine signal generator are usually digital signals, so that digital-to-analog conversion needs to be performed on the target control signal, and parallel-to-serial processing needs to be performed on the target control signal before digital-to-analog conversion.
The sine signal generator generates sine signals and cosine signals in a digital signal form, and the sine signals and the cosine signals are mostly realized in the FPGA, and the invention adopts two modes to generate sine and cosine signals with higher frequency in the FPGA in consideration of the limited highest working frequency of the FPGA.
For the first way, please refer to fig. 3, the sine and cosine signal generator 1 is used in the FPGA and can generate a sine and cosine signal with a higher frequency in the FPGA. The sine and cosine signal generator 1 comprises an address acquisition module 10A and a memory 20A, wherein the memory 20A stores sine values and cosine values of a first number of preset frequencies.
The address obtaining module 10A is configured to sequentially obtain the lookup table addresses incremented by the preset step length under the action of the working clock, and send the lookup table addresses into the memory 20A. The lookup table address is usually represented by binary, and the value of the first acquired lookup table address is preferably 0. The difference between the lookup address obtained each time and the lookup address obtained last time is a preset step size, and the preset step size may be set according to actual needs, for example, 1. The table lookup address can be obtained by internal pre-storage, internal generation or external input.
The memory 20A is configured to output a second number of current sine values and current cosine values for forming the sine signal and the cosine signal, respectively, in parallel, each time a look-up table address is entered; the second quantity is a preset number, the phase of the sine value and the phase of the cosine value output each time are increased progressively by a preset phase increment, the sine value and the cosine value output twice in adjacent times are continuous in phase, and the preset phase increment is determined according to a preset frequency, the first quantity, the second quantity and the frequency of the working clock.
In this case, for example, the sine value of each output is a preset frequency, but the phase is continuous. When the first lookup address is sent, the memory 20A may sequentially read the second number of sine values from the sine value with the smallest phase in the order from small to large, where the difference between the phases of the sine values read in two adjacent times is a preset phase increment, and then the memory 20A outputs the read second number of sine values in parallel. The memory 20A then does so every time a lookup address is entered, and the phase difference between the first sine value read at a subsequent time and the last sine value read at a previous time is also a predetermined phase increment.
Similarly, the frequency of the cosine value output each time is a preset frequency, and the phase is continuous. The second number of sine values forms a digitized sine signal and the second number of cosine values forms a digitized cosine signal, which are continuously generated as long as the table lookup address is continuously fed into the memory 20A.
The preset frequency, the first number, the second number and the frequency of the working clock are set according to actual needs. The preset frequencies are the frequencies of the sine signal and the cosine signal. The first number is the total number of sine or cosine values stored by the memory and the second number is a fraction of the total number of sine or cosine values, and thus the second number is less than or equal to the first number. The frequency of the operating clock should not exceed the maximum operating frequency of the FPGA. The frequency of the operating clock and the value of the second number are related to the sampling rate, the product of which is equivalent to the sampling rate, e.g. the frequency of the operating clock is set to 200MHz at a sampling rate of 1.6GHz, and the second number is 8. The sampling rate is determined by the control requirements of the qubit. According to the Nyquist sampling law, the ratio of the preset frequency to the sampling frequency is at most 1:2, that is, the preset frequency can theoretically reach 800MHz, so that a sine and cosine signal with a higher frequency is realized in the FPGA.
Referring to fig. 4, the memory 20A provides two identical lookup tables LUT1, where the two lookup tables LUT1 respectively store sine values and cosine values, the lookup address bit number of the lookup table LUT1 is a first bit number a, the data bit number of the lookup table LUT1 is a second bit number B, and the sine values and cosine values of a second number with continuous phases correspond to the same lookup address, where 2 A The product of which is equal to 2 B . The lookup address is incremented from 0.
Wherein a look-up table LUT1 stores a first numberA sine value of the quantity, another look-up table LUT1 stores a first number of cosine values, the first number being equal to 2 A 。2 A The sine or cosine value needs to pass 2 B The addressing of a single lookup address is complete and the second number of bits B is less than the first number of bits a, then a lookup address is required to address a second number of sine or cosine values simultaneously. The phases of the sine values and the cosine values of the second number corresponding to each table lookup address are continuous, the phase difference between two adjacent sine values and cosine values of the phases of the sine values and the cosine values of the second number corresponding to the same table lookup address is a preset phase increment, and the phase difference between the sine value and the cosine value of the second number corresponding to the previous table lookup address, which have the largest phase, and the phase difference between the sine value and the cosine value of the second number corresponding to the next table lookup address, which have the smallest phase, is also a preset phase increment.
The storage location of the first number of sine or cosine values in the look-up table LUT1 can be flexibly adjusted. In an application scenario of the embodiment of the present invention, the lookup table LUT1 has a second number of sub-tables, and each sub-table stores 2 sine values or 2 cosine values B The same data bit of each sub-table corresponds to the same table look-up address, the sine value or the cosine value stored by the same data bit is continuous in phase, and the phase difference of the sine value or the cosine value stored by two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
Wherein the number of sub-tables is also equal to the second number, so that each sub-table only needs to store a number of 2 B Such that the total number of sine or cosine values stored by all the subtables equals the first number. Each sine value or cosine value in the submenu occupies a data bit, the number of table lookup address bits corresponding to the data bits in the submenu is a second bit B, the 1 st table lookup address corresponds to the 1 st data bit of each submenu, namely, the 1 st data bit corresponds to the sine value or cosine value stored in the 1 st data bit, the 2 nd table lookup address corresponds to the 2 nd data bit of each submenu, the 3 rd table lookup address corresponds to the 3 rd data bit of each submenu, and so on, the 2 nd table lookup address corresponds to the 3 rd data bit of each submenu B The address of each table lookup corresponds to the 2 nd of each sub-table B And a data bit.
And the sine or cosine values stored for the same data bit of each sub-table are consecutive in phase, i.e. the difference in phase is a preset phase increment. The phase difference between the sine value and the cosine value stored in two adjacent data bits in the same sub-table is a preset phase increment of a second quantity, namely the product of the second quantity and the preset phase increment.
In this embodiment, the preset phase increment is:
wherein N represents a first number with a value range of [1,2 B ]C denotes a second number, f out Representing a predetermined frequency, f S Representing the frequency of the operating clock.
Further, the sinusoidal signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset. In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offsets of the sine signal and the cosine signal are the same.
Each sub-table will be explained in detail by means of fig. 5. Referring to fig. 5, each sine value of the sine signal expressed by the above formula is stored in 8 sub-tables of a look-up table LUT 1. The number of sine values, i.e. the first number N, is equal to 2 17 The number of sub-tables, i.e. the second number, is 8,c is in the range of [0,7]Respectively corresponding to 8 sub-tables, the number of bits of the table lookup address is 14, and the value range of the table lookup address is [0,2 ] 14 －1]For the convenience of calculation, a is 1,
and b takes 0. The sine values stored for each sub-table are as follows:
the sine value stored by each data bit of the 1 st sub-table is sin [0*2 pi × PINC/N]、sin[8*2π*PINC/N]、sin[16*2π*PINC/N]、…、sin[8*(2 14 -2)*2π*PINC/N]、sin[8*(2 14 -1)*2π*PINC/N]；
The sine value stored by each data bit of the 2 nd sub-table is sin [1*2 pi × PINC/N]、sin[9*2π*PINC/N]、sin[17*2π*PINC/N]、…、sin[(8*(2 14 -2)+1)*2π*PINC/N]、sin[(8*(2 14 -1)+1)*2π*PINC/N]；
The sine value stored by each data bit of the 3 rd sub-table is sin [2*2 pi × PINC/N]、sin[10*2π*PINC/N]、sin[18*2π*PINC/N]、…、sin[(8*(2 14 -2)+2)*2π*PINC/N]、sin[(8*(2 14 -1)+2)*2π*PINC/N]；
By analogy, the sine value stored by each data bit of the 8 th sub-table is sin [7*2 pi × PINC/N]、sin[15*2π*PINC/N]、sin[23*2π*PINC/N]、…、sin[(8*(2 14 -2)+7)*2π*PINC/N]、sin[(8*(2 14 -1)+7)*2π*PINC/N]。
It can be seen that the sine values stored for two adjacent data bits in each sub-table differ in phase by 8 x PINC.
The sinusoidal signal is generated as follows:
when the 1 st table lookup address is sent, namely N =0, the 8 sub-tables respectively output sin [0 × PINC × 2 pi/N ], sin [1 × PINC × 2 pi/N ], sin [2 × PINC × 2 pi/N ], … and sin [7 × PINC × 2 pi/N ];
when the 2 nd lookup table address is sent, namely N =1, the 8 sub-tables respectively output sin [8 × PINC × 2 pi/N ], sin [9 × PINC × 2 pi/N ], sin [10 × PINC × 2 pi/N ], … and sin [15 × PINC × 2 pi/N ];
when the 3 rd lookup address is sent, namely N =2, the 8 sub-tables respectively output sin [16 × PINC × 2 pi/N ], sin [17 × PINC × 2 pi/N ], sin [18 × PINC × 2 pi/N ], … and sin [23 × PINC × 2 pi/N ];
by parity of reasoning, in the stage 2 14 Individual table-look-up addresses, i.e. n =2 14 When the output signal is-1, 8 sub-tables respectively output sin [8 x (2) 14 -1)*2π*PINC/N]、sin[(8*(2 14 -1)+1)*2π*PINC/N]、sin[(8*(2 14 -1)+2)*2π*PINC/N]、…、sin[(8*(2 14 -1)+7)*2π*PINC/N]。
It can be seen that the phase of the 8 sine values output by each of the 8 sub-tables is incremented by PINC, and the phase of the last sine value output by the previous time differs from the phase of the first sine value output by the next time by PINC.
For the second way, please refer to fig. 6, the sin-cos signal generator 1 is used in an FPGA, and can generate high frequency sin-cos signals in the FPGA. The sine and cosine signal generator 1 comprises an address acquisition module 10B and a memory 20B which stores at least one-quarter period of trigonometric function values, wherein the number of the trigonometric function values of one period is a first number, and the number of the memory 20B is a second number.
The address obtaining module 10B is configured to sequentially obtain multiple paths of table lookup addresses under the action of the working clock, and send the multiple paths of table lookup addresses to the second number of memories 20B respectively, where two adjacent table lookup addresses in the same time differ by a preset phase increment, and two adjacent table lookup addresses in the same path differ by a second number multiple of the preset phase increment. If the preset phase increment is represented by PINC, the second quantity is represented by c, the difference between two adjacent lookup addresses at the same time is PINC, the minimum of the first acquired lookup addresses is preferably 0, the lookup addresses of other paths are 1 XPINC, 2 XPINC, 3 XPINC, 4 XPINC and … … in sequence, and the difference between two adjacent lookup addresses at the same path is c XPINC, for example, the lookup addresses of the first path are 0, c XPINC, 2C XPINC, 3C XPINC and … … in sequence.
The memory 20B is configured to output a current sine value and a current cosine value to form a sine signal and a cosine signal of a preset frequency, respectively, every time a lookup address is input. The second quantity is a preset number, and the preset phase increment is determined according to a preset frequency, the first quantity, the second quantity and the frequency of the working clock.
The lookup table address corresponding to each trigonometric function value stored in the memory 20B is incremented by the PINC from 0. For one memory 20B, for example, the memory 20B corresponding to the first path of table lookup address receives table lookup addresses of 0, c × PINC, 2c × PINC, 3c × PINC, and … … in sequence, then the phases of the finally output sine signal and cosine signal are increased by c × PINC, and the phase difference PINC between the sine signal and cosine signal output by two adjacent memories 20 is small.
The preset frequency, the first number, the second number and the frequency of the working clock are set according to actual needs. The first number is the total number of trigonometric values for one period and the memory 20B needs to store at least the first quarter of the trigonometric values of the first number. The frequency of the operating clock should not exceed the maximum operating frequency of the FPGA. The frequency of the operating clock and the value of the second number are related to the sampling rate, the product of which is equivalent to the sampling rate, e.g. the frequency of the operating clock is set to 200MHz at a sampling rate of 1.6GHz, then the second number is 8, i.e. 8 memories 20B are required. The sampling rate is determined by the control requirements of the qubit. According to the Nyquist sampling law, the ratio of the preset frequency to the sampling frequency is at most 1:2, that is, the preset frequency can theoretically reach 800MHz, so that a sine and cosine signal with a higher frequency is realized in the FPGA.
Since the trigonometric function has periodicity, the trigonometric function value of the last three-quarter period can be calculated according to the periodicity as long as the trigonometric function value of the first one-quarter period is known. In the present embodiment, the memory 20B stores the trigonometric values as sine values of at least a quarter of a cycle, cosine values of at least a quarter of a cycle, or sine and cosine values of at least a quarter of a cycle.
Further, the memory 20B is configured to check whether the current lookup address stores a corresponding sine value or cosine value every time a lookup address is sent in, output the stored current sine value and current cosine value when the corresponding sine value or cosine value is stored, respectively form a sine signal and a cosine signal of a preset frequency, and when the corresponding sine value or cosine value is not stored, calculate the corresponding sine value or cosine value according to the periodicity of the sine value or cosine value, output the calculated current sine value and current cosine value, respectively form a sine signal and a cosine signal of a preset frequency.
If the memory 20B stores the sine value of one cycle and the cosine value of one cycle, and the numbers of the sine value and the cosine value are both the first numbers, each table lookup address stores a corresponding sine value or cosine value, and the stored current sine value and current cosine value can be directly output. If the memory 20B only stores the sine value of less than one cycle and/or the cosine value of less than one cycle, there are some cases where the lookup table addresses do not have the corresponding sine value or cosine value, and then the sine value and cosine value corresponding to these lookup table addresses can be calculated according to the periodicity of the sine value or cosine value and the stored sine value and/or cosine value.
Referring to fig. 7, the memory 20B provides a lookup table LUT2, the lookup table LUT2 stores sine values of a quarter cycle, the number of lookup address bits of the lookup table LUT2 is a first number of bits a, where 2 A Equal to the first number. Only the front 2 A And/4, storing sine values in data bits corresponding to the table lookup addresses respectively, and leaving the data bits corresponding to the other table lookup addresses as null.
In this embodiment, the preset phase increment is:
wherein N represents a first number, c represents a second number, f out Representing a predetermined frequency, f S Representing the frequency of the operating clock and Round () representing the rounding function.
Further, the sinusoidal signal is:
the cosine signal is:
wherein n × PINC represents the value of the lookup table address, and the value range of n is [0,2 A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
The current sine value output by the memory 20B is:
the current cosine value output by memory 20B is:
wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 ] A －1]。
In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offsets of the sine signal and the cosine signal are the same. For the sake of easy understanding, a is taken to be 1,
and b takes 0.
As can be seen from fig. 7, the look-up table LUT2 front 2 A The/4 data bits store sine values of, in order, sin (0*2 π/N), sin (1*2 π/N), sin (2*2 π/N), sin (3*2 π/N), … …,
the remaining data bits store data NULL, indicating NULL. It can be seen that each stored sine value in the look-up table LUT2 is associated with a look-up address of the look-up table, where m is the look-up address, and sin (m × 2 pi/N) is the sine value.
Then by the periodicity of the sine function, one canThe sine values corresponding to other search addresses are calculated to be
sin[(N-1)*2π/N]。
Likewise, the cosine value may also be calculated from the periodicity of the sine value.
Assuming that the second number is 8, the process of generating the sinusoidal signal is as follows:
the lookup table addresses sent to the 1 st memory 20B are 0 Pinc, 8 Pinc, 16 Pinc and … … in sequence, the lookup table addresses in the lookup table LUT2 equal to 0 Pinc, 8 Pinc, 16 Pinc and … … are 0 Pinc, 8 Pinc, 16 Pinc and … … in sequence, the sine signal output by the 1 st memory 20B is sin (0*2 pi PINc/N), sin (8*2 pi PINc/N), sin (16 pi 2 pi PINc/N) and … …;
the lookup table addresses sent to the 2 nd memory 20B are 1 XPINC, 9 XPINC, 17 XPINC and … … in sequence, the lookup table addresses in the lookup table LUT2 equal to 1 XPINC, 9 XPINC, 17 XPINC and … … are 1 XPINC, 9 XPINC, 17 XPINC and … … in sequence, the sine signal output by the 2 nd memory 20B is sin (1*2 pi PINC/N), sin (9*2 pi PINC/N), sin (17 x 2 pi PINC/N) and … …;
the lookup table addresses sent to the 3 rd memory 20B are sequentially 2 XPINC, 10 XPINC, 18 XPINC, … …, the lookup table addresses in the lookup table LUT2 equal to 2 XPINC, 10 XPINC, 18 XPINC, … … are sequentially 2 XPINC, 10 XPINC, 18 XPINC, … …, the sine signal output by the 3 rd memory 20B is sin (2*2 π PINC/N), sin (10 XP 2 π PINC/N), sin (18 XP 2 π PINC/N), … …;
by analogy, the lookup table addresses sent to the 8 th memory 20B are 7 XPINC, 15 XPINC, 23 XPINC, … … in sequence, the lookup table addresses in the lookup table LUT2 equal to 7 XPINC, 15 XPINC, 23 XPINC, … … are 7 XPINC, 15 XPINC, 23 XPINC, … … in sequence, and the sine signal output by the 8 th memory 20B is sin (3245 zx3245 π PINC/N), sin (15 π 2 π PINC/N), sin (23 π 2 π PINC/N), … ….
It can be seen that the phase of the sinusoidal signal output by each of the 8 memories 20B is incremented by PINC, and the phase of the sinusoidal signal output by the same memory 20B is incremented by 8 x PINC.
It should be noted that, if the table lookup address sent into the memory 20B exceeds the maximum value of the table lookup addresses of the lookup table, the table lookup address addressed in the lookup table LUT2 by the memory 20B is the result of the complementation of the table lookup address sent into the memory 20B and the first number N.
Likewise, the 8 memories 20B output cosine signals according to the above-described procedure. Cosine signals output by the 1 st memory 20B are cos (0*2 pi x PINC/N), cos (8*2 pi x PINC/N), cos (16 x 2 pi X PINC/N) and … …; cosine signals output by the 2 nd memory 2B0 are cos (1*2 pi x PINC/N), cos (9*2 pi x PINC/N), cos (17 x 2 pi x PINC/N) and … …; cosine signals output by the 3 rd memory 20B are cos (2*2 pi × PINC/N), cos (10 × 2 pi × PINC/N), cos (18 × 2 pi × PINC/N) and … …; … …; the cosine signals output from the 8 th memory 20B are cos (7*2 pi × PINC/N), cos (15 × 2 pi × PINC/N), cos (23 × 2 pi × PINC/N), and … ….
In the two modes, the product of the frequency of the working clock and the second number is equivalent to the sampling frequency, and the preset frequency can reach half of the sampling frequency theoretically according to the Nyquist sampling law, so that sine and cosine signals with high frequency can be generated in the FPGA, and the resource consumption and the cost can be reduced.
Referring to fig. 8, a fifth embodiment of the present invention provides a qubit control system, which includes the apparatus 100, and the apparatus 100 is the apparatus for generating the qubit control signal provided in any of the previous embodiments.
In some other embodiments, the quantum computer control system further includes a mixer 200, and the mixer 200 is configured to mix the target steering signal with the local oscillator signal to change the target steering signal from an intermediate frequency to a radio frequency. After mixing, a target control signal of radio frequency is directly applied to the qubit, so that a target single-bit revolving gate is realized.
Further, the quantum computer control system further comprises a digital-to-analog converter 300, wherein the digital-to-analog converter 300 is configured to perform digital-to-analog conversion on the target steering signal before the target steering signal is mixed.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (18)
1. An apparatus for generating a qubit steering signal, the steering signal being mixed with a local oscillator signal from an intermediate frequency to a radio frequency and acting on the qubit to implement a single-bit turnstile, comprising:
the sine and cosine signal generator is used for respectively outputting sine signals and cosine signals with the same frequency of a preset path number in parallel under the action of a working clock;
the envelope generator is used for determining the envelope of a target control signal from a pre-stored corresponding table according to the target single-bit revolving gate, and respectively outputting envelope in-phase components and envelope quadrature components of a preset path number in parallel under the action of the working clock, wherein the corresponding table stores control signals corresponding to different single-bit revolving gates;
and the signal mixer is used for multiplying the sine signal with the preset path number by the envelope in-phase component and the cosine signal with the preset path number by the envelope orthogonal component under the action of the working clock, and adding the two multiplication results to obtain the target control signal, so that the phase difference between the target control signal and the local oscillator signal is consistent.
2. The apparatus of claim 1, further comprising a parallel-to-serial conversion module:
the signal mixer is also used for dividing the target control signal into at least one path of parallel output;
the parallel-serial conversion module is used for converting at least one path of target control signals output in parallel into serial signals under the action of a serial clock, wherein the frequency of the serial clock is not lower than that of the working clock.
3. The apparatus of claim 1 or 2, wherein the sine and cosine signal generator comprises an address acquisition module and a memory, the memory storing a first number of sine and cosine values at a preset frequency:
the address acquisition module is used for sequentially acquiring the table lookup addresses increased by the preset step length under the action of a working clock and sending the table lookup addresses into the memory;
the memory is configured to output a second number of current sine values and current cosine values for forming the sine signal and the cosine signal, respectively, in parallel, each time a lookup address is sent in;
the second quantity is the preset number, the phase of the sine value and the phase of the cosine value output each time are increased in a preset phase increment, the sine value and the cosine value output twice in adjacent times are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock.
4. The apparatus of claim 3, wherein the memory provides two identical lookup tables, the two lookup tables storing sine and cosine values, respectively, the lookup table having a first number of bits A for lookup address bits, a second number of bits B for data bits, and a phase positionThe successive sine and cosine values of the second number correspond to the same look-up address, 2 A The product of which is equal to 2 B 。
5. The apparatus of claim 4, wherein the lookup table has a second number of sub-tables, each of the sub-tables storing a number of sine or cosine values of 2 B The same data bit of each sub-table corresponds to the same table look-up address, the sine value or the cosine value stored in the same data bit is continuous in phase, and the phase difference of the sine value or the cosine value stored in two adjacent data bits in the same sub-table is a preset phase increment of a second quantity.
6. The apparatus of claim 5, wherein the predetermined phase increment is:
wherein N represents the first number and has a value range of [1,2 B ]C represents said second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock.
7. The apparatus of claim 6, wherein the sinusoidal signal is:
the cosine signal is:
wherein n represents the value of the table lookup address, and the value range is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
8. The apparatus of claim 1 or 2, wherein the sine and cosine signal generator comprises an address acquisition module and a memory storing trigonometric function values for at least one quarter of a cycle, the number of trigonometric function values for one cycle being a first number, the number of memory being a second number;
the address acquisition module is used for sequentially acquiring a plurality of paths of table lookup addresses under the action of a working clock and respectively sending the table lookup addresses into a second number of memories, wherein the table lookup addresses of two adjacent paths at the same moment differ by a preset phase increment, and the two adjacent table lookup addresses of the same path differ by a second number multiple of the preset phase increment;
the memory is configured to output a current sine value and a current cosine value to respectively form a sine signal and a cosine signal of a preset frequency when a table look-up address is sent in each time;
and the second quantity is the preset number of paths, and the preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock.
9. The apparatus of claim 8, wherein the memory stores trigonometric values that are at least a quarter period sine value, at least a quarter period cosine value, or at least a quarter period sine and cosine values.
10. The apparatus of claim 9, wherein the memory is configured to check whether a corresponding sine value or cosine value is stored in a current lookup address every time a lookup address is entered, output the stored current sine value and current cosine value when the corresponding sine value or cosine value is stored, respectively form a sine signal and a cosine signal of a preset frequency, and calculate the corresponding sine value or cosine value according to a periodicity of the sine value or cosine value when the corresponding sine value or cosine value is not stored, output the calculated current sine value and current cosine value, respectively form a sine signal and a cosine signal of a preset frequency.
11. The apparatus of claim 10, wherein the memory provides a lookup table having a quarter-cycle sine value stored therein, wherein the lookup address bits of the lookup table are a first number a of bits, wherein 2 A Equal to the first number.
12. The apparatus of claim 11, wherein the predetermined phase increment is:
wherein N represents the first number, c represents the second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock, round () representing a rounding function.
13. The apparatus of claim 12, wherein the sinusoidal signal is:
the cosine signal is:
wherein n × PINC represents the value of the lookup table address, and the value range of n is [0,2 A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
14. The apparatus of claim 13, wherein the memory outputs a current sine value of:
the current cosine value output by the memory is:
wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 ] A －1]。
15. The apparatus of claim 7 or 14, wherein the amplitudes, initial phases and offsets of the sine and cosine signals are the same.
16. A qubit computer control system comprising the apparatus of any of claims 1 to 15 for generating qubit steering signals.
17. The quantum computer control system according to claim 16, further comprising a mixer for mixing the target steering signal with a local oscillator signal to change the target steering signal from an intermediate frequency to a radio frequency.
18. The quantum computer control system of claim 17, further comprising a digital-to-analog converter for digital-to-analog converting the target steering signal prior to mixing the target steering signal.
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Address after: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, high tech Zone, Hefei City, Anhui Province Applicant after: Benyuan Quantum Computing Technology (Hefei) Co.,Ltd. Address before: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, high tech Zone, Hefei City, Anhui Province Applicant before: ORIGIN QUANTUM COMPUTING COMPANY, LIMITED, HEFEI |
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