CN115456186A - Sine and cosine signal generator and quantum computer control system - Google Patents
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Abstract
The invention discloses a sine and cosine signal generator and a quantum computer control system. The sine and cosine signal generator comprises an address acquisition module and a second number of memories which store trigonometric function values of at least one quarter period, wherein the number of the trigonometric function values of one period is a first number; the address acquisition module is used for sequentially acquiring a plurality of paths of table lookup addresses under the action of a working clock and respectively sending the table lookup addresses into a second number of memories, the table lookup addresses of two adjacent paths at the same moment differ by a preset phase increment, and the two table lookup addresses of the same path differ by a second number multiple of the preset phase increment; the memory is configured to output a current sine value and a current cosine value to respectively form a sine signal and a cosine signal with preset frequency when sending a table look-up address; and the preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock. The invention can generate sine and cosine signals with higher frequency in the FPGA, and can reduce resource consumption and cost.
Description
Technical Field
The invention relates to the field of quantum computing, in particular to a sine and cosine signal generator and a quantum computer control system.
Background
The quantum computer control system mainly functions to control a quantum computer, and more particularly, to control quantum bits. The essence of controlling the qubits is to apply various control signals to the qubits, which are mostly generated from the underlying sine and cosine signals. Because the frequency of the qubit is relatively high, the control signal needs to have a relatively high frequency, and the corresponding sine and cosine signal also needs to have a relatively high frequency.
However, the sine and cosine signals are generally generated by NCO (numerically controlled oscillator), which can be implemented in FPGA or other devices. The higher the frequency of sine and cosine signals is, the higher the sampling rate is required, but the maximum working frequency of most FPGAs is limited, so the frequency of the generated sine and cosine signals is lower. In order to increase the frequency of sine and cosine signals, the conventional method is to generate low-frequency sine and cosine signals in parallel through a plurality of FPGAs, and then synthesize the frequencies of the sine and cosine signals. But this requires multiple FPGAs, which significantly increases resource consumption and cost.
Disclosure of Invention
The invention aims to provide a sine and cosine signal generator, a memory and a quantum computer control system, which are used for solving the problem of low frequency of sine and cosine signals generated in an FPGA (field programmable gate array) in the prior art and can generate sine and cosine signals with high frequency in the FPGA.
In order to solve the technical problem, the invention provides a sine and cosine signal generator, which is used for an FPGA (field programmable gate array), and comprises an address acquisition module and a memory, wherein the memory stores at least one quarter of period of trigonometric function values, the number of the trigonometric function values in one period is a first number, and the number of the memory is a second number;
the address acquisition module is used for sequentially acquiring a plurality of paths of table lookup addresses under the action of a working clock and respectively sending the table lookup addresses into a second number of memories, wherein the table lookup addresses of two adjacent paths at the same moment differ by a preset phase increment, and the two adjacent table lookup addresses of the same path differ by a second number multiple of the preset phase increment;
the memory is configured to output a current sine value and a current cosine value to respectively form a sine signal and a cosine signal of a preset frequency when a table look-up address is sent in each time;
wherein the preset phase increment is determined according to the preset frequency, the first number, the second number and the frequency of the working clock.
Preferably, the memory stores trigonometric values that are at least a quarter cycle sine value, at least a quarter cycle cosine value or at least a quarter cycle sine value and cosine value.
Preferably, the memory is configured to check whether a corresponding sine value or cosine value is stored in a current lookup address every time a lookup address is sent in, output a stored current sine value and a stored current cosine value when the corresponding sine value or cosine value is stored, respectively form a sine signal and a cosine signal of a preset frequency, and calculate a corresponding sine value or cosine value according to the periodicity of the sine value or cosine value when the corresponding sine value or cosine value is not stored, output the calculated current sine value and current cosine value, and respectively form a sine signal and a cosine signal of a preset frequency.
Preferably, the memory provides a lookup table, the lookup table stores a sine value of a quarter cycle, and the lookup address bit number of the lookup table is a first bit number a, wherein 2 A Equal to the first number.
Preferably, the preset phase increment is as follows:
wherein N represents the first number, c represents the second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock, round () representing a rounding function.
Preferably, the sinusoidal signal is:
the cosine signal is:
where n × PINC represents the value of the lookup address sent to the memory, and n has a value in the range of [0, 2% A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
Preferably, the current sine value output by the memory is:
the current cosine value output by the memory is:
wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 ] A －1]。
Preferably, the amplitudes, initial phases and offset distances of the sine signal and the cosine signal are the same.
Preferably, the address acquisition module comprises a frequency word unit and a phase accumulator corresponding to the second number of memories one to one;
the frequency word unit is used for acquiring multiple paths of frequency words, and respectively sending the frequency words to a second number of phase accumulators, wherein the frequency words are second number multiples of a preset phase increment;
and the phase accumulators are used for continuously accumulating by taking the frequency words as steps under the action of the working clock to obtain a table look-up address and sending the table look-up address to corresponding memories, wherein the table look-up addresses obtained by two adjacent phase accumulators at the same moment are different by a preset phase increment.
In order to solve the above technical problem, the present invention further provides a quantum computer control system, including any one of the above sine and cosine signal generators.
Different from the situation of the prior art, the sine and cosine signal generator provided by the invention is provided with a second number of memories, each memory stores a trigonometric function value of at least one quarter period, the memories are configured to output a current sine value and a current cosine value to respectively form a sine signal and a cosine signal of preset frequency when each lookup address is sent, the difference between two adjacent lookup addresses at the same time is a preset phase increment, the difference between two adjacent lookup addresses at the same time is a second number multiple of the preset phase increment, and as the product of the frequency of the working clock and the second number is equivalent to a sampling frequency, the preset frequency can reach half of the sampling frequency theoretically according to a nyquist sampling law, so that a sine and cosine signal of higher frequency can be generated in an FPGA, and the resource consumption and the cost can be reduced.
The quantum computer control system provided by the invention and the sine and cosine signal generator belong to the same inventive concept, so that the quantum computer control system has the same beneficial effects, and is not repeated herein.
Drawings
Fig. 1 is a schematic structural diagram of a sine and cosine signal generator according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of a data structure of a lookup table provided in a memory of the sine and cosine signal generator in the first embodiment.
Fig. 3 is a schematic structural diagram of an address obtaining module of a sine and cosine signal generator according to a second embodiment of the present invention.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
Referring to fig. 1, a first embodiment of the present invention provides a sine and cosine signal generator for an FPGA, which is capable of generating a sine and cosine signal with a higher frequency in the FPGA. The sine and cosine signal generator comprises an address acquisition module 10 and a memory 20 which stores at least one-quarter period of trigonometric function values, wherein the number of the trigonometric function values in one period is a first number, and the number of the memory 20 is a second number.
The address obtaining module 10 is configured to sequentially obtain multiple paths of table lookup addresses under the action of a working clock, and send the multiple paths of table lookup addresses to the memories 20 of the second number respectively, where the table lookup addresses of two adjacent paths at the same time differ by a preset phase increment, and two adjacent table lookup addresses of the same path differ by a second number multiple of the preset phase increment. If the preset phase increment is represented by PINC, the second quantity is represented by c, the two adjacent lookup table addresses at the same time have the difference of PINC, the smallest of the first acquired lookup table addresses is preferably 0, and the lookup table addresses of other paths sequentially have the difference of 1 PinC, 2 PinC, 3 PinC, 4 PINC, 823082308230, the two adjacent lookup table addresses at the same path have the difference of c PINC, for example, the lookup table addresses of the first path sequentially have the difference of 0, c PINC, 2c PINC, 3c PINC, 8230, 8230.
The memory 20 is configured to output a current sine value and a current cosine value to form a sine signal and a cosine signal of a preset frequency, respectively, every time a lookup address is input. The preset phase increment is determined according to the preset frequency, the first quantity, the second quantity and the frequency of the working clock.
The lookup table address corresponding to each trigonometric function value stored in the memory 20 is incremented by the PINC from 0. For one memory 20, for example, the memory 20 corresponding to the first path lookup address receives the lookup addresses of 0, c-PINC, 2 c-PINC, 3 c-PINC, \ 8230 \ the phases of the finally output sine signal and cosine signal are increased by c-PINC, and the phases of the sine signal and cosine signal output by two adjacent memories 20 are different by PINC.
The preset frequency, the first number, the second number and the frequency of the working clock are set according to actual needs. The first number is the total number of trigonometric values for one period and the memory 20 needs to store at least the first quarter of the first number of trigonometric values. The frequency of the operating clock should not exceed the maximum operating frequency of the FPGA. The frequency of the operating clock and the value of the second number are related to the sampling rate, the product of which is equivalent to the sampling rate, e.g. the frequency of the operating clock is set to 200MHz at a sampling rate of 1.6GHz, then the second number is 8, i.e. 8 memories 20 are required. The sampling rate is determined by the control requirements of the qubit. According to the nyquist sampling law, the ratio of the preset frequency to the sampling frequency is at most 1:2, namely, the preset frequency can reach 800MHz theoretically, so that sine and cosine signals with higher frequency are realized in the FPGA.
Since the trigonometric function has periodicity, the trigonometric function value of the last three-quarter period can be calculated according to the periodicity as long as the trigonometric function value of the first one-quarter period is known. In the present embodiment, the memory 20 stores trigonometric values that are at least a quarter-cycle sine value, at least a quarter-cycle cosine value, or at least a quarter-cycle sine value and cosine value.
Further, the memory 20 is configured to check whether the current lookup address stores a corresponding sine value or cosine value every time a lookup address is sent, output the stored current sine value and current cosine value when the corresponding sine value or cosine value is stored, respectively form a sine signal and a cosine signal of a preset frequency, and when the corresponding sine value or cosine value is not stored, calculate the corresponding sine value or cosine value according to the periodicity of the sine value or cosine value, output the calculated current sine value and current cosine value, respectively form a sine signal and a cosine signal of a preset frequency.
If the memory 20 stores the sine value of one cycle and the cosine value of one cycle, and the numbers of the sine value and the cosine value are both the first number, then each table lookup address stores the corresponding sine value or cosine value, and the stored current sine value and current cosine value can be directly output. If the memory 20 stores only the sine value of less than one cycle and/or the cosine value of less than one cycle, there is a case that some table lookup addresses do not have the corresponding sine value or cosine value, and then the sine value and the cosine value corresponding to the table lookup addresses can be calculated according to the periodicity of the sine value or the cosine value and the stored sine value and/or cosine value.
Referring to fig. 2, the memory 20 provides a lookup table LUT, in which the sine value of a quarter cycle is stored, and the number of bits of the lookup address of the lookup table LUT is a first number of bits a, where 2 A Equal to the first number. Only the front 2 A And/4, storing sine values in data bits corresponding to the table lookup addresses respectively, and leaving the data bits corresponding to the rest table lookup addresses empty.
In this embodiment, the preset phase increment is:
wherein N represents a first number, c represents a second number, f out Representing a predetermined frequency, f S Representing the frequency of the operating clock and Round () representing the rounding function.
Further, the sinusoidal signal is:
the cosine signal is:
wherein n-PINC represents the value of the lookup table address,the value range of n is [0,2 ] A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
The current sine value output by the memory 20 is:
the current cosine value output by memory 20 is:
wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 ] A －1]。
In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offsets of the sine signal and the cosine signal are the same. For the sake of easy understanding, a is taken to be 1,
and b is taken to be 0.
As can be seen from fig. 2, the look-up table LUT front 2 A The/4 data bits store sine values of, sin (0 x 2 pi/N), sin (1 x 2 pi/N), sin (2 x 2 pi/N), sin (3 x 2 pi/N), \ 8230; \ 8230;, and,
The remaining data bits store data NULL, indicating NULL. It can be seen that each stored sine value in the look-up table LUT is related to the look-up address of the look-up table, and if the look-up address is m, the sine value is sin (m × 2 pi/N).
Then, through the periodicity of the sine function, the sine values corresponding to the other search addresses can be calculated to be
……、sin[(N-2)*2π/N]、sin[(N-1)*2π/N]。
Likewise, the cosine value may also be calculated from the periodicity of the sine value.
Assuming that the second number is 8, the process of generating the sinusoidal signal is as follows:
the look-up table addresses sent to 1 st memory 20 are 0 PINC, 8 PINC, 16 PINC, 8230, and the look-up table LUT is 0 PINC, 8 PINC, 16 PINC, 8230, and the same look-up table addresses are 0 PINC, 8 PINC, 16 PINC, 8230, and the sine signals output from 1 st memory 20 are sin (0 pi 2 PINC/N), sin (8 pi 2 PINC/N), sin (16 pi 2 PINC/N), 8230, and 8230;
the lookup table address sent to the 2 nd memory 20 is 1 Pinc, 9 Pinc, 17 Pinc, 8230, the lookup table LUT is 1 Pinc, 9 Pinc, 17 Pinc, 8230, the same lookup table address is 1 Pinc, 9 Pinc, 17 Pinc, 8230, the sine signal output from the 2 nd memory 20 is sin (1 pi 2 pi PINc/N), sin (9 pi 2 pi PINc/N), sin (17 pi 2 pi PINc/N), 8230, the sine signal output from the 2 nd memory 20 is sin (1 pi 2 pi PINc/N);
the lookup table address sent to the 3 rd memory 20 is 2-PINC, 10-PINC, 18-PINC, 8230, the lookup table LUT is 2-PINC, 10-PINC, 18-PINC, 8230, the same lookup table address is 2-PINC, 10-PINC, 18-PINC, 8230, the sine signal output from the 3 rd memory 20 is sin (2-2 pi-PINC/N), sin (10-2 pi-PINC/N), sin (18-2 pi-PINC/N), 8230, the sine signal output from the 3 rd memory 20 is sin (2-2 pi-PINC/N);
by analogy, the look-up table addresses sent to 8 th memory 20 are 7 th PINC, 15 th PINC, 23 th PINC, \8230, 8230, the look-up table LUT is 7 th PINC, 15 th PINC, 23 th PINC, \8230, 8230, the same look-up table addresses are 7 th PINC, 15 th PINC, 23 th PINC, 8230, the sine signals output by 8 th memory 20 are sin (7 th 2 pi PINC/N), sin (15 th 2 pi PINC/N), sin (23 th 2 pi PINC/N), 8230, and 8230.
It can be seen that the phase of the sinusoidal signal output by each of the 8 memories 20 is incremented by PINC, and the phase of the sinusoidal signal output by the same memory 20 is incremented by 8 x PINC.
It should be noted that, if the table lookup address sent into the memory 20 exceeds the maximum value of the table lookup addresses of the lookup table, the table lookup address addressed in the lookup table LUT by the memory 20 is the result of the complementation of the table lookup address sent into the memory 20 and the first number N.
Likewise, 8 memories 20 output cosine signals according to the above process. Cosine signals output by the 1 st memory 20 are cos (0 x 2 pi) PINC/N), cos (8 x 2 pi PINC/N), cos (16 x 2 pi PINC/N), \ 8230; the cosine signal output by the 2 nd memory 20 is cos (1 x 2 pi) PINC/N), cos (9 x 2 pi PINC/N), cos (17 x 2 pi PINC/N), \8230; cosine signals output by the 3 rd memory 20 are cos (2 x 2 pi) PINC/N), cos (10 x 2 pi PINC/N), cos (18 x 2 pi PINC/N), \8230; \8230; the cosine signals output from the 8 th memory 20 are cos (7 × 2 π × PINC/N), cos (15 × 2 π × PINC/N), cos (23 × 2 π × PINC/N), \ 8230; \ 8230;.
Referring to fig. 3, a second embodiment of the present invention provides a sine and cosine signal generator, which includes all the technical features of the first embodiment, and on the basis of the first embodiment, the address obtaining module 10 includes a frequency word unit 11 and a phase accumulator 12 corresponding to a second number of memories 20.
The frequency word unit 11 is configured to obtain multiple frequency words, and send the multiple frequency words to the second number of phase accumulators 12, where the frequency words are multiples of the second number of preset phase increments. The frequency word may be input externally, or may be stored in advance or generated automatically by the frequency word unit 11.
The phase accumulators 12 are configured to continuously accumulate the lookup addresses by taking the frequency words as steps under the action of the working clock to obtain lookup addresses, and send the lookup addresses to the corresponding memories 20, where the lookup addresses obtained by two adjacent phase accumulators 12 at the same time differ by a preset phase increment. Wherein, assuming the preset phase increment is PINC, the second number is 8, taking the first phase accumulator 12 as an example, when the phase accumulator 12 receives the first frequency word, it outputs a table lookup address 0 PinC, then accumulates 0 PinC with the frequency word to obtain a second table lookup address 8 PinC, and continues to accumulate 8 PinC with the frequency word to obtain a third table lookup address 16 PinC. That is, each time the phase accumulator 12 outputs a lookup address, the lookup address is accumulated with the frequency word as the next lookup address to be output.
Through the mode, the sine and cosine signal generator provided by the embodiment of the invention is provided with the second number of memories, each memory stores a trigonometric function value of at least one quarter period, the memory is configured to output the current sine value and the current cosine value when a lookup address is sent in, sine signals and cosine signals with preset frequencies are respectively formed, adjacent two paths of lookup addresses at the same time have a difference of a preset phase increment, two adjacent lookup addresses at the same time have a difference of a second number multiple of the preset phase increment, and the product of the frequency of the working clock and the second number is equivalent to the sampling frequency.
The embodiment of the invention also provides a quantum computer control system which comprises the sine and cosine signal generator of the first embodiment or the second embodiment.
It should be noted that, besides being applied to a quantum computer control system, the sine and cosine generator provided in the foregoing embodiments is also applicable to any other application scenario with sine and cosine signal generation requirements, and the present invention is not limited to this.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. Any person skilled in the art can make any equivalent substitutions or modifications on the technical solutions and technical contents disclosed in the present invention without departing from the scope of the technical solutions of the present invention, and still fall within the protection scope of the present invention without departing from the technical solutions of the present invention.
Claims (10)
1. A sine and cosine signal generator is used for FPGA and is characterized by comprising an address acquisition module and a memory for storing trigonometric function values of at least one quarter period, wherein the number of the trigonometric function values of one period is a first number, and the number of the memory is a second number;
the address acquisition module is used for sequentially acquiring a plurality of paths of table lookup addresses under the action of a working clock and respectively sending the table lookup addresses into a second number of memories, wherein the table lookup addresses of two adjacent paths at the same moment differ by a preset phase increment, and the two adjacent table lookup addresses of the same path differ by a second number multiple of the preset phase increment;
the memory is configured to output a current sine value and a current cosine value to respectively form a sine signal and a cosine signal of a preset frequency when a table look-up address is sent in each time;
wherein the preset phase increment is determined according to the preset frequency, the first number, the second number and the frequency of the working clock.
2. The sine-cosine signal generator of claim 1, wherein the memory stores trigonometric values that are at least a quarter period sine value, at least a quarter period cosine value, or at least a quarter period sine value and cosine value.
3. The sine-cosine signal generator of claim 2, wherein the memory is configured to check whether a corresponding sine value or cosine value is stored in a current lookup address every time a lookup address is sent, output the stored current sine value and current cosine value when the corresponding sine value or cosine value is stored, respectively form a sine signal and a cosine signal of a preset frequency, and when the corresponding sine value or cosine value is not stored, calculate the corresponding sine value or cosine value according to the periodicity of the sine value or cosine value, output the calculated current sine value and current cosine value, respectively form a sine signal and a cosine signal of a preset frequency.
4. The sine-cosine signal generator of claim 3, wherein the memory provides a look-up table storing a quarter-cycle sine value, the look-up table having a first number A of look-up address bits, of which 2 is A Equal to the first number.
5. The sine-cosine signal generator of claim 4, wherein the predetermined phase increment is:
wherein N represents the first number, c represents the second number, f out Representing said predetermined frequency, f S Representing the frequency of the operating clock, round () representing a rounding function.
6. The sine-cosine signal generator of claim 5, wherein the sine signal is:
the cosine signal is:
wherein n × PINC represents the value of the lookup address sent to the memory, and the value range of n is [0, 2% A －1]And a represents the amplitude value, a represents,
indicates the initial phase, and b indicates the offset.
7. The sine-cosine signal generator of claim 6, wherein the current sine value of the memory output is:
the current cosine value output by the memory is:
wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 ] A －1]。
8. The sine-cosine signal generator of claim 7, wherein the amplitude, initial phase and offset of the sine signal and the cosine signal are the same.
9. The sine-cosine signal generator of claim 1, wherein said address acquisition module comprises a frequency word unit and a phase accumulator in one-to-one correspondence with a second number of memories;
the frequency word unit is used for acquiring multiple paths of frequency words, and respectively sending the frequency words to a second number of phase accumulators, wherein the frequency words are second number multiples of a preset phase increment;
and the phase accumulators are used for continuously accumulating by taking the frequency words as steps under the action of the working clock to obtain a table look-up address and sending the table look-up address to corresponding memories, wherein the table look-up addresses obtained by two adjacent phase accumulators at the same moment are different by a preset phase increment.
10. A quantum computer control system comprising the sine-cosine signal generator of any one of claims 1 to 9.
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