CN115440796A - Super junction device terminal protection layout structure - Google Patents

Super junction device terminal protection layout structure Download PDF

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Publication number
CN115440796A
CN115440796A CN202211305048.4A CN202211305048A CN115440796A CN 115440796 A CN115440796 A CN 115440796A CN 202211305048 A CN202211305048 A CN 202211305048A CN 115440796 A CN115440796 A CN 115440796A
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region
conductive type
columns
type
layout structure
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CN115440796B (en
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柴展
栗终盛
罗杰馨
徐大朋
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Shanghai Gongcheng Semiconductor Technology Co Ltd
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Shanghai Gongcheng Semiconductor Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a super junction device terminal protection layout structure, which comprises a transition area and a terminal area; the corner region includes: the first conductive type columns and the second conductive type columns are arranged alternately, wherein at least one oblique second conductive type column obliquely extends to a second conductive type base region in the transition region at a certain included angle with the row direction, the oblique second conductive type columns are close to one side of the first side edge region and are multiple, the first conductive type columns reach the second conductive type columns and extend along the row direction, the oblique second conductive type columns are close to one side of the second side edge region and are multiple, and the first conductive type columns reach the second conductive type columns and extend along the row direction. The layout structure for terminal protection of the super junction device can solve the problems that the depletion layer depletion state of the terminal region of the existing super junction device is not ideal in the corner region of the terminal region, and the drain-source breakdown voltage of the device is influenced.

Description

Super junction device terminal protection layout structure
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a super junction device terminal protection layout structure.
Background
The on-resistance of conventional power semiconductor devices leads to a drastic increase in power consumption with an increase in withstand voltage. The occurrence of charge balance devices represented by Super-Junction (Super-Junction) devices breaks through the limitation, improves the restriction relationship between on-resistance and voltage resistance, and can simultaneously realize low-state power consumption and high-off voltage, so that the Super-Junction device can be rapidly applied to various high-energy-efficiency occasions, and has a very wide market prospect.
In the super junction device, a structure of alternately arranged P-type columns and N-type columns is adopted to replace a single conduction type material in a traditional power device to serve as a voltage maintaining layer, and a transverse electric field is introduced into a drift region; the P-type column and the N-type column meet the charge balance condition, under reverse bias, the P-type column and the N-type column are completely exhausted, and the region can be broken down only if the external voltage is greater than the internal transverse electric field, so that the voltage resistance of the region (the active region, which is divided into the charge flowing region and the transition region positioned around the charge flowing region) is extremely high, and the purposes of improving the breakdown voltage and reducing the on-resistance can be achieved.
At present, the terminal structure of the superjunction device which is most widely applied adopts the same structure as the active region, as shown in fig. 1, which is a layout structure of the superjunction device (N-type channel device) which is most widely applied, and it can be seen that the terminal region also has a plurality of alternating P-type columns and N-type columns, and the terminal structure is the same as the extending direction of the P-type columns and the N-type columns in the active region, and both the terminal structure and the active region extend along the column direction; however, as shown in fig. 1, the P-type pillars and the N-type pillars in the termination regions 31 located above and below the active region can be considered to be formed by extending the P-type pillars and the N-type pillars in the active region in the column direction, and a P-base region (the P-base region is represented by diagonal hatching in the figure, that is, a P-body) is formed at the upper ends of these N-type pillars and P-type pillars, and in contrast, the P-base region is not formed at the upper ends of the P-type pillars and N-type pillars in the termination regions 32 located at the left and right sides of the active region, so the termination regions 32 located at the left and right sides of the active region are not protected by the P-base region, so that the field voltage zero points of the termination regions 32 and 31 are not consistent, and the depletion state of the depletion layer is easily caused to cause premature breakdown, which affects the drain-source breakdown voltage (BVdss breakdown voltage) of the device.
For the layout structure of the improved super junction device terminal, as shown in fig. 2, the extending directions of the P-type columns and the N-type columns in the terminal regions 22 located at the left and right sides of the active region extend along the row direction, and the N-type columns and the P-type columns extending in the row direction extend into the active region and are protected by the P-type base region, so that the field voltage zero points of the terminal regions 22 located at the left and right sides of the active region are consistent with the field voltage zero points of the terminal regions 21 located at the upper and lower sides of the active region; however, for the termination region 23 located at the corner, the N-type columns and the P-type columns inside the termination region cannot extend into the active region, and the field voltage zero point is not consistent, so that premature breakdown is likely to occur, which affects the breakdown voltage of the device.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a layout structure for protecting a termination of a superjunction device, which is used to solve the problem that the drain-source breakdown voltage of the superjunction device is affected due to an unsatisfactory depletion layer state in a corner region of a termination region of the superjunction device.
In order to achieve the purpose, the invention provides a super junction device terminal protection layout structure, which comprises a transition region and a terminal region, wherein the terminal region is arranged at the periphery of the transition region;
the terminal area is divided into a first side area, a second side area and a corner area, the first side area is arranged along the row direction, the second side area is arranged along the column direction, and the corner area is positioned at the intersection of the adjacent first side area and the adjacent second side area;
the first side area, the second side area and the corner area respectively comprise first conductive columns and second conductive columns which are alternately arranged, the corner area further comprises at least one oblique second conductive column, and the oblique second conductive column divides the corner area into a first area close to the first side area and a second area close to the second side area;
the at least one oblique second conductive type column obliquely extends to the second conductive type base region located in the transition region, the first conductive type columns and the second conductive type columns in the first region are alternately arranged and extend in the column direction, and the first conductive type columns and the second conductive type columns in the second region are alternately arranged and extend in the row direction.
Optionally, the number of the oblique second conductive type pillars is odd.
Optionally, the diagonal posts are angled at 45 ° to the row direction.
Optionally, the lengths of all the pillars in the first region gradually decrease along a direction away from the first side edge region, and the lengths of all the pillars in the second region gradually decrease along a direction away from the second side edge region.
Optionally, the widths of the first conductivity-type pillars in the first side region, the second side region, and the corner region are all the same, and the widths of the second conductivity-type pillars in the first side region, the second side region, and the corner region are all the same.
Optionally, the first conductive type pillar and the second conductive type pillar in the first side region extend in a column direction to a second conductive type base region located in the transition region; the first conductive type pillar and the second conductive type pillar in the second side region extend to a second conductive type base region located in the transition region in a row direction.
Optionally, the first conductive type pillars and the second conductive type pillars in the transition region are alternately arranged, and the second conductive type base region is formed above the first conductive type pillars and the second conductive type pillars.
Optionally, the layout structure further includes a charge flowing region, the transition region is located between the charge flowing region and the terminal region, the first conductive type pillars and the second conductive type pillars in the charge flowing region are alternately arranged, and the second conductive type base region is formed above the second conductive type pillars.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type.
Optionally, the layout structure further includes a stop ring, and the stop ring is located at the periphery of the terminal region.
As described above, in the layout structure for super junction device terminal protection of the present invention, at least one second conductive type pillar exists in the corner region and directly and obliquely extends into the transition region, that is, is directly connected to the second conductive type base region in the transition region, so that it is ensured that the field voltage zero point of the corner region is consistent with the field voltage zero point of the first side region and the field voltage zero point of the second side region, so that the corner region is not broken down in advance, and the breakdown voltage of the device is improved.
Drawings
Fig. 1 shows a layout structure of the superjunction device terminal protection in which the P-type column and the N-type column in the terminal region all extend in the column direction in the background art.
Fig. 2 shows a layout structure of the superjunction device terminal protection in the background art, where the P-type columns and the N-type columns in the terminal regions on the left and right sides of the active region extend in the row direction.
Fig. 3 shows a layout structure of the super junction device terminal protection of the invention.
Fig. 4 shows a quarter of the layout structure of the super junction device terminal protection of the invention.
Fig. 5 shows a perspective view of the inventive corner region.
Description of component reference numerals
10. Super junction device terminal protection layout structure
Two central axes of layout structure for A-A ', B-B' super junction device terminal protection
11. Quarter equal part of layout structure for super junction device terminal protection
111. Region of charge flow
112. Transition zone
120. Terminal area
121. First side edge region
122. Second side region
123. Corner region
130 N type column (first conductive type column)
140 P type column (second conductive type column)
141. Oblique P type column (oblique second conductive type column)
150 P base region (second conductive type base region)
160. Cut-off region
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one structure or feature's relationship to another structure or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between 8230 \ 8230;" between "means both end points are included.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
Please refer to fig. 3 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The present embodiment provides a layout structure 10 for terminal protection of a superjunction device, as shown in fig. 3, the layout structure includes a transition region 112 and a terminal region 120.
In this embodiment, for convenience of description, as shown in fig. 3, the layout structure 10 protected by the terminal of the superjunction device is divided into 4 equal parts along two central axes (an axisbase:Sub>A-base:Sub>A 'and an axis B-B') of the layout structure 10 protected by the terminal of the superjunction device; because the layout pattern in the structure of 4 equal parts is centrosymmetric, and there is only difference in the extending direction between the equal parts, therefore, only one of the equal parts is described herein without limiting the invention; the layout structure 10 of the superjunction device will be explained hereinafter based on the quarter 11 located at the upper left corner as an example.
The terminal region 120 is disposed at the periphery of the transition region 112; the first conductive type pillars 130 and the second conductive type pillars 140 in the transition region 112 are alternately arranged, and the second conductive type base region 150 is formed above the first conductive type pillars 130 and the second conductive type pillars 140.
In this embodiment, as shown in fig. 3, the first conductive type column 130 and the second conductive type column 140 are provided in different regions in the layout structure 10 for super junction device terminal protection, the first conductive type column 130 and the second conductive type column 140 are alternately arranged, and the first conductive type column 130 and the second conductive type column 140 in different regions have different extending directions, different doping concentrations, and different column lengths. A second conductive type base region 150 is formed above the plurality of second conductive type pillars 140 and the plurality of first conductive type pillars 130 in the transition region 112 (in the figure, the area hatched by oblique lines is the second conductive type base region 150), and correspondingly, the second conductive type base region 150 is not formed above the second conductive type pillars 140 and the first conductive type pillars 130 in the termination region 120. It should be noted that the first conductive type pillar 130 may be an N-type pillar or a P-type pillar, the second conductive type pillar 140 may be an N-type pillar or a P-type pillar, and the conductive type of the first conductive type pillar 130 is opposite to that of the second conductive type pillar 140; as an example, in the present embodiment, a super junction device with an N-type channel region is taken as an example to illustrate the layout structure 10 for protecting the terminal of the super junction device, that is, the first conductivity type N-type and the second conductivity type P-type, and in some variation embodiments, super junction units with other topology structures are also applicable to the super junction device of the present invention.
Specifically, the layout structure 10 further includes a charge flowing region 111.
In this embodiment, as shown in fig. 3, the charge flowing region 111 is located in the middle region of the layout structure 10 protected along the terminal of the superjunction device, the terminal region 120 is located at the periphery of the charge flowing region 111, and the transition region 112 is located between the charge flowing region 111 and the terminal region 120; in the charge flowing region 111, all the P-type pillars 140 and the N-type pillars 130 have the same length, extend in the column direction, and only the P-type base region 150 is formed above the P-type pillars 140 (the P-base region width is the same as the P-type pillar width); it should be noted that, in some embodiments, the P-type base region on the charge flowing region 111 may also be slightly wider than the width of the P-type pillar, and a partial region is formed at the upper end of the N-type pillar, but does not completely cover one N-type pillar, so as to reserve a sufficient channel region width for the super junction device.
Terminal area 120 divides into first side region 121, second side region 122 and corner region 123, first side region 121 sets up along the row direction, second side region 122 sets up along the column direction, corner region 123 is located adjacently first side region 121 with the junction of second side region 122.
In the present embodiment, as shown in fig. 2 and 3, the terminal regions 120 located right above and right below the transition region 112 are defined as a first side region 121, the terminal regions 120 located right to the left and right of the transition region 112 are defined as a second side region 122, the rectangular regions located at the four corners of the terminal regions are defined as corner regions 123, and the corner regions 123 separate the first side region 121 and the second side region 122.
Specifically, the first side region 121, the second side region 122 and the corner region 123 all include first conductive type pillars 130 and second conductive type pillars 140 that are alternately arranged, the corner region 123 further includes at least one oblique second conductive type pillar 141, and the oblique second conductive type pillar 141 divides the corner region into a first region close to the first side region 121 and a second region close to the second side region 122; at least one of the oblique second conductive type pillars 141 extends obliquely to the second conductive type base region 150 located in the transition region, the first conductive type pillars 130 and the second conductive type pillars 140 in the first region are alternately arranged and extend in the column direction, and the first conductive type pillars 130 and the second conductive type pillars 140 in the second region are alternately arranged and extend in the row direction.
In this embodiment, as shown in fig. 4, in the quarter 11 located at the upper left corner, the terminal area right to the corner area 123 is the first side area 121, and the terminal area right below the corner area 123 is the second side area 122; in the corner region 121, the corner region 123 located on the right side of the diagonal P-type pillar 141 is a first region, and the P-type pillar and the N-type pillar in the first region extend in the column direction; the corner area 123 on the lower side of the diagonal P-type pillar 141 is a second region in which the P-type pillar and the N-type pillar extend in the row direction.
Furthermore, as shown in fig. 4 and fig. 5, the slanted P-type pillar 141 extends into the transition region 112, that is, is directly connected to the P-type base region 150 in the transition region 112, since the P-type base region 150 can protect the terminal region 120 from the interface surface state and the charge concentration at the junction between different material layers of the device, the corner region 123 is protected by the P-type base region 150, which can ensure that the field voltage zero point of the corner region 123 is consistent with the field voltage zero point of the first side region 121 and the field voltage zero point of the second side region 122, when the depletion layer is depleted, depletion can start from the same position, so that the corner region 123 is not broken down in advance, the withstand voltage of the superjunction device is more uniform, and the breakdown voltage of the superjunction device is increased.
Meanwhile, in the super junction device, the depletion layer is expanded approximately spherically when expanding, and due to the P-type column 140 extending along the oblique direction in the corner region 123, when the depletion layer expands to the corner region 123, the depletion layer can be expanded into the corner region 123 along the oblique direction, so that the expansion of the depletion layer is smoother, and the breakdown voltage of the super junction device is improved.
More specifically, the lengths of all the pillars in the first region decrease gradually in a direction away from the first side region 121, and the lengths of all the pillars in the second region decrease gradually in a direction away from the second side region 122.
In this embodiment, since the oblique P-type pillar 141 is oblique, the longer the distance between the P-type pillar and the N-type pillar in the first region and the first side region 121 is, the shorter the pillar length is; the longer the distance between the P-type and N-type pillars in the second region and the second side region 122, the shorter the pillar length.
More specifically, the number of the diagonal second conductive type pillars 141 is an odd number.
In this embodiment, the central axis of one of the oblique P-type pillars 141 overlaps with the oblique diagonal line of the corner region 123, the length of the P-type pillar 141 is longest, and the other oblique P-type pillars 141 and the oblique N-type pillars are alternately arranged at intervals on both sides thereof, and since the pillar overlapping with the oblique diagonal line of the corner region 123 is a P-type pillar and the oblique pillars adjacent to the first region and the second region are N-type pillars, the number of the oblique P-type pillars is one less than the number of the oblique N-type pillars, and is an odd number.
More specifically, the diagonal posts form a 45 ° angle with the row direction.
In this embodiment, as shown in fig. 4 and 5, the diagonal line of the corner region forms 45 ° with the row direction, and the obliquely arranged N-type columns and the N-type columns also extend obliquely at an included angle of 45 ° with the row direction; as an example, when there is only one oblique P-type pillar 141, two regions, a first region and a second region, which are isosceles right triangles are respectively disposed on two sides of the oblique P-type pillar, and one oblique N-type pillar is disposed on each side of the oblique P-type pillar to respectively separate the oblique P-type pillar 141 from the two regions, wherein the P-type pillar and the N-type pillar in the first region extend along the row direction, the P-type pillar and the N-type pillar in the second region extend along the column direction, and the first region and the second region are symmetrically distributed with the central line of the oblique P-type pillar 141 as the central axis.
It should be additionally noted that, in the layout structure 10, no matter the P-type columns 140 extending along the column direction, the P-type columns 140 extending along the row direction, or the oblique P-type columns 141 and the oblique N-type columns extending along the oblique direction, the head end and the tail end of each P-type column do not contact with the other P-type column, and a certain distance exists between the P-type columns 140 and the oblique N-type columns, where the distance is less than or equal to the width of the P-type column 140 or the N-type column 130.
Specifically, the first conductive type pillar 130 and the second conductive type pillar 140 in the first side region 121 extend to the second conductive type base region 150 in the transition region 112 along the column direction; the first conductive type pillar 130 and the second conductive type pillar 140 in the second side edge region 122 extend in a row direction to a second conductive type base region 150 in the transition region 112.
In the present embodiment, as shown in fig. 4 and fig. 5, the P-type columns and the N-type columns in the first side region 121 are formed by extending the P-type columns 140 and the N-type columns 130 in the transition region 112 along the column direction, and the P-type columns 140 and the N-type columns 130 in the second side region 122 are formed by extending the P-type columns and the N-type columns in the transition region 112 along the row direction, which is favorable for ensuring that the field voltage zero point of the first side region 121 and the field voltage zero point of the second side region 122 are consistent.
More specifically, the widths of the first conductive type pillars 130 in the first side region 121, the second side region 122, and the corner region 123 are all the same, and the widths of the second conductive type pillars 140 in the first side region 121, the second side region 122, and the corner region 123 are all the same.
In the present embodiment, the widths and concentrations of the N-type pillars 130 in the charge flow region 111, the transition region 112, the first side region 121, and the second side region 122 are the same, and the widths and concentrations of the P-type pillars in the charge flow region 111, the transition region 112, the first side region 121, and the second side region 122 are the same; and the product of the width and the concentration of the N-type columns 130 is equal to the product of the width and the concentration of the P-type columns 140, so that each N-type column 130 can be completely depleted by the P-type columns 140 positioned on the two sides of the N-type column, intrinsic characteristics are shown, and the breakdown voltage of the super junction device is favorably improved.
Specifically, the layout structure 10 further includes a stop ring 160, where the stop ring 160 is located at the periphery of the terminal region 120.
In the present embodiment, in the termination region 120, the stop ring 160 is further disposed on the outer side of the alternating arrangement of the N-type pillars 130 and the P-type pillars 140, the conductivity type of the stop ring 160 is N-type, and the stop ring is N + doped with respect to the N-type substrate, and the doping concentration is greater than 1e16cm-3.
In summary, in the layout structure for protecting the terminal of the super junction device provided by the invention, at least one second conductive type column exists in the corner region and directly and obliquely extends into the transition region, that is, is directly connected to the second conductive type base region in the transition region, so that the field voltage zero point of the corner region can be ensured to be consistent with the field voltage zero point of the first side region and the field voltage zero point of the second side region, the corner region cannot be broken down in advance, and the breakdown voltage of the device is improved. Therefore, the present invention has a great industrial utility value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A layout structure for protecting a terminal of a super junction device is characterized by comprising a transition region and a terminal region, wherein the terminal region is arranged on the periphery of the transition region;
the terminal area is divided into a first side area, a second side area and a corner area, the first side area is arranged along the row direction, the second side area is arranged along the column direction, and the corner area is positioned at the intersection of the adjacent first side area and the adjacent second side area;
the first side area, the second side area and the corner area respectively comprise first conductive columns and second conductive columns which are alternately arranged, the corner area further comprises at least one oblique second conductive column, and the oblique second conductive column divides the corner area into a first area close to the first side area and a second area close to the second side area;
the at least one oblique second conductive type column obliquely extends to the second conductive type base region located in the transition region, the first conductive type columns and the second conductive type columns in the first region are alternately arranged and extend in the column direction, and the first conductive type columns and the second conductive type columns in the second region are alternately arranged and extend in the row direction.
2. The layout structure of super junction device terminal protection according to claim 1, wherein the number of the oblique second conductive type columns is an odd number.
3. The layout structure of super junction device terminal protection according to any one of claims 1-2, wherein the oblique columns form an angle of 45 ° with the row direction.
4. The layout structure of superjunction device terminal protection according to claim 1, wherein lengths of all pillars in the first region are gradually reduced in a direction away from the first side edge region, and lengths of all pillars in the second region are gradually reduced in a direction away from the second side edge region.
5. The layout structure of superjunction device terminal protection according to claim 1, wherein widths of the first conductivity type pillars in the first side region, the second side region, and the corner region are all the same, and widths of the second conductivity type pillars in the first side region, the second side region, and the corner region are all the same.
6. The super junction device terminal protection layout structure according to claim 1, wherein the first and second conductivity type pillars in the first side region extend in a column direction to a second conductivity type base region in the transition region; the first conductive type column and the second conductive type column in the second side region extend to the second conductive type base region in the transition region along the row direction.
7. The layout structure of super junction device terminal protection according to claim 1, wherein first conductive type columns and second conductive type columns in the transition region are alternately arranged, and the second conductive type base region is formed above the first conductive type columns and the second conductive type columns.
8. The super junction device terminal protection layout structure according to claim 1, wherein the layout structure further comprises a charge flowing region, the transition region is located between the charge flowing region and the terminal region, first conductive type columns and second conductive type columns in the charge flowing region are alternately arranged, and the second conductive type base region is formed above the second conductive type columns.
9. The layout structure of super junction device terminal protection according to claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
10. The layout structure of superjunction device terminal protection according to claim 1, further comprising a cut-off ring located at an outer periphery of the terminal region.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050280086A1 (en) * 2004-06-21 2005-12-22 Kabushiki Kaisha Toshiba Power semiconductor device
US20070029597A1 (en) * 2005-07-30 2007-02-08 Lee Jae-Gil High-voltage semiconductor device
CN102623504A (en) * 2012-03-29 2012-08-01 无锡新洁能功率半导体有限公司 Super junction semiconductor device with novel terminal structure and manufacture method thereof
CN103165670A (en) * 2011-12-09 2013-06-19 上海华虹Nec电子有限公司 Terminal protection structure of super junction component
CN204243047U (en) * 2014-11-03 2015-04-01 吉林华微电子股份有限公司 The orthogonal super junction turning terminal of groove super junction-semiconductor device
CN105161518A (en) * 2015-06-18 2015-12-16 中航(重庆)微电子有限公司 Super junction layout structure
CN106711191A (en) * 2017-02-14 2017-05-24 无锡新洁能股份有限公司 Super junction semiconductor device with terminal protection zone and manufacturing method thereof
WO2017187856A1 (en) * 2016-04-27 2017-11-02 三菱電機株式会社 Semiconductor device
CN108428732A (en) * 2017-02-15 2018-08-21 深圳尚阳通科技有限公司 Superjunction devices and its manufacturing method
CN108987459A (en) * 2018-07-25 2018-12-11 王永贵 A kind of power device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050280086A1 (en) * 2004-06-21 2005-12-22 Kabushiki Kaisha Toshiba Power semiconductor device
US20070029597A1 (en) * 2005-07-30 2007-02-08 Lee Jae-Gil High-voltage semiconductor device
CN103165670A (en) * 2011-12-09 2013-06-19 上海华虹Nec电子有限公司 Terminal protection structure of super junction component
CN102623504A (en) * 2012-03-29 2012-08-01 无锡新洁能功率半导体有限公司 Super junction semiconductor device with novel terminal structure and manufacture method thereof
CN204243047U (en) * 2014-11-03 2015-04-01 吉林华微电子股份有限公司 The orthogonal super junction turning terminal of groove super junction-semiconductor device
CN105161518A (en) * 2015-06-18 2015-12-16 中航(重庆)微电子有限公司 Super junction layout structure
WO2017187856A1 (en) * 2016-04-27 2017-11-02 三菱電機株式会社 Semiconductor device
CN106711191A (en) * 2017-02-14 2017-05-24 无锡新洁能股份有限公司 Super junction semiconductor device with terminal protection zone and manufacturing method thereof
CN108428732A (en) * 2017-02-15 2018-08-21 深圳尚阳通科技有限公司 Superjunction devices and its manufacturing method
CN108987459A (en) * 2018-07-25 2018-12-11 王永贵 A kind of power device

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