TW201701476A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- TW201701476A TW201701476A TW104120351A TW104120351A TW201701476A TW 201701476 A TW201701476 A TW 201701476A TW 104120351 A TW104120351 A TW 104120351A TW 104120351 A TW104120351 A TW 104120351A TW 201701476 A TW201701476 A TW 201701476A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 239000011295 pitch Substances 0.000 description 30
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
本發明是有關於一種積體電路，且特別是有關於一種具有彎角佈局的半導體元件。 The present invention relates to an integrated circuit, and more particularly to a semiconductor component having an angular layout.
一般而言，在功率半導體元件中，崩潰電壓(breakdown voltage)與導通狀態電阻(ON-state resistance)之間存在一種取捨(trade off)關係。而超接面(super junction)元件為常見的一種功率半導體元件，其可達到低導通狀態電阻，且同時維持高崩潰電壓。超接面元件具有在漂移區(drift region)中的相互交替的P型摻雜柱與N型摻雜柱。在超接面元件的關閉狀態(OFF-state)中，在相對很低的電壓下，摻雜柱便可完全空乏(deplete)，進而維持較高的崩潰電壓。而且在相同崩潰電壓的條件下，超接面元件的導通狀態電阻小於傳統功率半導體元件的導通狀態電阻。 In general, in power semiconductor devices, there is a trade off relationship between a breakdown voltage and an ON-state resistance. The super junction element is a common type of power semiconductor component that achieves a low on-state resistance while maintaining a high breakdown voltage. The super junction element has mutually alternating P-type doped columns and N-type doped columns in a drift region. In the off-state of the superjunction element, at relatively low voltages, the doped column can be completely depleted, thereby maintaining a high breakdown voltage. Moreover, under the same breakdown voltage condition, the on-state resistance of the super junction element is smaller than the on-state resistance of the conventional power semiconductor element.
在超接面元件中，晶胞區和終端區內的各處電荷都需要平衡。然而，在彎角區卻很難達到電荷平衡，導致彎角區中的崩潰電壓下降。因此，美國專利US 2011/0204442將其彎角區分成三個部分，且每一個部分又有各自的設計規範(design rule)。為了 平衡彎角區中的電荷，且同時符合上述每一個部分的設計規範，將變得非常複雜且不切實際。利用三維模型軟體模擬彎角區，是另一種達到電荷的方法，但使用這些軟體不僅價格昂貴、操作複雜，還相當費時。因此，如何提供一種具有彎角佈局的半導體元件，其可簡化設計規範，且同時提升彎角區的崩潰電壓將成為重要的一門課題。 In the super junction element, the charge in the cell region and the termination region needs to be balanced. However, it is difficult to achieve charge balance in the corner region, resulting in a drop in breakdown voltage in the corner region. Therefore, U.S. Patent No. 2011/0204442 divides its corner into three parts, and each part has its own design rule. in order to Balancing the charge in the corner regions, while meeting the design specifications for each of the above sections, becomes very complicated and impractical. Simulating the corner area using the 3D model software is another way to reach the charge, but using these software is not only expensive, complicated, but also time consuming. Therefore, how to provide a semiconductor component having a corner layout which simplifies the design specification and simultaneously raises the breakdown voltage in the corner region will become an important issue.
本發明提供一種具有彎角佈局的半導體元件，以提升半導體元件的崩潰電壓。 The present invention provides a semiconductor component having an angular layout to enhance the breakdown voltage of the semiconductor component.
本發明提供一種半導體元件，包括：基底、具有第一導電型的摻雜區、具有第二導電型的多個第一條狀摻雜區、具有第二導電型的多個第二條狀摻雜區以及具有第二導電型的多個第三條狀摻雜區。基底具有第一區、第二區以及第三區。所述第一區圍繞第二區與第三區，且第二區與第三區相鄰。摻雜區位於基底中。第一條狀摻雜區位於第一區的摻雜區中。第二條狀摻雜區位於第二區的摻雜區中。第二條狀摻雜區沿著第一方向交替排列。第三條狀摻雜區位於第三區的摻雜區中。第三條狀摻雜區包括：第一部分、第二部分以及第三部分。第一部分具有第一端與第二端。第二部分與第一部分的第一端相連。第二部分的第三條狀摻雜區沿著第二方向交替排列。第三部分與第一部分的第二端相連。第三部分的第三條狀摻雜區沿著第一方向交替排列。第一方 向與第二方向不同。 The present invention provides a semiconductor device comprising: a substrate, a doped region having a first conductivity type, a plurality of first strip doped regions having a second conductivity type, and a plurality of second strip dopings having a second conductivity type a miscellaneous region and a plurality of third strip doped regions having a second conductivity type. The substrate has a first zone, a second zone, and a third zone. The first zone surrounds the second zone and the third zone, and the second zone is adjacent to the third zone. The doped regions are located in the substrate. The first strip doped region is located in the doped region of the first region. The second strip-shaped doped region is located in the doped region of the second region. The second strip-shaped doped regions are alternately arranged along the first direction. The third strip-shaped doped region is located in the doped region of the third region. The third strip-shaped doping region includes: a first portion, a second portion, and a third portion. The first portion has a first end and a second end. The second portion is coupled to the first end of the first portion. The third strip-shaped doped regions of the second portion are alternately arranged along the second direction. The third portion is connected to the second end of the first portion. The third strip-shaped doped regions of the third portion are alternately arranged along the first direction. First party It is different from the second direction.
在本發明的一實施例中，所述第一部分的形狀為扇形、三角形或其組合。 In an embodiment of the invention, the first portion has a shape of a sector, a triangle, or a combination thereof.
在本發明的一實施例中，當所述第一部分的形狀為扇形、三角形或其組合，其第一端與第二端之間的夾角為90度。 In an embodiment of the invention, when the shape of the first portion is a fan shape, a triangle shape or a combination thereof, an angle between the first end and the second end is 90 degrees.
在本發明的一實施例中，所述第二部分為第一部分的第一延伸部，其自第一端沿著第一方向延伸。所述第三部分為第一部分的第二延伸部，其自第二端沿著第二方向延伸。 In an embodiment of the invention, the second portion is a first extension of the first portion that extends from the first end along the first direction. The third portion is a second extension of the first portion that extends from the second end in the second direction.
在本發明的一實施例中，各第二條狀摻雜區的末端與第一條狀摻雜區之間的第一最近距離小於或等於第三條狀摻雜區與第一條狀摻雜區之間的間距。 In an embodiment of the invention, the first closest distance between the end of each of the second strip-shaped doping regions and the first strip-shaped doping region is less than or equal to the third strip-shaped doping region and the first strip-shaped doping The spacing between the miscellaneous areas.
在本發明的一實施例中，所述第二部分的各第三條狀摻雜區的末端與第二條狀摻雜區之間的第二最近距離小於或等於第三部分的一側與第二條狀摻雜區之間的第三最近距離。 In an embodiment of the invention, a second closest distance between an end of each of the third strip-shaped doped regions of the second portion and the second strip-shaped doped region is less than or equal to a side of the third portion The third closest distance between the second strip-shaped doped regions.
在本發明的一實施例中，所述第一方向與第二方向實質上垂直。 In an embodiment of the invention, the first direction is substantially perpendicular to the second direction.
在本發明的一實施例中，所述第一區、第二區以及第三區皆為晶胞區。 In an embodiment of the invention, the first region, the second region, and the third region are all unit cell regions.
在本發明的一實施例中，所述第一區為終端區，第二區以及第三區皆為晶胞區。 In an embodiment of the invention, the first area is a terminal area, and the second area and the third area are both a unit cell area.
基於上述，本發明利用具有扇形或三角形形狀的第三條狀摻雜區配置在彎角區中，以簡化彎角區的設計規範，進而提升 彎角區的崩潰電壓。再藉由調整第三條狀摻雜區自第一端沿著第一方向延伸的第一延伸部，以平衡第二區與第三區之間的電荷。此外，由於本發明將具有扇形或三角形形狀的第三條狀摻雜區配置在彎角區中，其使得P型摻雜柱與N型摻雜柱的設計不良(例如是摻雜柱寬度差異問題)所導致的崩潰不會出現在彎角區內。因此，相較於習知的美國專利US 2011/0204442，本發明可用以判定崩潰原因，以利於元件設計者判斷。 Based on the above, the present invention utilizes a third strip-shaped doping region having a fan shape or a triangular shape to be disposed in the corner region to simplify the design specification of the corner region and thereby improve The breakdown voltage in the corner area. The charge between the second region and the third region is balanced by adjusting the first extension extending along the first direction from the first end of the third strip-shaped doped region. In addition, since the present invention arranges the third strip-shaped doping region having a fan shape or a triangular shape in the corner region, the poor design of the P-type doped column and the N-type doped column (for example, the difference in doping column width) The crash caused by the problem does not occur in the corner area. Thus, the present invention can be used to determine the cause of a collapse as compared to the prior art U.S. Patent No. 2011/0204442, to facilitate the judgment of the component designer.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
10‧‧‧閘極結構 10‧‧‧ gate structure
10a‧‧‧閘介電層 10a‧‧‧gate dielectric layer
10b‧‧‧閘極 10b‧‧‧ gate
12‧‧‧導體層 12‧‧‧Conductor layer
14‧‧‧源極區 14‧‧‧ source area
16‧‧‧本體區 16‧‧‧ Body area
18‧‧‧汲極區 18‧‧‧Bungee Area
100‧‧‧基底 100‧‧‧Base
102‧‧‧摻雜區 102‧‧‧Doped area
104‧‧‧第一條狀摻雜區 104‧‧‧First strip doped area
106‧‧‧第二條狀摻雜區 106‧‧‧Second strip doping
108‧‧‧第三條狀摻雜區 108‧‧‧Third strip doping
C1‧‧‧第一最近距離 C1‧‧‧first closest distance
C2‧‧‧第二最近距離 C2‧‧‧ second closest distance
C3‧‧‧第三最近距離 C3‧‧‧ third closest distance
F‧‧‧扇形部分 F‧‧‧ sectoral part
D1‧‧‧第一方向 D1‧‧‧ first direction
D2‧‧‧第二方向 D2‧‧‧ second direction
E1‧‧‧第一端 E1‧‧‧ first end
E2‧‧‧第二端 E2‧‧‧ second end
L1~L5‧‧‧長度 L1~L5‧‧‧ length
P1‧‧‧第一間距 P1‧‧‧ first spacing
P2‧‧‧第二間距 P2‧‧‧Second spacing
P3‧‧‧第三間距 P3‧‧‧ third spacing
P4‧‧‧第四間距 P4‧‧‧fourth spacing
S1‧‧‧第一部分 S1‧‧‧Part 1
S2‧‧‧第二部分 S2‧‧‧ Part II
S3‧‧‧第三部分 S3‧‧‧Part III
R1‧‧‧第一區 R1‧‧‧ first district
R2‧‧‧第二區 R2‧‧‧Second District
R3‧‧‧第三區 R3‧‧‧ Third District
T‧‧‧三角形部分 T‧‧‧ triangle part
θ、θ1、θ2‧‧‧夾角 θ, θ 1 , θ 2 ‧‧‧ angle
圖1為本發明之第一實施例的半導體元件的上視示意圖。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top plan view showing a semiconductor device according to a first embodiment of the present invention.
圖2是圖1之A-A’切線的剖面示意圖。 Figure 2 is a schematic cross-sectional view taken along line A-A' of Figure 1.
圖3為本發明之第二實施例的半導體元件的上視示意圖。 Fig. 3 is a top plan view showing a semiconductor device according to a second embodiment of the present invention.
圖4為本發明之第三實施例的半導體元件的上視示意圖。 Fig. 4 is a top plan view showing a semiconductor device of a third embodiment of the present invention.
在以下的實施例中，當第一導電型為N型，第二導電型為P型；當第一導電型為P型，第二導電型為N型。P型摻雜例如是硼；N型摻雜例如是磷或是砷。在本實施例中，是以第一導電型為N型，第二導電型為P型為例來說明，但本發明並不以此 為限。 In the following embodiments, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, and the second conductivity type is N type. The P-type doping is, for example, boron; the N-type doping is, for example, phosphorus or arsenic. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type as an example, but the present invention does not Limited.
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。另外，圖式中的層與區域的厚度會為了清楚起見而放大。 The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. In addition, the thickness of layers and regions in the drawings will be exaggerated for clarity.
圖1為本發明之第一實施例的半導體元件的上視示意圖。圖3為本發明之第二實施例的半導體元件的上視示意圖。圖4為本發明之第三實施例的半導體元件的上視示意圖。為圖面清楚起見，在圖1、圖3以及圖4中僅繪示出半導體元件的部分彎角區。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top plan view showing a semiconductor device according to a first embodiment of the present invention. Fig. 3 is a top plan view showing a semiconductor device according to a second embodiment of the present invention. Fig. 4 is a top plan view showing a semiconductor device of a third embodiment of the present invention. For the sake of clarity of the drawing, only the partial corner regions of the semiconductor component are depicted in Figures 1, 3 and 4.
請參照圖1，本發明提供一種半導體元件，包括：基底100、具有第一導電型的摻雜區102、具有第二導電型的多個第一條狀摻雜區104、具有第二導電型的多個第二條狀摻雜區106以及具有第二導電型的多個第三條狀摻雜區108。基底100具有第一區R1、第二區R2以及第三區R3。第一區R1圍繞第二區R2與第三區R3，且第二區R2與第三區R3相鄰。基底100可例如是具有第一導電型的半導體基底，例如N型基底。半導體基底的材料例如是選自於由Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs與InP所組成的群組中的至少一種材料。在一實施例中，第一區R1、第二區R2以及第三區R3皆可例如是晶胞區(Cell region)。在其他實施例中，第一區R1可例如是終端區(Termination region)；而第二區R2與第三區R3則可例如是晶胞區。 Referring to FIG. 1, the present invention provides a semiconductor device comprising: a substrate 100, a doped region 102 having a first conductivity type, a plurality of first strip doped regions 104 having a second conductivity type, and a second conductivity type A plurality of second strip doped regions 106 and a plurality of third strip doped regions 108 having a second conductivity type. The substrate 100 has a first region R1, a second region R2, and a third region R3. The first zone R1 surrounds the second zone R2 and the third zone R3, and the second zone R2 is adjacent to the third zone R3. Substrate 100 can be, for example, a semiconductor substrate having a first conductivity type, such as an N-type substrate. The material of the semiconductor substrate is, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In an embodiment, the first region R1, the second region R2, and the third region R3 may each be, for example, a cell region. In other embodiments, the first region R1 may be, for example, a termination region; and the second region R2 and the third region R3 may be, for example, a unit cell region.
摻雜區102位於基底100中。在一實施例中，摻雜區102所植入的摻質可例如是磷或是砷，摻雜的濃度可例如是 2.2×1014/cm3至4.9×1015/cm3。 Doped region 102 is located in substrate 100. In an embodiment, the doping implanted in the doping region 102 may be, for example, phosphorus or arsenic, and the doping concentration may be, for example, 2.2×10 14 /cm 3 to 4.9×10 15 /cm 3 .
第一條狀摻雜區104位於第一區R1的摻雜區102中。第一條狀摻雜區104圍繞第二條狀摻雜區106與第三條狀摻雜區108。第一條狀摻雜區104可例如是同心環狀結構。在一實施例中，第一條狀摻雜區104可例如是圓形、橢圓、跑道形或其組合。相鄰第一條狀摻雜區104之間具有第一間距P1。在一實施例中，第一間距P1可例如0.05nm至2nm。第一條狀摻雜區104所植入的摻質可例如是硼，摻雜的濃度可例如是6.725×1014/cm3至1.496×1016/cm3。另外，雖然圖1僅繪示出兩個第一條狀摻雜區104、四個第二條狀摻雜區106以及四個第三條狀摻雜區108，但本發明不限於此。在其他實施例中，可依設計者的需求與元件面積來調整上述條狀摻雜區的數量。 The first strip doped region 104 is located in the doped region 102 of the first region R1. The first strip doped region 104 surrounds the second strip doped region 106 and the third strip doped region 108. The first strip-shaped doped region 104 can be, for example, a concentric annular structure. In an embodiment, the first strip-shaped doped region 104 can be, for example, a circle, an ellipse, a racetrack, or a combination thereof. A first pitch P1 is formed between adjacent first strip-shaped doping regions 104. In an embodiment, the first pitch P1 may be, for example, 0.05 nm to 2 nm. The dopant implanted in the first doped region 104 may be, for example, boron, and the doping concentration may be, for example, 6.725 × 10 14 /cm 3 to 1.496 × 10 16 /cm 3 . In addition, although FIG. 1 only shows two first strip-shaped doping regions 104, four second strip-shaped doping regions 106, and four third strip-shaped doping regions 108, the present invention is not limited thereto. In other embodiments, the number of strip-shaped doped regions described above can be adjusted according to the designer's needs and component area.
第二條狀摻雜區106位於第二區R2的摻雜區102中。第二條狀摻雜區106沿著第一方向D1交替排列。在一實施例中，第二條狀摻雜區106可例如是相互平行的條紋，其與第一條狀摻雜區104的一側(可例如是內側)相互垂直。相鄰第二條狀摻雜區106之間具有第二間距P2。在一實施例中，第二間距P2可例如0.05nm至2nm。第二條狀摻雜區106所植入的摻質可例如是硼，摻雜的濃度可例如是6.725×1014/cm3至1.496×1016/cm3。 The second strip-shaped doped region 106 is located in the doped region 102 of the second region R2. The second strip-shaped doped regions 106 are alternately arranged along the first direction D1. In an embodiment, the second strip-shaped doped regions 106 may be, for example, stripes parallel to each other that are perpendicular to one side (which may be, for example, the inner side) of the first strip-shaped doped region 104. There is a second pitch P2 between adjacent second strip-shaped doping regions 106. In an embodiment, the second pitch P2 may be, for example, 0.05 nm to 2 nm. The dopant implanted in the second strip-shaped doping region 106 may be, for example, boron, and the doping concentration may be, for example, 6.725×10 14 /cm 3 to 1.496×10 16 /cm 3 .
第三條狀摻雜區108位於第三區R3的摻雜區102中。在一實施例中，第三條狀摻雜區108可例如是配置於彎角區中，其可簡化彎角區的設計規範，進而提升彎角區的崩潰電壓。相鄰第 三條狀摻雜區108之間具有第三間距P3。在一實施例中，第三間距P3可例如0.05nm至2nm。第三條狀摻雜區108所植入的摻質可例如是硼，摻雜的濃度可例如是6.725×1014/cm3至1.496×1016/cm3。在一實施例中，第三條狀摻雜區108與第一條狀摻雜區104具有相同曲率。在一實施例中，第三條狀摻雜區108與第一條狀摻雜區104之間的第四間距P4可例如0.5nm至20nm。在一實施例中，第一間距P1、第二間距P2、第三間距P3以及第四間距P4可以相同，亦或不同。 The third strip-shaped doped region 108 is located in the doped region 102 of the third region R3. In an embodiment, the third strip-shaped doped region 108 can be disposed, for example, in a corner region, which simplifies the design specification of the corner region, thereby increasing the breakdown voltage of the corner region. A third pitch P3 is formed between adjacent third strip-shaped doped regions 108. In an embodiment, the third pitch P3 may be, for example, 0.05 nm to 2 nm. The dopant implanted in the third strip-shaped doping region 108 may be, for example, boron, and the doping concentration may be, for example, 6.725×10 14 /cm 3 to 1.496×10 16 /cm 3 . In an embodiment, the third strip-shaped doped region 108 has the same curvature as the first strip-shaped doped region 104. In an embodiment, the fourth pitch P4 between the third strip-shaped doping region 108 and the first strip-shaped doping region 104 may be, for example, 0.5 nm to 20 nm. In an embodiment, the first pitch P1, the second pitch P2, the third pitch P3, and the fourth pitch P4 may be the same or different.
詳細地說，第三條狀摻雜區108包括：第一部分S1、第二部分S2以及第三部分S3。第一部分S1具有第一端E1與第二端E2。在一實施例中，第一部分S1的形狀可例如是扇形、三角形或其組合。當第一部分S1的形狀例如是扇形(如圖1所示)，其第一端E1與第二端E2之間的夾角θ為90度。 In detail, the third strip-shaped doping region 108 includes a first portion S1, a second portion S2, and a third portion S3. The first portion S1 has a first end E1 and a second end E2. In an embodiment, the shape of the first portion S1 may be, for example, a sector, a triangle, or a combination thereof. When the shape of the first portion S1 is, for example, a sector shape (as shown in FIG. 1), the angle θ between the first end E1 and the second end E2 is 90 degrees.
另一方面，當第一部分S1的形狀例如是三角形(如圖3所示)，其第一端E1與第二端E2之間的夾角θ為90度。在一實施例中，第一部分S1中的第三條狀摻雜區108之間的第三間距P3與第二部分S2以及第三部分S3中的第三條狀摻雜區108之間的第三間距P3’不同。在一實施例中，第三間距P3小於第三間距P3’。相似地，與第一部分S1相鄰的第一條狀摻雜區104之間的第一間距P1亦與第二部分S2以及第三部分S3相鄰的第一條狀摻雜區104之間的第一間距P1’不同。在一實施例中，第一間距P1小於第一間距P1’。 On the other hand, when the shape of the first portion S1 is, for example, a triangle (as shown in FIG. 3), the angle θ between the first end E1 and the second end E2 is 90 degrees. In an embodiment, the third pitch P3 between the third strip-shaped doping regions 108 in the first portion S1 and the third strip-shaped doping region 108 in the second portion S2 and the third portion S3 The three pitches are different from P3'. In an embodiment, the third pitch P3 is smaller than the third pitch P3'. Similarly, a first pitch P1 between the first strip-shaped doped regions 104 adjacent to the first portion S1 is also between the first strip-shaped doped regions 104 adjacent to the second portion S2 and the third portion S3. The first pitch P1' is different. In an embodiment, the first pitch P1 is smaller than the first pitch P1'.
此外，當第一部分S1的形狀例如是扇形與三角形的組合(如圖4所示)，三角形部分T的夾角θ1可例如是0至90度，其具有第三間距P3。扇形部分F的夾角θ2可例如是0至90度，其具有第三間距P3’。第一部分S1的第一端E1與第二端E2之間的夾角θ(亦即夾角θ1與夾角θ2的總和)為90度。在一實施例中，第三間距P3與第三間距P3’不同，且第三間距P3小於第三間距P3’。相似地，與三角形部分T相鄰的第一條狀摻雜區104之間的第一間距P1亦與扇形部分F相鄰的第一條狀摻雜區104之間的第一間距P1’不同。在一實施例中，第一間距P1小於第一間距P1’。雖然圖4中僅繪示一個三角形與一個扇形，但本發明不以此為限。在其他實施例中，可依設計者的需求來調整上述三角形與扇形的數量、配置以及角度。 Further, when the shape of the first portion S1 is, for example, a combination of a sector and a triangle (as shown in FIG. 4), the angle θ 1 of the triangular portion T may be, for example, 0 to 90 degrees, which has a third pitch P3. The angle θ 2 of the sector portion F may be, for example, 0 to 90 degrees, which has a third pitch P3'. The angle θ between the first end E1 and the second end E2 of the first portion S1 (that is, the sum of the included angle θ 1 and the included angle θ 2 ) is 90 degrees. In an embodiment, the third pitch P3 is different from the third pitch P3', and the third pitch P3 is smaller than the third pitch P3'. Similarly, the first pitch P1 between the first strip-shaped doping regions 104 adjacent to the triangular portion T is also different from the first pitch P1' between the first strip-shaped doping regions 104 adjacent to the sector portion F. . In an embodiment, the first pitch P1 is smaller than the first pitch P1'. Although only one triangle and one sector are shown in FIG. 4, the invention is not limited thereto. In other embodiments, the number, configuration, and angle of the triangles and sectors described above can be adjusted as desired by the designer.
請回頭參考圖1，第二部分S2與第一部分S1的第一端E1相連。在一實施例中，第二部分S2可視為第一部分S1的延伸部，其自第一端E1沿著第一方向D1延伸。在一實施例中，第二部分S2的長度L1、L2、L3以及L4可分別例如是0nm至20nm。第二部分S2的第三條狀摻雜區108沿著第二方向D2交替排列。第一方向D1與第二方向D2不同。在一實施例中，第一方向D1與第二方向D2實質上垂直。在一實施例中，第二部分S2的長度L1、L2、L3以及L4可以相同。但本發明不以此為限，在其他實施例中，第二部分S2的長度L1、L2、L3以及L4亦可以不同。 Referring back to FIG. 1, the second portion S2 is connected to the first end E1 of the first portion S1. In an embodiment, the second portion S2 can be considered as an extension of the first portion S1 that extends from the first end E1 along the first direction D1. In an embodiment, the lengths L1, L2, L3, and L4 of the second portion S2 may be, for example, 0 nm to 20 nm, respectively. The third strip-shaped doped regions 108 of the second portion S2 are alternately arranged along the second direction D2. The first direction D1 is different from the second direction D2. In an embodiment, the first direction D1 is substantially perpendicular to the second direction D2. In an embodiment, the lengths L1, L2, L3, and L4 of the second portion S2 may be the same. However, the present invention is not limited thereto. In other embodiments, the lengths L1, L2, L3, and L4 of the second portion S2 may also be different.
第三部分S3與第一部分S1的第二端E2相連。第三部分 S3的第三條狀摻雜區108沿著第一方向D1交替排列。在一實施例中，第三部分S3可視為第一部分S1的延伸部，其自第二端E2沿著第二方向D2延伸。 The third portion S3 is connected to the second end E2 of the first portion S1. the third part The third strip-shaped doped regions 108 of S3 are alternately arranged along the first direction D1. In an embodiment, the third portion S3 can be considered as an extension of the first portion S1 that extends from the second end E2 along the second direction D2.
值得注意的是，第二條狀摻雜區106的末端與第一條狀摻雜區104的一側(可例如是內側)之間具有第一最近距離C1。在一實施例中，可藉由調整第一最近距離C1，以達到第一區R1與第二區R2之間的電荷平衡。在一實施例中，第三區R3的最外圍的第三條狀摻雜區108的切線延伸方向與第二條狀摻雜區106的末端之間具有一距離，其可視為第二條狀摻雜區106的延伸長度L5。在一實施例中，第二條狀摻雜區106的延伸長度L5可例如0nm至20nm。在一實施例中，第一最近距離C1可例如是小於或等於第四間距P4。 It is noted that the end of the second strip-shaped doped region 106 has a first closest distance C1 between one side of the first strip-shaped doped region 104 (which may be, for example, the inner side). In an embodiment, the charge balance between the first region R1 and the second region R2 can be achieved by adjusting the first closest distance C1. In an embodiment, the tangential extending direction of the outermost third strip-shaped doping region 108 of the third region R3 has a distance from the end of the second strip-shaped doping region 106, which may be regarded as a second strip shape. The extension length L5 of the doped region 106. In an embodiment, the extended length L5 of the second strip-shaped doping region 106 may be, for example, 0 nm to 20 nm. In an embodiment, the first closest distance C1 may be, for example, less than or equal to the fourth pitch P4.
另外，第二部分S2的第三條狀摻雜區108的末端與第二條狀摻雜區106的一側(可例如是右側)之間具有第二最近距離C2。同樣地，在本實施例中，亦可藉由調整第二最近距離C2，也就是調整第二部分S2的長度L1~L4，以達到第二區R2與第三區R3之間的電荷平衡。 In addition, the end of the third strip-shaped doping region 108 of the second portion S2 has a second closest distance C2 between one side of the second strip-shaped doping region 106 (which may be, for example, the right side). Similarly, in this embodiment, the charge balance between the second region R2 and the third region R3 can also be achieved by adjusting the second closest distance C2, that is, adjusting the lengths L1 to L4 of the second portion S2.
此外，第三部分S3的一側(可例如是左側)與第二條狀摻雜區106的一側(可例如是右側)之間具有第三最近距離C3。在一實施例中，第三最近距離C3大於或等於第二最近距離C2。而第三最近距離C3與第二最近距離C2的比值可例如是1至2。在本實施例中，亦可藉由調整第三最近距離C3，以達到第二區R2 與第三區R3之間的電荷平衡。 Further, a side of the third portion S3 (which may be, for example, the left side) and a side of the second strip-shaped doping region 106 (which may be, for example, the right side) have a third closest distance C3. In an embodiment, the third closest distance C3 is greater than or equal to the second closest distance C2. The ratio of the third closest distance C3 to the second closest distance C2 may be, for example, 1 to 2. In this embodiment, the second closest zone C2 can also be adjusted by adjusting the third closest distance C3. The charge balance with the third zone R3.
由於本實施例利用具有相同曲率的第三條狀摻雜區108配置在彎角區中，其可簡化彎角區的設計規範，進而提升彎角區的崩潰電壓。換言之，利用具有扇形或三角形形狀的第三條狀摻雜區108便可達到彎角區的電荷平衡。因此，本實施例可藉由簡單調整上述第一最近距離C1、第二最近距離C2以及第三最近距離C3，進而達到整體的電荷平衡。另外，由於本實施例已平衡彎角區的電荷，其使得P型摻雜柱與N型摻雜柱的設計不良(例如是摻雜柱寬度差異問題)所導致的崩潰不會出現在彎角區內。因此，本實施例可用以判定崩潰原因(例如是摻雜柱寬度差異問題或是摻雜柱佈局問題)，以利於元件設計者判斷。 Since the present embodiment utilizes the third strip-shaped doping region 108 having the same curvature to be disposed in the corner region, it can simplify the design specification of the corner region, thereby increasing the collapse voltage of the corner region. In other words, the charge balance of the corner region can be achieved by using the third strip-shaped doping region 108 having a fan shape or a triangular shape. Therefore, in this embodiment, the overall charge balance can be achieved by simply adjusting the first closest distance C1, the second closest distance C2, and the third closest distance C3. In addition, since the present embodiment has balanced the charge of the corner region, the collapse caused by the poor design of the P-type doped column and the N-type doped column (for example, the difference in the width of the doped column) does not occur at the corner. In the district. Therefore, the present embodiment can be used to determine the cause of the collapse (for example, a problem of the difference in the width of the doped column or the problem of the doped column layout) to facilitate the judgment of the component designer.
圖2是圖1之A-A’切線的剖面示意圖。為圖面清楚起見，在圖2中僅繪示出第二區R2中的剖面示意圖，但本發明不限於此。 Figure 2 is a schematic cross-sectional view taken along line A-A' of Figure 1. For the sake of clarity of the drawing, only a schematic cross-sectional view in the second region R2 is illustrated in FIG. 2, but the invention is not limited thereto.
請同時參照圖1與圖2，在一實施例中，半導體元件包括：基底100、具有第一導電型的摻雜區102、具有第二導電型的多個第二條狀摻雜區106、閘極結構10、導體層12、具有第一導電型的源極區14、具有第二導電型的本體區16以及汲極區18。摻雜區102與第二條狀摻雜區106位於基底100上。摻雜區102與第二條狀摻雜區106相互交替。 Referring to FIG. 1 and FIG. 2 simultaneously, in an embodiment, the semiconductor device includes: a substrate 100, a doped region 102 having a first conductivity type, and a plurality of second strip doping regions 106 having a second conductivity type, The gate structure 10, the conductor layer 12, the source region 14 having the first conductivity type, the body region 16 having the second conductivity type, and the drain region 18. The doped region 102 and the second strip doped region 106 are located on the substrate 100. The doped region 102 and the second strip doped region 106 alternate with each other.
閘極結構10位於摻雜區102上。閘極結構10包括閘介電層10a與閘極10b，其中閘介電層10a位於閘極10b與摻雜區102之間。導體層12位於閘極結構10上，其覆蓋閘極結構10以 及源極區14。在一實施例中，導體層12可例如是電性連接至源極區14。源極區14位於第二條狀摻雜區106上。本體區16位於源極區14與第二條狀摻雜區106之間。汲極區18位於基底100下方。 The gate structure 10 is located on the doped region 102. The gate structure 10 includes a gate dielectric layer 10a and a gate 10b, wherein the gate dielectric layer 10a is between the gate 10b and the doped region 102. The conductor layer 12 is located on the gate structure 10, which covers the gate structure 10 to And the source region 14. In an embodiment, the conductor layer 12 can be electrically connected to the source region 14, for example. Source region 14 is located on second strip doped region 106. The body region 16 is located between the source region 14 and the second strip doping region 106. The drain region 18 is located below the substrate 100.
綜上所述，本發明利用具有扇形或三角形形狀的第三條狀摻雜區配置在彎角區中，以簡化彎角區的設計規範，進而提升彎角區的崩潰電壓。再藉由調整第一最近距離，以達到第一區與第二區之間的電荷平衡。另外，亦可藉由調整第二最近距離以及第三最近距離，以達到第二區與第三區之間的電荷平衡。此外，由於本發明將具有扇形或三角形形狀的第三條狀摻雜區配置在彎角區中，其使得P型摻雜柱與N型摻雜柱的設計不良(例如是摻雜柱寬度差異)所導致的崩潰不會出現在彎角區內。因此，本發明可用以判定崩潰原因，以利於元件設計者判斷。 In summary, the present invention utilizes a third strip-shaped doped region having a fan shape or a triangular shape to be disposed in the corner region to simplify the design specification of the corner region, thereby increasing the collapse voltage of the corner region. The charge balance between the first zone and the second zone is achieved by adjusting the first closest distance. In addition, the charge balance between the second zone and the third zone can also be achieved by adjusting the second closest distance and the third closest distance. In addition, since the present invention arranges the third strip-shaped doping region having a fan shape or a triangular shape in the corner region, the poor design of the P-type doped column and the N-type doped column (for example, the difference in doping column width) The resulting crash does not occur in the corner area. Therefore, the present invention can be used to determine the cause of the collapse to facilitate the judgment of the component designer.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧基底 100‧‧‧Base
102‧‧‧摻雜區 102‧‧‧Doped area
104‧‧‧第一條狀摻雜區 104‧‧‧First strip doped area
106‧‧‧第二條狀摻雜區 106‧‧‧Second strip doping
108‧‧‧第三條狀摻雜區 108‧‧‧Third strip doping
C1‧‧‧第一最近距離 C1‧‧‧first closest distance
C2‧‧‧第二最近距離 C2‧‧‧ second closest distance
C3‧‧‧第三最近距離 C3‧‧‧ third closest distance
D1‧‧‧第一方向 D1‧‧‧ first direction
D2‧‧‧第二方向 D2‧‧‧ second direction
E1‧‧‧第一端 E1‧‧‧ first end
E2‧‧‧第二端 E2‧‧‧ second end
L1~L5‧‧‧長度 L1~L5‧‧‧ length
P1‧‧‧第一間距 P1‧‧‧ first spacing
P2‧‧‧第二間距 P2‧‧‧Second spacing
P3‧‧‧第三間距 P3‧‧‧ third spacing
P4‧‧‧第四間距 P4‧‧‧fourth spacing
S1‧‧‧第一部分 S1‧‧‧Part 1
S2‧‧‧第二部分 S2‧‧‧ Part II
S3‧‧‧第三部分 S3‧‧‧Part III
R1‧‧‧第一區 R1‧‧‧ first district
R2‧‧‧第二區 R2‧‧‧Second District
R3‧‧‧第三區 R3‧‧‧ Third District
θ‧‧‧夾角 Θ‧‧‧ angle
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