CN115437992A - PCIe link training method, device, equipment and storage medium - Google Patents

PCIe link training method, device, equipment and storage medium Download PDF

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CN115437992A
CN115437992A CN202211293048.7A CN202211293048A CN115437992A CN 115437992 A CN115437992 A CN 115437992A CN 202211293048 A CN202211293048 A CN 202211293048A CN 115437992 A CN115437992 A CN 115437992A
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state machine
ltssm
machine
data
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王廷平
郭继龙
郑茳
肖佐楠
匡启和
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CCore Technology Suzhou Co Ltd
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CCore Technology Suzhou Co Ltd
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Abstract

The application discloses a PCIe link training method, a PCIe link training device, PCIe link training equipment and a PCIe link training storage medium. The method comprises the following steps: acquiring state data of an LTSSM state machine in real time through software, and judging whether the LTSSM state machine is in a normal working state or not according to the state data; if not, judging whether the target sub-state machine has abnormal state or not based on the state data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine; and if the state exception exists, transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training entry so that the LTSSM state machine can execute PCIe link training logic again. After the state data is acquired by the software, the state abnormity judgment is carried out when the chip is not in the normal working state, the state conversion is carried out when the state is abnormal, the PCIe link training logic is executed again so as to enter the normal working state, the chip works normally through the assistance of the software logic, and the cost generated by tape out is avoided.

Description

PCIe link training method, device, equipment and storage medium
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a PCIe link training method, apparatus, device, and storage medium.
Background
When the PCIe (PCI Express) device is in a normal operating state (L0 state), data transmission and reception may be completed between the PCIe device and other PCIe devices through a PCIe link. When the PCIe bus carries out link training, the physical layer, the sending and receiving module and relevant link state information of PCIe equipment are initialized, and after the link training is successfully finished, the equipment at two ends of the PCIe link can carry out normal data exchange. The process of training a link between devices that conform to the PCIe protocol specification and the electrical specification is normally done by hardware logic. When the PCIe bus performs Link Training, an LTSSM (Link Training and Status State Machine) State Machine, also called PCIe Link Training State Machine, is used.
The mature, complete PCIe controller IP is currently available from internationally known semiconductor IP vendors. However, due to the complexity of the PCIe protocol itself and the wide range of devices that need to be adapted, the semiconductor chip companies that need to design PCIe controllers independently are challenged, often have many functional defects in the chip product, and need to repair the defects repeatedly and stream the chips several times. The cost of each chip is very high. Therefore, how to reduce the cost of the slide is a matter which needs to be solved at present.
Disclosure of Invention
In view of this, the present invention provides a PCIe link training method, apparatus, device, and medium, which can reduce the cost of tape-out. The specific scheme is as follows:
in a first aspect, the present application discloses a PCIe link training method, including:
acquiring state data of an LTSSM state machine in real time through software, and judging whether the LTSSM state machine is in a normal working state or not according to the state data;
if not, judging whether the target sub-state machine has abnormal state or not based on the state data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine;
and if the state exception exists, transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training entry so that the LTSSM state machine can execute PCIe link training logic again.
Optionally, the determining, based on the state data and a determination logic corresponding to the target sub-state machine in the LTSSM state machine, whether the target sub-state machine has a state anomaly includes:
if the target sub-state machine is a Detect state machine, judging whether the state is changed or not according to the state data in a Detect.
And after the state is changed and the state enters a detect.Act or detect.Wait process, carrying out state monitoring according to the state data, and if the next target sub-state machine is not entered within a first preset time, judging that the state of the Detect state machine is abnormal.
Optionally, the determining, based on the state data and the determination logic corresponding to the target sub-state machine in the LTSSM state machine, whether the target sub-state machine has a state anomaly includes:
if the target sub-state machine is a Polling state machine, judging whether the state is a polling.active state or not according to the state data in a polling.active process, and if the state is the polling.active state or a Detect state is detected in a second preset time, judging that the Polling state has state abnormality;
if the current state is not a polling.active state, polling.compatibility state monitoring is carried out according to the state data, and if the current state is a polling.compatibility state within a third preset time period, the Polling state machine is judged to have abnormal state;
and if the current state is not a polling.compatibility state, performing polling.configuration state monitoring according to the state data, and if the polling.configuration state is the polling.configuration state or a Detect state is detected in a fourth preset time period, determining that the Polling state has abnormal state.
Optionally, the determining, based on the state data and a determination logic corresponding to the target sub-state machine in the LTSSM state machine, whether the target sub-state machine has a state anomaly includes:
if the target sub-state machine is a Configuration state machine, performing exception judgment of the corresponding target Configuration sub-state in each target Configuration sub-process according to the state data, and judging that the Configuration state machine has an exception state when any one target Configuration sub-state has an exception state;
wherein, the performing the exception judgment of the corresponding target Configuration subprocess in each target Configuration subprocess includes:
and if the current target Configuration subprocess does not enter the next target Configuration subprocess within the corresponding preset duration of the subprocess, or the Detect state is detected, judging that the current target Configuration subprocess has abnormal state.
Optionally, the determining, based on the state data and a determination logic corresponding to the target sub-state machine in the LTSSM state machine, whether the target sub-state machine has a state anomaly includes:
if the target sub-state machine is a Recovery state machine, judging whether the current state hits the state in a preset state list or not according to the state data, and if so, judging that the Recovery state machine has abnormal state; the preset state list comprises a Detect state, a Loopback state, a Disable state, a Hot Reset state and a Configuration state.
Optionally, after determining whether the current state hits a state in a preset state list according to the state data, the method further includes:
and if the current state does not hit the state in the preset state list and is not the normal working state, transferring the current state to a Recovery state machine entry.
Optionally, after determining whether the LTSSM state machine is in a normal working state according to the state data, the method further includes:
if the LTSSM state machine is in a normal working state, judging whether the actual speed of the LTSSM state machine entering the normal working state reaches a target speed or not;
if yes, ending the PCIe link training;
and if not, transferring the state of the LTSSM state machine from the normal working state to a Recovery state.
In a second aspect, the present application discloses a PCIe link training apparatus, including:
the state data acquisition module is used for acquiring the state data of the LTSSM state machine in real time through software and judging whether the LTSSM state machine is in a normal working state or not according to the state data;
the state abnormity judging module is used for judging whether the state abnormity exists in the target sub-state machine or not based on the state data and the judging logic corresponding to the target sub-state machine in the LTSSM state machine if the state abnormity does not exist in the target sub-state machine;
and the resetting module is used for transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training inlet if the state exception exists so that the LTSSM state machine can execute PCIe link training logic again.
In a third aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
and the processor is used for executing the computer program to realize the PCIe link training method.
In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program when executed by the processor implements the PCIe link training method described above.
In the application, the state data of the LTSSM state machine is acquired in real time through software, and whether the LTSSM state machine is in a normal working state or not is judged according to the state data; if not, judging whether the target sub-state machine has abnormal state or not based on the state data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine; and if the state exception exists, transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training entry so that the LTSSM state machine can execute PCIe link training logic again. Therefore, the state data is acquired by software, the state is judged, the state abnormity is judged when the state is not in the normal working state, the state is migrated when the state is abnormal, the PCIe link training logic is executed again so as to enter the normal working state, and the hardware logic is replaced by the software logic part, so that the chip works normally, and the tape-out cost is saved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a PCIe link training method provided in the present application;
FIG. 2 is a flow diagram of the transition logic of the LTSSM state machine;
FIG. 3 is a flowchart of a specific PCIe link training method provided herein;
fig. 4 is a flowchart of a Detect state machine in a PCIe link training process provided in the present application;
fig. 5 is a flowchart of a Polling state machine in a PCIe link training process provided in the present application;
fig. 6 is a flowchart of a Configuration state machine in a PCIe link training process provided in the present application;
FIG. 7 is a flow diagram of a Recovery state machine in a PCIe link training process according to the present application;
FIG. 8 is a schematic structural diagram of a PCIe link training device provided in the present application;
fig. 9 is a block diagram of an electronic device provided in the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, mature, complete PCIe controller IP is typically from an internationally known semiconductor IP vendor. However, due to the complexity of the PCIe protocol itself and the wide range of devices that need to be adapted, the semiconductor chip companies that need to design PCIe controllers independently are challenged, often have many functional defects in the chip product, and need to repair the defects repeatedly and stream the chips several times. The cost of each chip is very high. In order to overcome the technical problem, the application provides a method for training a software logic-assisted PCIe link, which can realize normal training of the PCIe link.
The embodiment of the application discloses a PCIe link training method, as shown in fig. 1, the method may include the following steps:
step S11: the method comprises the steps of acquiring state data of the LTSSM state machine in real time through software, and judging whether the LTSSM state machine is in a normal working state or not according to the state data.
First, a brief description will be made of the logic of a hardware LTSSM state machine, such as the switching logic of the LTSSM state machine shown in fig. 2, where the hardware LTSSM state machine is composed of 11 states of Detect, polling, configuration, disable, hot Reset, loopback, L0 (normal operating state), L0s, L1, L2, and Recovery. These states are associated with link training, link retraining, ASPM (Active State Power Management) of the PCIe bus, and Power Management of the system software, respectively.
In this embodiment, first, state data of the LTSSM state machine is obtained in real time through software, and whether the LTSSM state machine is in a normal working state is determined according to the state data. That is, according to the current state data of the LTSSM state machine, it is determined whether the LTSSM state machine is in a normal working state, that is, an L0 state.
In this embodiment, before the acquiring, by software, the state data of the LTSSM state machine in real time, the closing of the PCIe low-power-consumption management mechanism is further included. Namely, when the exception problem is discovered in the assistance of software in the follow-up process, the state conversion is successfully realized through the assistance of the software, and the PCIe low-power-consumption management mechanism is closed in advance.
Step S12: if not, judging whether the target sub-state machine has abnormal state or not based on the state data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine.
In this embodiment, if the LTSSM state machine is not in the normal operating state, whether the target sub-state machine has the abnormal state is determined based on the state data and the determination logic corresponding to the target sub-state machine in the LTSSM state machine. That is, if the LTSSM state machine is not in the L0 state, it is further determined whether the state of the target sub-state machine in the state machine is abnormal, specifically, the determination is performed according to the state data acquired in real time and the determination logic corresponding to each target sub-state machine. It should be noted that, in this embodiment, the state data is not acquired only once, but the current latest state data is acquired every time the state judgment needs to be performed, so that it can be judged whether the current state is abnormal. The target sub-state machines include, but are not limited to, a Detect state machine, a Polling state machine, a Configuration state machine, and a Recovery state machine.
Step S13: and if the state exception exists, transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training entry so that the LTSSM state machine can execute PCIe link training logic again.
In this embodiment, when the state anomaly of a certain target sub-state machine is determined, and it is determined that the target sub-state machine has the state anomaly, the state of the LTSSM state machine is transferred to the LTSSM training entry, that is, the initial state of the LTSSM state machine, that is, the PCIe controller and the PCIe PHY hardware logic are reset, so that the LTSSM state machine re-executes the PCIe link training logic. Therefore, the software logic part replaces hardware logic, and state transfer is carried out when the state is abnormal, so that the chip works normally, the tape-out cost can be saved, the defects of the PCIe hardware logic can be repaired in the design of the next chip, and a large amount of research and development funds are saved.
If the target sub-state machines include a Detect state machine, a Polling state machine, a Configuration state machine, and a Recovery state machine, the PCIe link training process, as shown in fig. 3, for example, includes the following steps:
101: an LTSSM training inlet, a state timer is initialized; the state timer may be used to time the duration of a certain state;
102: reading a current state value of the LTSSM to judge whether the current state is in an L0 state, if so, transferring a software state machine to 107, and otherwise, entering 103 a Detect state machine;
103: a Detect state machine; predicting the transition of the Detect sub-state based on the state data of the LTSSM, if the Detect sub-state is abnormal, entering 101 the LTSSM training entrance for retraining, and otherwise entering 104 the Polling state machine.
104: a Polling state machine; and predicting Polling sub-state transition based on the state data of the LTSSM, if Polling sub-state abnormity is found, entering 101LTSSM training entries for retraining, and otherwise entering 105Configuration state machines.
105: a Configuration state machine; predicting Configuration sub-state transition based on state data of LTSSM, if the Configuration sub-state is found to be abnormal, entering 101LTSSM training entry for retraining, otherwise, judging the state machine to enter 106Recovery state machine according to 109LTSSM state data, or judging the state machine to enter 107LTSSM L0 state machine according to 108LTSSM state data.
106: and predicting Recovery sub-state transition based on the state data of the LTSSM by using a Recovery state machine, if the Recovery sub-state is found to be abnormal, entering a 101LTSSM training entry for retraining, and otherwise, entering a 107LTSSM L0 state machine.
In this embodiment, after determining whether the LTSSM state machine is in a normal operating state according to the state data, the method may further include: if the LTSSM state machine is in a normal working state, judging whether the actual speed of the LTSSM state machine entering the normal working state reaches a target speed or not; if yes, ending the PCIe link training; and if not, transferring the state of the LTSSM state machine from the normal working state to a Recovery state. That is, when the LTSSM enters the L0 state machine, when the target rate for configuring PCIe is 5GT/s or higher, and the LTSSM enters L0 at the rate of 2.5GT/s, the LTSSM enters the Recovery state again and trains to the higher rate stage. The LTSSM L0 training is completed and the current rate is the target rate 2.5GT, 5GT, or higher, the PCIe link LTSSM training is finished.
As can be seen from the above, in this embodiment, the state data of the LTSSM state machine is obtained in real time through software, and whether the LTSSM state machine is in a normal working state is determined according to the state data; if not, judging whether the target sub-state machine has abnormal state or not based on the state data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine; and if the state exception exists, transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training entry so that the LTSSM state machine can execute PCIe link training logic again. Therefore, the state data is acquired by software, the state is judged, the state abnormity is judged when the state is not in the normal working state, the state is migrated when the state is abnormal, the PCIe link training logic is executed again so as to enter the normal working state, and the hardware logic is replaced by the software logic part, so that the chip works normally, and the tape-out cost is saved.
On the basis of the above embodiment, the determining logic that is based on the state data and the corresponding target sub-state machine in the LTSSM state machine determines whether the target sub-state machine has a state anomaly, and includes different determining steps according to different target sub-state machines.
If the target sub-state machine is a Detect state machine, the state data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine judge whether the target sub-state machine has state abnormality, and the method comprises the following steps:
s21: judging whether the state is changed or not according to the state data in the detect.Quiet process;
s22: and after the state is changed and enters a detect.Act or detect.Wait process, carrying out state monitoring according to the state data, and if the next target sub-state machine is not entered within a first preset time, judging that the Detect state machine has abnormal state.
It will be appreciated that, for example, as shown in fig. 4, the Detect state machine logic first enters the 101LTSSM training entry block after powering up the PCIe device, the entry block representing a software entry flag, with no logic running within the block. Then, the logic enters 201detect.Quiet or Pre detect.Quiet process to read LTSSM state data to judge the current state, if the state changes, 202detect.Act or detect.Wait is entered, if the state does not change, 203 is executed to circularly read the LTSSM state value until the state changes. Entering a 202detect.act or detect.wait block, reading LTSSM state data to judge the current state, setting a first preset time length which can be a 24-millisecond timeout timer, if the LTSSM state value is transferred to a Polling stage, entering a 301Polling state machine entry block after step 205, otherwise executing 204, namely after 24-millisecond timeout, entering 101LTSSM to start a training process.
If the target sub-state machine is a Polling state machine, the determining whether the target sub-state machine has a state anomaly based on the state data and a determination logic corresponding to the target sub-state machine in the LTSSM state machine may include the following steps:
s31: judging whether the state is a Polling.active state or not according to the state data in the Polling.active process, and if the Polling.active state is all in a second preset time or a Detect state is detected, judging that the Polling state has abnormal state;
s32: if the current state is not a polling.active state, polling.company state monitoring is carried out according to the state data, and if the polling.company states exist in a third preset time, the Polling state machine is judged to have abnormal states;
s33: and if the current state is not a polling.compatibility state, performing polling.configuration state monitoring according to the state data, and if the polling.configuration state is all the polling.configuration state within a fourth preset time period or a Detect state is detected, determining that the Polling state has an abnormal state.
It is understood that the Polling state machine logic is as follows: and the 301Polling state machine entry block enters a 302polling.active process, and the current state is judged by circularly reading the LTSSM state value and setting a second preset time, specifically, a 48 millisecond timeout timer is set. If the state value is not polling.active state, entering 303polling.company state judgment process, or entering 101LTSSM to start training process. For example, as shown in fig. 5, the specific process is as follows:
1. if the state value of the LTSSM is detected to be a polling.active state, the state is kept until 48 milliseconds is overtime, and no state transition is generated, or a Detect stage state value is detected within 48 milliseconds, entering 101LTSSM to start a training process;
2. otherwise, if the state is not Polling.active, entering 303Polling.company state judgment process;
3. performing 303Polling.compatibility state judgment process, and entering 305Polling.configuration process if the judgment result is that the status is not Polling.compatibility state;
4. the status is judged as Polling.Complence, and the process is entered 304Polling.Complence.
5. After entering 304polling. Compatibility process, circularly reading LTSSM state data to judge the current state and setting a third preset time length, specifically setting a 98 millisecond timeout timer, if detecting that the LTSSM state value is polling. Compatibility state, and if the state is maintained to 98 millisecond timeout timer, and still there is no state transition, entering 101LTSSM to start training process;
6. otherwise, if the polling.company state changes, entering 302polling.active process;
7. and entering a 305polling. Configuration process, circularly reading the LTSSM state data to judge the current state and setting a fourth preset time length, which may be specifically setting a 96 millisecond timeout timer. If the state value of the LTSSM is detected to be a polling. Configuration state, the state is kept until 96 milliseconds is overtime and no state transition is generated, or a Detect stage state value is detected within 96 milliseconds, entering 101LTSSM to start a training process;
8. configuration state machine entry block 401 is entered if the state value is not polling. Configuration state and not Detect stage state value during 96 milliseconds.
If the target sub-state machine is a Configuration state machine, the determining whether a state exception exists in the target sub-state machine based on the state data and the determination logic corresponding to the target sub-state machine in the LTSSM state machine may include:
s41: according to the state data, carrying out abnormity judgment on the corresponding target Configuration subprocess in each target Configuration subprocess, and judging that the Configuration state machine has abnormal state when any one target Configuration subprocess has abnormal state;
s42: and if the current target Configuration subprocess does not enter the next target Configuration subprocess within the corresponding preset duration of the subprocess, or the Detect state is detected, judging that the current target Configuration subprocess has abnormal state.
The target Configuration sub-process includes Configuration. The preset time length of each sub-state is used for judging whether the corresponding target Configuration sub-state is overtime or not. For example, as shown in fig. 6, the specific process of Configuration state machine logic is as follows:
1. the 401Configuration state machine entry enters 402configuration.linkwidth.start procedure, determines the current state by reading the LTSSM state values in a loop and sets a 64ms timeout timer, and if the 64ms duration state is the non-configuration.linkwidth.start state, enters 404configuration.linkwidth.accept procedure. If the condition 403 64ms is overtime or the Detect state is detected to be established, entering 101LTSSM to start a training process;
2. after entering 404configuration.linkwidth.accept process, the status value of the LTSSM is read circularly to judge the current status and set a 6 millisecond timeout timer, if the status is the non-configuration.linkwidth.accept status in the 6 millisecond period, the process enters 406configuration.linknum.wait process. If the condition 405 6ms is overtime or a Detect state is detected to be established, entering 101LTSSM to start a training process;
3. after entering the 406configuration.linknum.wait process, the LTSSM state value is read circularly to judge the current state and a 6 millisecond timeout timer is set, if the state value is not the configuration.linknum.wait state during 6 milliseconds, the 408configuration.linknum.accept process is entered. If the condition 407 6ms times out or the Detect state is detected to be established, entering 101LTSSM to start a training process;
4. after entering the 408configuration. Linknum. Accept procedure, the LTSSM state value is read cyclically to determine the current state and set the 4 msec timeout timer, and if the 4 msec period state is the non-configuration. Linknum. Accept state, the 410configuration. Complete procedure is entered. If the condition 409 is overtime for 4ms or the Detect state is detected to be established, entering 101LTSSM to start a training process;
5. after entering 410configuration. If the condition 4114ms is overtime or the Detect state is detected to be established, entering 101LTSSM to start a training process;
6. the 412configuration.idle process loops reading the LTSSM state value to determine the current state and setting a 4-ms timeout timer, and if the 4-ms duration state is a non-configuration.idle state, it goes to the 107LTSSM L0 state block. If the condition 413 ms times out or Detect that the Detect state is true, 101LTSSM is entered to start the training process.
And if the target sub-state machine is a Recovery state machine. The determining whether the target sub-state machine has a state anomaly based on the state data and the determination logic corresponding to the target sub-state machine in the LTSSM state machine may include the following steps:
s51: if the target sub-state machine is a Recovery state machine, judging whether the current state hits the state in a preset state list or not according to the state data, and if so, judging that the Recovery state machine has abnormal state; the preset state list comprises a Detect state, a Loopback state, a Disable state, a Hot Reset state and a Configuration state.
S52: and if the current state does not hit the state in the preset state list and is not the normal working state, transferring the current state to a Recovery state machine inlet.
The Recovery state machine logic reads the LTSSM state value for 501 the Recovery state machine entry block and then enters 502 the Detect state decision process. The judgment process is shown in FIG. 7:
1. after entering 502 a Detect state judgment process, judging whether the current state value is in a Detect stage or not through LTSSM state data, and if so, entering 101LTSSM to start a training process. If the judgment result is no, the 503Loopback state judgment process is entered.
2. After entering a 503Loopback state judgment process, judging whether the current state value is in a Loopback stage or not through LTSSM state data, and if so, entering a 101LTSSM training process. If not, the Disable state determination process is entered 504.
3. After entering 504 a Disable state judgment process, judging whether the current state value is in a Disable stage through LTSSM state data, and if so, entering 101LTSSM to start a training process. If the determination is no, the process proceeds to 505Hot Reset status determination.
4. After the 505Hot Reset state judgment process is entered, judging whether the current state value is in the Hot Reset stage or not through the LTSSM state data, and if so, entering the 101LTSSM training process. If not, the Configuration state determination process is entered 506.
5. After entering 506Configuration state judgment process, judging whether current state value is in Configuration stage or not by LTSSM state data, if yes, entering 101LTSSM to start training process. If not, entering 507L0 state judgment process.
6. After entering 507L0 state judgment process, judging whether the current state value is in L0 stage by LTSSM state data, if not, entering 501Recovery state machine entry block. If yes, go to 107LTSSM L0 status block. 107LTSSM L0 state block, when PCIe device enters this state and keeps L0 state unchanged, mark PCIe link training is completed.
As can be seen, in this embodiment, a software-assisted control training scheme is provided for the problem that training cannot be completed in the PCIe bus link training process due to incomplete hardware logic. Aiming at the problems that the working state of RX logic of an opposite terminal cannot be detected and the Lane number cannot be automatically identified in an LTSSM state machine during PCIe link training, the correct conversion of the PCIe training state is completed through software logic of PCIe equipment, and the PCIe link training between PCIe RC (Root Complex) and EP (End Point, PCIe common equipment) is finally completed and the LTSSM state machine enters an L0 state.
Correspondingly, an embodiment of the present application further discloses a PCIe link training apparatus, as shown in fig. 8, the apparatus includes:
the state data acquisition module 11 is configured to acquire state data of the LTSSM state machine in real time through software, and determine whether the LTSSM state machine is in a normal working state according to the state data;
a state anomaly determination module 12, configured to determine, if the state of the target sub-state machine is abnormal, based on the state data and a determination logic corresponding to the target sub-state machine in the LTSSM state machine;
and a resetting module 13, configured to transfer the state of the LTSSM state machine from the target sub-state machine to an LTSSM training entry if a state exception exists, so that the LTSSM state machine re-executes PCIe link training logic.
As can be seen from the above, in this embodiment, the state data of the LTSSM state machine is obtained in real time through software, and whether the LTSSM state machine is in a normal working state is determined according to the state data; if not, judging whether the target sub-state machine has abnormal state or not based on the state data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine; and if the state exception exists, transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training entry so that the LTSSM state machine can execute PCIe link training logic again. Therefore, the state data is acquired through software, the state judgment is carried out, the state abnormity judgment is carried out when the state data is not in the normal working state, the state transition is carried out when the state is abnormal, the PCIe link training logic is re-executed so as to enter the normal working state, and the hardware logic is replaced by the software logic part, so that the chip works normally, and the cost of tape-out is saved.
In some specific embodiments, the state anomaly determination module 12 may specifically include:
a Detect state machine state judgment unit, configured to judge, if the target sub-state machine is a Detect state machine, whether a state changes according to the state data in a Detect.
And the state abnormity determining unit is used for monitoring the state according to the state data after the state is changed and the state enters a detect.Act or detect.Wait process, and if the next target sub-state machine is not entered within a first preset time period, determining that the state abnormity exists in the Detect state machine.
In some embodiments, the state anomaly determination module 12 may specifically include:
a Polling state machine state judging unit, configured to judge whether a state is a polling.active state according to the state data in a polling.active process if the target sub-state machine is a Polling state machine, and determine that a state abnormality exists in the Polling state if both polling.active states exist or a Detect state is detected within a second preset time period;
a first judging unit for judging the state abnormality of the Polling state machine, configured to perform polling.compatibility state monitoring according to the state data if the current state is not polling.active state, and judge that the Polling state machine has a state abnormality if all polling.compatibility states exist within a third preset time period;
and the Polling state machine state abnormality second unit is used for monitoring a Polling state according to the state data if the current state is not a polling.compatibility state, and determining that the Polling state has a state abnormality if the polling.configuration state or a Detect state is detected within a fourth preset time period.
In some specific embodiments, the state anomaly determination module 12 may specifically include:
configuration state machine state judgment means for, if the target sub-state machine is a Configuration state machine, performing abnormality judgment of the corresponding target Configuration sub-state in each target Configuration sub-process according to the state data, and judging that the Configuration state machine has a state abnormality when any one of the target Configuration sub-states has a state abnormality;
the Configuration state machine state determining unit is further configured to determine that the current target Configuration subprocess has a state exception if the current target Configuration subprocess does not enter the next target Configuration subprocess within the preset time duration of the corresponding subprocess, or a Detect state is detected.
In some embodiments, the state anomaly determination module 12 may specifically include:
a Recovery state machine state judgment unit, configured to judge whether a current state hits a state in a preset state list according to the state data if the target sub-state machine is a Recovery state machine, and if so, judge that the Recovery state machine has a state abnormality; the preset state list includes Detect state, loopback state, disable state, hot Reset state and Configuration state.
In some embodiments, the Recovery state machine state determining unit may specifically include:
and the state transfer unit is used for transferring the current state to the Recovery state machine inlet if the current state does not hit the state in the preset state list and is not the normal working state.
In some embodiments, the PCIe link training apparatus may specifically include:
the speed judging unit is used for judging whether the actual speed of the LTSSM state machine in the normal working state reaches the target speed or not if the LTSSM state machine is in the normal working state;
a training ending unit, which is used for ending the PCIe link training if the PCIe link training is reached;
and the state transfer unit is used for transferring the state of the LTSSM state machine from the normal working state to a Recovery state if the state is not reached.
Further, the embodiment of the present application also discloses an electronic device, which is shown in fig. 9, and the content in the drawing cannot be considered as any limitation to the application scope.
Fig. 9 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. The memory 22 is configured to store a computer program, and the computer program is loaded and executed by the processor 21 to implement relevant steps in the PCIe link training method disclosed in any one of the foregoing embodiments.
In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and a communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, and is not specifically limited herein; the input/output interface 25 is configured to acquire external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.
In addition, the storage 22 is used as a carrier for resource storage, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon include an operating system 221, a computer program 222, data 223 including state data, etc., and the storage may be a transient storage or a permanent storage.
The operating system 221 is used for managing and controlling each hardware device and the computer program 222 on the electronic device 20, so as to realize the operation and processing of the mass data 223 in the memory 22 by the processor 21, and may be Windows Server, netware, unix, linux, and the like. The computer programs 222 may further include computer programs that can be used to perform other specific tasks in addition to the computer programs that can be used to perform the PCIe link training method performed by the electronic device 20 disclosed in any of the foregoing embodiments.
Further, an embodiment of the present application also discloses a computer storage medium, where computer-executable instructions are stored, and when the computer-executable instructions are loaded and executed by a processor, the PCIe link training method steps disclosed in any of the foregoing embodiments are implemented.
In the present specification, the embodiments are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same or similar parts between the embodiments are referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The PCIe link training method, apparatus, device, and medium provided by the present invention are described in detail above, and a specific example is applied in the present disclosure to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. A PCIe link training method, comprising:
acquiring state data of an LTSSM state machine in real time through software, and judging whether the LTSSM state machine is in a normal working state or not according to the state data;
if not, judging whether the target sub-state machine has abnormal state or not based on the state data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine;
and if the state exception exists, transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training entry so that the LTSSM state machine can execute PCIe link training logic again.
2. The PCIe link training method of claim 1, wherein said determining whether a state exception exists in a target sub-state machine in the LTSSM state machine based on the state data and a corresponding determination logic of the target sub-state machine comprises:
if the target sub-state machine is a Detect state machine, judging whether the state is changed according to the state data in the Detect.
And after the state is changed and enters a detect.Act or detect.Wait process, carrying out state monitoring according to the state data, and if the next target sub-state machine is not entered within a first preset time, judging that the Detect state machine has abnormal state.
3. The PCIe link training method of claim 1, wherein the determining whether the target sub-state machine has a status exception based on the status data and a determination logic corresponding to the target sub-state machine in the LTSSM state machine comprises:
if the target sub-state machine is a Polling state machine, judging whether the state is polling.active state or not according to the state data in a polling.active process, and if the state is polling.active state or a Detect state is detected in a second preset time, judging that the Polling state has state abnormality;
if the current state is not a polling.active state, polling.compatibility state monitoring is carried out according to the state data, and if the current state is a polling.compatibility state within a third preset time period, the Polling state machine is judged to have abnormal state;
and if the current state is not a polling.compatibility state, performing polling.configuration state monitoring according to the state data, and if the polling.configuration state is the polling.configuration state or a Detect state is detected in a fourth preset time period, determining that the Polling state has abnormal state.
4. The PCIe link training method of claim 1, wherein said determining whether a state exception exists in a target sub-state machine in the LTSSM state machine based on the state data and a corresponding determination logic of the target sub-state machine comprises:
if the target sub-state machine is a Configuration state machine, performing exception judgment on a corresponding target Configuration sub-state in each target Configuration sub-process according to the state data, and judging that the Configuration state machine has an exception when any one target Configuration sub-state has an exception;
wherein, the determining the abnormality of the corresponding target Configuration subprocess in each target Configuration subprocess includes:
and if the current target Configuration subprocess does not enter the next target Configuration subprocess within the corresponding preset duration of the subprocess, or the Detect state is detected, judging that the current target Configuration subprocess has abnormal state.
5. The PCIe link training method of claim 1, wherein the determining whether the target sub-state machine has a status exception based on the status data and a determination logic corresponding to the target sub-state machine in the LTSSM state machine comprises:
if the target sub-state machine is a Recovery state machine, judging whether the current state hits the state in a preset state list or not according to the state data, and if so, judging that the Recovery state machine has abnormal state; the preset state list comprises a Detect state, a Loopback state, a Disable state, a Hot Reset state and a Configuration state.
6. The PCIe link training method of claim 5, wherein after determining whether the current state hits in a state in a predetermined state list according to the state data, further comprising:
and if the current state does not hit the state in the preset state list and is not the normal working state, transferring the current state to a Recovery state machine entry.
7. The PCIe link training method of any one of claims 1 to 6, wherein after determining whether the LTSSM state machine is in a normal operating state according to the state data, further comprising:
if the LTSSM state machine is in a normal working state, judging whether the actual speed of the LTSSM state machine in the normal working state reaches a target speed or not;
if yes, ending the PCIe link training;
and if not, transferring the state of the LTSSM state machine from the normal working state to a Recovery state.
8. A PCIe link training device, comprising:
the state data acquisition module is used for acquiring the state data of the LTSSM state machine in real time through software and judging whether the LTSSM state machine is in a normal working state or not according to the state data;
the state abnormity judging module is used for judging whether the state abnormity exists in the target sub-state machine or not based on the state data and the judging logic corresponding to the target sub-state machine in the LTSSM state machine if the state abnormity does not exist in the target sub-state machine;
and the resetting module is used for transferring the state of the LTSSM state machine from the target sub-state machine to an LTSSM training inlet if the state exception exists so that the LTSSM state machine can execute PCIe link training logic again.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the PCIe link training method as recited in any one of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program; wherein the computer program when executed by the processor implements the PCIe link training method as recited in any one of claims 1 to 7.
CN202211293048.7A 2022-10-21 2022-10-21 PCIe link training method, device, equipment and storage medium Pending CN115437992A (en)

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Application Number Priority Date Filing Date Title
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