CN107993430B - Method for improving stability of Ethernet PHY chip of concentrator - Google Patents
Method for improving stability of Ethernet PHY chip of concentrator Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention relates to a method for improving the stability of an Ethernet PHY chip of a concentrator, which comprises the following steps of 1, configuring parameters of an MAC controller of a main control chip of the concentrator; 2. setting a periodic polling function, inquiring the value of a connection state register of the PHY chip by using the frequency f, and judging the connection state of the current link by using a slip judgment mode; 3. if the connection state of the current link is disconnected, turning to the step 2; if the connection state of the current link is access, checking the parameter values of all working registers of the PHY chip; 4. if the connection state of the current link is access and the PHY chip reset mark is 1, renegotiating the Ethernet working mode; otherwise, go to step 2. The invention improves the accuracy of judgment, ensures the real-time control of the main control chip on the working condition of the PHY chip, improves the response speed of the main control chip when the PHY chip is abnormal, ensures the reliability of communication and improves the working efficiency of the main control chip.
Description
Technical Field
The invention belongs to the technical field of power consumption information acquisition systems, and particularly relates to a method for improving the stability of an Ethernet PHY chip of a concentrator in a complex electromagnetic environment.
Background
With the continuous promotion of the informatization transformation of the power system, the use amount of the concentrator in the meter reading system is continuously increased. Ethernet is widely used in concentrators as an efficient communication means. Because the environment of the concentrator in actual work is complex and changeable, most concentrators are in the environment of strong magnetic field and high static electricity. The PHY chip is used as a key core component of Ethernet communication, and how to stably work in a complicated electromagnetic environment on site directly determines the communication quality of the Ethernet communication.
At present, the stability of the PHY chip is generally improved by increasing a protection device of hardware to avoid the entry of an interference signal. However, this measure has a great risk that once the protection device fails, the PHY chip is completely in a strong interference environment, and at this time, if there is no good measure in software, the PHY chip may work disorderly and affect the normal communication of the ethernet.
Disclosure of Invention
In view of the above technical problems, the present invention provides a method for improving the stability of a PHY chip of an ethernet network of a concentrator, which includes the following steps:
step 1, when a concentrator initially runs, firstly configuring parameters of an MAC (media access control) controller of a concentrator main control chip;
step 2, setting a periodic polling function, inquiring the value of a connection state register of the PHY chip at a fixed frequency f, and judging the connection state of the current link by using a slip judgment mode;
step 3, if the connection state of the current link is disconnected, turning to step 2; if the connection state of the current link is access, checking the parameter values of all working registers of the PHY chip in order to avoid abnormal working of the PHY chip under the interference of an external electromagnetic environment;
step 4, if the connection state of the current link is access and the reset flag of the PHY chip is 1, it indicates that the PHY chip has just recently performed a reset operation, and needs to renegotiate the ethernet working mode (including a communication rate of 10M or 100M, and a communication mode of half-duplex or full-duplex); otherwise, go to step 2.
Preferably, the configuring of the parameters of the MAC controller of the concentrator main control chip in step 1 includes the following steps:
1.1, performing function configuration on all pins for communication between the main control chip and the PHY chip, namely configuring GPIO pins of the main control chip;
1.2, configuring the working mode between the MAC controller interface and the PHY chip interface of the main control chip, wherein the working mode mainly comprises a negotiation mode, a media interface form and a communication inspection mode;
and 1.3, configuring each working register of the PHY chip, wherein the working registers comprise the number of registers, the type of the registers and configuration parameters of the registers. According to the type of the selected PHY chip, the number of registers to be configured, the type of the registers, and the configuration parameters of the registers may be slightly different.
Preferably, the step 2 of judging the connection state of the current link by using a form of slip judgment includes the following steps:
2.1, judging whether the value of the register is valid, if not, directly quitting and waiting for the next polling period to execute the step 2 again, and if so, turning to the next step; the effective condition is that the value of the register is in a reasonable range, and the reasonable range value has different defining modes according to different manufacturers and models of the PHY chip;
2.2, judging whether the connection state of the current link is switched on or off according to the register value obtained in the step 2.1;
and 2.3, eliminating the interference signals by using a slip judgment mode. Since the external complex electromagnetic field environment may affect the normal operation of the PHY chip, the connection state determined in step 2.2 may be an interference signal, and if the connection state is directly used, a risk of connection misjudgment may be generated, so as to avoid adverse effects of the misjudgment on the application layer code, a method for determining a slip is designed herein, and the accuracy and stability of link determination are increased under the condition that the detection efficiency is properly reduced.
Preferably, the rejecting interference signals in the form of using slip estimation in step 2.3 includes the following steps:
2.3.1, creating a slip array Arry [ N ] containing N elements, defining that 0 represents link disconnection, 1 represents link access, the value range of [ N ] is more than 0 and less than 30, and the larger the value of [ N ] is, the higher the judgment accuracy is but the lower the efficiency is;
2.3.2, if the link connection state judged in the step 2.2 is access, sliding 1 into a slip array Arry [ N ], otherwise sliding 0 into the slip array Arry [ N ];
2.3.3, judging whether the number of elements in the slip array Arry [ N ] reaches [ N ], if not, directly quitting and waiting for the next polling period to execute the step 2 again, and if so, turning to the step 2.3.4;
2.3.4, judging whether all the element values in the current slip array Arry [ N ] are 0 or 1, if so, judging that the current link enters a stable state, and determining that the state of the current link is switched on or off according to the data value of 0 or 1; if not, judging that the current link is in the transient process and the connection state judgment result of the current link is invalid, and turning to the step 2.
Preferably, the fixed frequency f in step 2 has a value range of: 0Hz < f < -100 Hz.
Preferably, the checking the parameter values of the operating registers of the PHY chip in step 3 includes the following steps:
3.1, reading the parameter values of each working register, and comparing the read parameter values with the initial written values;
3.2, if the read parameter value is inconsistent with the initial write value, judging that the PHY chip is abnormal, resetting the PHY chip, then reconfiguring each working register of the PHY chip, wherein the configuration parameters comprise the number of registers, the type of the registers and the configuration parameters of the registers, setting a reset mark of the PHY chip to be 1, and turning to the step 4;
if the read parameter value is consistent with the initial written value, go to step 4 directly.
Preferably, the renegotiation of the ethernet working mode in step 4 includes the following steps:
4.1, utilizing the Ethernet working mode auto-negotiation function of the PHY chip to enable the PHY chip to start to automatically negotiate the working modes of the PHY chip and the Ethernet interface of the far end;
4.2, continuously inquiring a register related to the completion of auto-negotiation in the PHY chip within the time T, judging whether the negotiation is completed, if the negotiation is not completed, turning to the step 4.3, and if the negotiation is completed, turning to the step 4.4;
4.3, in order to prevent the link from being suddenly disconnected in the process of carrying out automatic negotiation on the PHY chip, and causing invalid negotiation waiting, judging the connection state of the current link again by using a slip judgment mode, and if the connection state is the disconnection state, directly quitting the negotiation, and turning to the step 2;
if the access state is the access state, judging whether the time waiting for the completion of the negotiation currently exceeds the specified time, if the time exceeds the maximum waiting time, directly quitting the negotiation, and turning to the step 2; if the maximum waiting time is not exceeded, turning to step 4.2 to continue waiting for the negotiation to be completed;
4.4, after the renegotiation is completed, obtaining a negotiation result of the PHY chip, including: and configuring the negotiation result value into the MAC controller of the main control chip in a communication rate and a half-duplex/full-duplex mode, and restarting the MAC controller to complete the negotiation configuration.
Preferably, the value range of the time T in step 4.2 is: t is not less than 0 second and less than 120 seconds.
The invention has the beneficial effects that:
1. the connection state of the current link is judged by using a slip judgment mode, so that the risk of misjudgment caused by obtaining a single point judgment is avoided, and the judgment accuracy is improved.
2. Under the link access state, the PHY chip configuration register parameter value is periodically checked, the condition that the PHY chip is interfered by the outside, the data of the internal register is disordered and the main control chip is not known is avoided, the real-time control of the main control chip on the work condition of the PHY chip is ensured, and the response speed of the main control chip when the PHY chip works abnormally is improved.
3. When the PHY chip is reset, the reliability of communication is ensured by adding the mode of renegotiation of the Ethernet working mode.
4. In the process of renegotiation of the PHY chip, by increasing the judgment of the link connection state, once the current connection is judged to be in a disconnected state, the negotiation process is directly quitted, and the negotiation is carried out again after the link is reconnected, so that the working efficiency of the main control chip is improved.
Drawings
FIG. 1 is a logic flow diagram of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a logic flow diagram of the present invention, and a method for improving the stability of a concentrator ethernet PHY chip includes the following steps:
step 1, when a concentrator initially runs, firstly configuring parameters of an MAC (media access control) controller of a concentrator main control chip; the method comprises the following specific steps:
1.1, performing function configuration on all pins for communication between the main control chip and the PHY chip;
1.2, configuring the working mode between the MAC controller interface and the PHY chip interface of the main control chip, wherein the working mode mainly comprises a negotiation mode, a media interface form and a communication inspection mode;
and 1.3, configuring each working register of the PHY chip, wherein the working registers comprise the number of registers, the type of the registers and configuration parameters of the registers.
Step 2, setting a periodic polling function, inquiring the value of a connection state register of the PHY chip by using a fixed frequency f, and judging the connection state of the current link by using a slip judgment mode, wherein the value range of f is as follows: 0Hz < f < -100 Hz; the method comprises the following specific steps:
2.1, judging whether the value of the register is valid, if not, directly quitting and waiting for the next polling period to execute the step 2 again, and if so, turning to the next step;
2.2, judging whether the connection state of the current link is switched on or off according to the register value obtained in the step 2.1;
2.3, eliminating the interference signals by using a slip judgment form, and specifically comprising the following steps:
2.3.1, creating a slip array Arry [ N ] containing N elements, defining that 0 represents link disconnection, 1 represents link access, and the value range of [ N ] is more than 0 and less than 30;
2.3.2, if the link connection state judged in the step 2.2 is access, sliding 1 into a slip array Arry [ N ], otherwise sliding 0 into the slip array Arry [ N ];
2.3.3, judging whether the number of elements in the slip array Arry [ N ] reaches [ N ], if not, directly quitting and waiting for the next polling period to execute the step 2 again, and if so, turning to the step 2.3.4;
2.3.4, judging whether all the element values in the current slip array Arry [ N ] are 0 or 1, if so, judging that the current link enters a stable state, and determining that the state of the current link is switched on or off according to the data value of 0 or 1; if not, judging that the current link is in the transient process and the connection state judgment result of the current link is invalid, and turning to the step 2.
Step 3, if the connection state of the current link is disconnected, turning to step 2; if the connection state of the current link is access, checking the parameter values of all working registers of the PHY chip; the method comprises the following specific steps:
3.1, reading the parameter values of each working register, and comparing the read parameter values with the initial written values;
3.2, if the read parameter value is inconsistent with the initial written value, resetting the PHY chip, then reconfiguring each working register of the PHY chip, including the number of registers, the type of the registers and the configuration parameters of the registers, setting a reset mark of the PHY chip to be 1, and turning to the step 4;
if the read parameter value is consistent with the initial written value, go to step 4 directly.
Step 4, if the connection state of the current link is access and the PHY chip reset mark is 1, renegotiating the Ethernet working mode; otherwise, turning to the step 2; the method comprises the following specific steps:
4.1, utilizing the Ethernet working mode auto-negotiation function of the PHY chip to enable the PHY chip to start to automatically negotiate the working modes of the PHY chip and the Ethernet interface of the far end;
4.2, continuously inquiring a register related to the completion of auto-negotiation in the PHY chip within the time T, judging whether the negotiation is completed, if the negotiation is not completed, turning to the step 4.3, and if the negotiation is completed, turning to the step 4.4; the value range of T is as follows: t is more than or equal to 0 second and less than 120 seconds;
4.3, judging the connection state of the current link by using a slip judgment mode again, and if the current link is in a disconnection state, directly quitting the negotiation and turning to the step 2;
if the access state is the access state, judging whether the time waiting for the completion of the negotiation currently exceeds the specified time, if the time exceeds the maximum waiting time, directly quitting the negotiation, and turning to the step 2; if the maximum waiting time is not exceeded, turning to step 4.2 to continue waiting for the negotiation to be completed;
4.4, after the renegotiation is completed, obtaining a negotiation result of the PHY chip, including: and configuring the negotiation result value into the MAC controller of the main control chip in a communication rate and a half-duplex/full-duplex mode, and restarting the MAC controller to complete the negotiation configuration.
Claims (6)
1. A method for improving the stability of a concentrator Ethernet PHY chip is characterized by comprising the following steps:
step 1, configuring parameters of an MAC controller of a concentrator main control chip;
step 2, setting a periodic polling function, inquiring the value of a connection state register of the PHY chip at a fixed frequency f, and judging the connection state of the current link by using a slip judgment mode; the method specifically comprises the following steps:
2.1, judging whether the value of the register is valid, if not, directly quitting and waiting for the next polling period to execute the step 2 again, and if so, turning to the next step;
2.2, judging whether the connection state of the current link is switched on or off according to the register value obtained in the step 2.1;
2.3, eliminating the interference signals by using a slip judgment form;
the elimination of the interference signals by using the form of slip judgment in the step 2.3 comprises the following steps:
2.3.1, creating a slip array Arry [ N ] containing N elements, defining that 0 represents link disconnection, 1 represents link access, and the value range of [ N ] is more than 0 and less than 30;
2.3.2, if the link connection state judged in the step 2.2 is access, sliding 1 into a slip array Arry [ N ], otherwise sliding 0 into the slip array Arry [ N ];
2.3.3, judging whether the number of elements in the slip array Arry [ N ] reaches [ N ], if not, directly quitting and waiting for the next polling period to execute the step 2 again, and if so, turning to the step 2.3.4;
2.3.4, judging whether all the element values in the current slip array Arry [ N ] are 0 or 1, if so, judging that the current link enters a stable state, and determining that the state of the current link is switched on or off according to the data value of 0 or 1; if not, judging that the current link is in the transient process and the connection state judgment result of the current link is invalid, then turning to the step 2;
step 3, if the connection state of the current link is disconnected, turning to step 2; if the connection state of the current link is access, checking the parameter values of all working registers of the PHY chip;
step 4, if the connection state of the current link is access and the PHY chip reset mark is 1, renegotiating the Ethernet working mode; otherwise, go to step 2.
2. The method according to claim 1, wherein the configuring the parameters of the MAC controller of the concentrator main control chip in step 1 comprises the following steps:
1.1, performing function configuration on all pins for communication between the main control chip and the PHY chip;
1.2, configuring the working mode between the MAC controller interface and the PHY chip interface of the main control chip, including a negotiation mode, a media interface form and a communication inspection mode;
and 1.3, configuring each working register of the PHY chip, wherein the working registers comprise the number of registers, the type of the registers and configuration parameters of the registers.
3. The method according to claim 1, wherein the fixed frequency f in step 2 has a value range of: 0Hz < f < -100 Hz.
4. A method according to any of claims 1-3, wherein said checking of the parameter values of the operating registers of the PHY chip in step 3 comprises the following steps:
3.1, reading the parameter values of each working register, and comparing the read parameter values with the initial written values;
3.2, if the read parameter value is inconsistent with the initial write value, judging that the PHY chip is abnormal, resetting the PHY chip, then reconfiguring each working register of the PHY chip, wherein the configuration parameters comprise the number of registers, the type of the registers and the configuration parameters of the registers, setting a reset mark of the PHY chip to be 1, and turning to the step 4;
if the read parameter value is consistent with the initial written value, go to step 4 directly.
5. A method according to any of claims 1-3, wherein the renegotiation of ethernet operation mode in step 4 comprises the following steps:
4.1, utilizing the Ethernet working mode auto-negotiation function of the PHY chip to enable the PHY chip to start to automatically negotiate the working modes of the PHY chip and the Ethernet interface of the far end;
4.2, continuously inquiring a register related to the completion of auto-negotiation in the PHY chip within the time T, judging whether the negotiation is completed, if the negotiation is not completed, turning to the step 4.3, and if the negotiation is completed, turning to the step 4.4;
4.3, judging the connection state of the current link by using a slip judgment mode, and if the current link is in a disconnection state, directly quitting the negotiation and turning to the step 2;
if the access state is the access state, judging whether the time waiting for the completion of the negotiation currently exceeds the specified time, if the time exceeds the maximum waiting time, directly quitting the negotiation, and turning to the step 2; if the maximum waiting time is not exceeded, turning to step 4.2 to continue waiting for the negotiation to be completed;
4.4, after the renegotiation is completed, obtaining a negotiation result of the PHY chip, including: and configuring the negotiation result value into the MAC controller of the main control chip in a communication rate and a half-duplex/full-duplex mode, and restarting the MAC controller to complete the negotiation configuration.
6. The method according to claim 5, wherein the time T in step 4.2 has a value range of: t is not less than 0 second and less than 120 seconds.
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| CN113504773A (en) * | 2021-07-29 | 2021-10-15 | 安徽江淮汽车集团股份有限公司 | Ethernet test method and Ethernet test system of vehicle-mounted controller |
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| CN101060442A (en) * | 2006-04-22 | 2007-10-24 | 华为技术有限公司 | A linkage status detection device and method |
| CN101425952A (en) * | 2008-12-09 | 2009-05-06 | 中兴通讯股份有限公司 | Method and apparatus for ensuring Ether ring network reliable operation |
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