CN115437453A - Biasing circuit and self-biased OSC circuit - Google Patents
Biasing circuit and self-biased OSC circuit Download PDFInfo
- Publication number
- CN115437453A CN115437453A CN202110619514.5A CN202110619514A CN115437453A CN 115437453 A CN115437453 A CN 115437453A CN 202110619514 A CN202110619514 A CN 202110619514A CN 115437453 A CN115437453 A CN 115437453A
- Authority
- CN
- China
- Prior art keywords
- module
- circuit
- switch
- osc
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 15
- 239000004973 liquid crystal related substance Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Abstract
The present application provides a bias circuit and a self-biased OSC circuit. The bias circuit is used for providing bias current for the OSC circuit; the impedance module and the first switch module of the biasing circuit are connected in series between the power supply end of the OSC circuit and the biasing current input end of the OSC circuit, and when the OSC circuit is started, namely the first switch module is conducted, the power supply of the OSC circuit can be used for providing the biasing current for the OSC circuit through the impedance module, so that the OSC circuit can realize self-biasing, and the biasing circuit can reduce the power consumption caused by external biasing.
Description
Technical Field
The present invention relates to the field of power electronics, and more particularly, to a bias circuit and a self-biased OSC circuit.
Background
With the advent of the intelligent era, handheld and wearable devices are increasingly being used, and as far as the present situation is concerned, the difficulty in designing the wearable devices is controlling power consumption. At present, two ideas for realizing low power consumption exist, one is to reduce the power consumption of each module in the device; another is to intermittently turn off or on unnecessary blocks in the device, for example, by turning off non-essential blocks during intermittent turn off by an externally biased OSC (Oscillator) circuit shown in fig. 1, and to allow only a portion of the critical blocks to operate, thereby reducing the average power consumption.
Referring to fig. 1, an external circuit provides a bias current IBIAS to the external bias OSC circuit; the ring oscillator is composed of an odd number of inverters, and the frequency of the ring oscillator is determined by the voltage of the connection point B of the first switch tube and the output capacitor, the voltage of the connection point B is equal to the voltage of the connection point a of the second switch tube and the adjusting impedance, and the voltage of the connection point a is determined by the adjusting impedance Rq, so that the output frequency of the externally biased OSC circuit, namely the frequency of intermittent turning off or on, can be adjusted by adjusting the impedance value of the adjusting impedance Rq.
However, the externally biased OSC circuit requires an external circuit to provide a bias current for normal start-up and operation, i.e., the external circuit must be kept in operation all the time, which results in much extra power consumption.
Disclosure of Invention
In view of the above, the present invention provides a bias circuit and a self-biased OSC circuit, which can reduce power consumption due to external biasing.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
one aspect of the present application provides a bias circuit applied to an oscillator OSC circuit to provide a bias current, the bias circuit including: an impedance module and a first switch module; wherein:
the impedance module and the first switch module are connected in series between a power supply terminal of the OSC circuit and a bias current input terminal of the OSC circuit;
the control end of the first switch module receives the control signal output by the OSC circuit.
Optionally, the OSC circuit includes an enable state pin, and the control end of the first switch module is connected to the enable state pin of the OSC circuit.
Optionally, a first terminal of the impedance module is connected to the power supply terminal of the OSC circuit, a second terminal of the impedance module is connected to the input terminal of the first switch module, and an output terminal of the first switch module is connected to the bias current input terminal of the OSC circuit; alternatively, the first and second electrodes may be,
an input terminal of the first switch module is connected to a power supply terminal of the OSC circuit, an output terminal of the first switch module is connected to a first terminal of the impedance module, and a second terminal of the impedance module is connected to a bias current input terminal of the OSC circuit.
Optionally, the method further includes: the switch comprises a switch switching module and a current mirror module; wherein:
the current mirror module is connected with a third switch module in the switch switching module in series to form a first branch circuit, and the impedance module is connected with a second switch module in the switch switching module in series to form a second branch circuit; the first branch circuit and the second branch circuit are connected in parallel, and the branch circuit and the first switch module which are connected in parallel are connected in series between a power supply end and a bias current input end of the OSC circuit;
the current mirror module is used for proportionally mirroring the current value of a power supply branch circuit of a ring oscillator in the OSC circuit;
the switch switching module is configured to switch the impedance module to provide the bias current for the OSC circuit after the impedance module provides the bias current for the OSC circuit for a preset time: providing, by the current mirror module, a bias current for the OSC circuit.
Optionally, an input end of the current mirror module is connected to a first end of the impedance module, and a connection point is used as a connection point at which the first branch and the second branch are connected in parallel; the first input end of the switch switching module is connected with the second end of the impedance module; the second input end of the switch switching module is connected with the output end of the current mirror module; the output end of the switch switching module is used as the other connecting point of the first branch circuit and the second branch circuit which are connected in parallel; alternatively, the first and second electrodes may be,
the input end of the switch switching module is used as a connection point of the first branch circuit and the second branch circuit which are connected in parallel; the first output end of the switch switching module is connected with the first end of the impedance module; the second output end of the switch switching module is connected with the input end of the current mirror module; and the second end of the impedance module is connected with the output end of the current mirror module, and a connection point is used as the other connection point of the parallel connection of the first branch and the second branch.
Optionally, the switch switching module includes: the second switch module, the third switch module, a counter and an inverter; wherein:
the control end of the third switch module is connected with the output end of the phase inverter, the input end of the phase inverter and the control end of the second switch module are both connected with the output end of the counter, and the input end of the counter is used as the control end of the switch switching module and receives an oscillation signal of a ring oscillator in the OSC circuit;
the second switch module and the impedance module are connected in series to form the second branch circuit; the third switch module and the current mirror module are connected in series to form the first branch circuit.
Optionally, the enable state pin of the counter is connected to the enable state pin of the OSC circuit;
a feedback pin of the counter receives a signal output by an output end of the counter;
the priority of the enable state signal received by the enable state pin of the counter is greater than that of the signal output by the output end of the counter.
Optionally, the preset time is a time when the oscillation period of the oscillation signal is counted to a preset value by the counter.
Optionally, the current mirror module includes: a switching tube; wherein:
and the switching tube and an output switching tube in the ring oscillator power supply branch circuit form a current mirror.
Optionally, the number ratio of the switch tubes to the output switch tubes is a preset multiple.
Optionally, the impedance module includes: at least one impedance; wherein:
when the number of the impedances is more than 1, the impedances are connected in series and/or in parallel.
Optionally, each switch module is a reverse conducting transistor or a mechanical switch.
Another aspect of the application provides a self-biased OSC circuit, comprising: an OSC circuit and a bias circuit as described in any one of the previous aspects of the present application.
As can be seen from the above technical solutions, the present invention provides a bias circuit for providing a bias current to an OSC circuit; the impedance module and the first switch module of the biasing circuit are connected in series between the power supply end of the OSC circuit and the biasing current input end of the OSC circuit, and when the OSC circuit is started, namely the first switch module is conducted, the power supply of the OSC circuit can be used for providing the biasing current for the OSC circuit through the impedance module, so that the OSC circuit can realize self-biasing, and the biasing circuit can reduce the power consumption caused by external biasing.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of an externally biased OSC circuit in the prior art;
fig. 2-6 are schematic diagrams of five structures of a self-biased OSC circuit, respectively.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to reduce power consumption caused by external bias, embodiments of the present application provide a bias circuit, which can be applied to an OSC circuit 01, and a specific structure of the bias circuit is shown in fig. 2, and includes: an impedance module 10 and a first switch module 20.
The impedance module 10 and the first switch module 20 are connected in series between the power supply terminal VCC of the OSC circuit 01 and the bias current input terminal O of the OSC circuit 01, and the control terminal of the first switch module 20 receives the control level output by the OSC circuit 01, for example, the control terminal of the first switch module 20 is connected to the enable status pin EN1 of the OSC circuit 01 (in the figure, only EN1 represents the enable status pin EN1 of the OSC circuit 01, but the specific structure thereof is not shown).
When the enable state pin EN1 of the OSC circuit 01 receives the first level signal, the OSC circuit 01 is turned on, and the first switch module 20 is turned on, so that a current flows through the impedance module 10 and is input to the OSC circuit 01 from the bias current input terminal O of the OSC circuit 01 as a bias current of the OSC circuit 01; when the enable state pin EN1 of the OSC circuit 01 receives the second level signal, the OSC circuit 01 is turned off, and the first switch module 20 is turned off, so that no current flows through the impedance module 10, i.e., the bias circuit is also turned off, and stops working.
When a current is input to the OSC circuit 01 through the bias current input terminal O of the OSC circuit 01 as a bias current of the OSC circuit 01, the potential of the bias current input terminal O of the OSC circuit 01 is approximately equal to the low level, and therefore, the bias current IBIAS = (VR-Vo)/Ro of the OSC circuit 01.
Wherein VR is the potential of the power supply terminal VCC of the OSC circuit 01; vo is a voltage value below the impedance module 10, such as a sum of a potential difference across the first switch module 20 and a potential difference across an input switch tube N in the OSC circuit; ro is the equivalent impedance value of the impedance module 10.
It should be noted that the first level signal is a start signal issued by the system controller when the system where the OSC circuit 01 is located is started; the second level signal is a shutdown signal issued by the system controller when the system where the OSC circuit 01 is located is shutdown; in practical applications, the first level signal and the second level signal may be various level signals, such as a high level or a low level, but embodiments that can be distinguished between the first level signal and the second level signal are within the protection scope of the present application, and are not specifically limited herein and may be selected according to specific situations; preferably, the first level signal is a high level signal, and the second level signal is a low level signal.
As can be seen from the above description, the bias circuit provided in the present invention can provide the bias current IBIAS to the OSC circuit 01 through the impedance module 10 by using the power supply of the OSC circuit 01 after the OSC circuit 01 is turned on, that is, after the first switch module 20 is turned on, that is, the OSC circuit 01 can realize self-bias, so that the bias circuit can reduce the power consumption caused by external bias.
In practical applications, there are different embodiments of the connection relationship between the impedance module 10 and the first switch module 20 and the connection relationship between the two and the OSC circuit 01, and one embodiment is as shown in fig. 2, specifically: a first terminal of the impedance module 10 is connected to the power supply terminal VCC of the OSC circuit 01, a second terminal of the impedance module 10 is connected to the input terminal of the first switch module 20, and the output terminal of the first switch module 20 is connected to the bias current input terminal O of the OSC circuit 01; another embodiment is shown in fig. 3, which specifically includes: an input end of the first switch module 20 is connected to a power supply end VCC of the OSC circuit 01, an output end of the first switch module 20 is connected to a first end of the impedance module 10, and a second end of the impedance module 10 is connected to a bias current input end O of the OSC circuit 01; the two embodiments can be selected according to specific situations, and are not specifically limited herein and are within the scope of the present application.
Optionally, the impedance module 10 includes at least one resistor R, and when the number of the resistors R is greater than 2, the resistors R are connected in series and/or in parallel, which is not specifically limited herein and may be determined according to specific situations, and all of the resistors R are within the protection scope of the present application.
Optionally, the first switch module 20 may be: the reverse conducting Transistor, for example, a MOS Transistor, a JEET (Junction Field-Effect Transistor), and an IGBT may also be: mechanical switches, such as relays, are not limited specifically herein, and may be within the scope of the present application as the case may be.
When the first switch module 20 is a MOS transistor, the potential difference between the input terminal and the output terminal of the first switch module 20 is the potential difference VTH between the drain and the source of the MOS transistor.
Although the bias circuit provided in the above embodiment may enable the OSC circuit 01 to realize self-bias, that is, reduce power consumption caused by external bias, since the bias current IBIAS provided by the bias circuit in the above embodiment for the OSC circuit 01 is related to the power supply of the OSC circuit 01, the bias current IBIAS of the OSC circuit 01 may frequently change, thereby affecting the power consumption of the OSC circuit 01.
Therefore, another embodiment of the present application provides another implementation of a bias circuit, a specific structure of which is shown in fig. 4, and on the basis of the bias circuit in the foregoing embodiment, the bias circuit further includes: a switch switching module 40 and a current mirror module 30.
The current mirror module 30 is connected in series with a third switch module in the switch switching module 40 to form a first branch, the impedance module 10 is connected in series with a second switch module in the switch switching module 40 to form a second branch, the first branch and the second branch are connected in parallel, and the parallel branches and the first switch module 20 are connected in series between the power supply terminal VCC and the bias current input terminal O of the OSC circuit 01.
After the OSC circuit 01 is started, the switch switching module 40 selects the impedance module 10 to provide the bias current IBIAS to the OSC circuit 01, that is, the second branch is turned on; after a preset time, the switch switching module 40 selects the current mirror module 30 to provide the bias current IBIAS for the OSC circuit 01; after a preset time, the first branch is conducted; that is, after a preset time, the switch switching module 40 switches the bias current IBIAS provided by the impedance module 10 to the OSC circuit 01 to: the OSC circuit 01 is provided with a bias current IBIAS by the current mirror module 30.
It should be noted that the preset time needs to be longer than the time required for the OSC circuit 01 to be in the steady state from the start-up, that is, after the preset time, the OSC circuit 01 is already in the steady state; in practical application, the specific selection of the preset time can be selected according to practical conditions, as long as the requirements are met, and the specific selection is not specifically limited herein and is within the protection scope of the present application.
In addition, the control terminal of the current mirror module 30 is connected to the control terminal of the ring oscillator power supply branch 02 in the OSC circuit 01; the input end of the current mirror module 30 is directly connected with the input end of the ring oscillator power supply branch 02, or the input end of the current mirror module 30 is indirectly connected with the input end of the ring oscillator power supply branch 02 through a corresponding switch module in the switch switching module 40; the current mirror module 30 is configured to mirror and output a current of the ring oscillator power supply branch 02 in the OSC circuit 01 according to a predetermined ratio.
It should be noted that the ring oscillator power supply branch 02 in the OSC circuit 01 includes the first output switch tube MX, the second output switch tube MY, the output capacitor C, and the output resistor Rc in fig. 4, when the first output switch tube MX and the second output switch tube MY are both PMOS transistors, as shown in fig. 4, the first output switch tube MX and the second output switch tube MY form a current mirror, that is, the gates of the first output switch tube MX and the second output switch tube MY are connected, and the sources of the first output switch tube MX and the second output switch tube MY are both connected to the power supply terminal VCC of the OSC circuit 01; the drain electrode of the first output switch tube MX is grounded through an output resistor Rc, and the drain electrode of the second output switch tube MY is grounded through an output capacitor C; therefore, the current of the ring oscillator power supply branch 02 in the OSC circuit 01 may be the current flowing through the first output switch tube MX or the current flowing through the second output switch tube MY, and is not particularly limited herein, and it is within the scope of the present application.
After the preset time, the OSC circuit 01 is in a stable state, the output of the operational amplifier in the OSC circuit 01 is a stable voltage, and the current of the ring oscillator power supply branch 02 in the OSC circuit 01 is directly related to the frequency, so that the current of the ring oscillator power supply branch 02 in the OSC current is relatively stable, and since M1, MX and MY are in a mirror relationship, the current in the current mirror module 30 is relatively stable, and the current mirror module 30 is selected to provide the bias current IBIAS for the OSC current, so that the OSC circuit 01 obtains the relatively stable bias current IBIAS, that is, the frequent switching of the bias current IBIAS can be reduced, and the influence on the power consumption of the OSC circuit 01 can be reduced.
Specifically, in the present embodiment, there are two embodiments of the connection relationship among the current mirror module 30, the impedance module 10, and the switch switching module 40, one embodiment is as shown in fig. 4, specifically:
the input end of the current mirror module 30 is connected to the first end of the impedance module 10, and the connection point is used as a connection point where the first branch and the second branch are connected in parallel; a first input end of the switch switching module 40 is connected with a second end of the impedance module 10, and a second input end of the switch switching module 40 is connected with an output end of the current mirror module 30; the output terminal of the switching module 40 serves as another connection point where the first branch and the second branch are connected in parallel.
Another embodiment is shown in fig. 5, which specifically includes:
the input end of the switch switching module 40 is used as a connection point where the first branch and the second branch are connected in parallel; a first output end of the switch switching module 40 is connected with a first end of the impedance module 10, and a second output end of the switch switching module 40 is connected with an input end of the current mirror module 30; the second terminal of the impedance module 10 is connected to the output terminal of the circuit mirror module, and the connection point serves as another connection point at which the first branch and the second branch are connected in parallel.
The two embodiments of the connection relationship among the current mirror module 30, the impedance module 10, and the switch switching module 40 may be selected according to specific situations, and are not limited herein, and are all within the protection scope of the present application.
It should be noted that in this embodiment, the connection relationship between the branch formed by the parallel connection of the first branch and the second branch and the first switch module 20 is the same as the connection relationship between the impedance module 10 and the first switch module 20 in the above embodiment, and can be derived by referring to the description of the connection relationship between the impedance module 10 and the first switch module 20 in the above embodiment, which is not repeated herein.
In the above embodiment, the switch switching module 40 may switch to a power supply module, such as the current mirror module 30 in the above embodiment, for providing the bias current IBIAS to the OSC circuit 01 after a preset time, so as to reduce the influence on the power consumption of the OSC circuit 01. To achieve the above object, another embodiment of the present application provides an implementation manner of an internal structure of the switch switching module 40, a specific structure of which is shown in fig. 6 (which is illustrated on the basis of fig. 4) and includes: a second switching module 41, a third switching module 42, a counter 43, and an inverter INV.
The second switch module 41 is connected in series with the impedance module 10 as a second branch; the third switching module 42 is connected in series with the current mirror module 30 as a first branch.
The control end of the third switch module 42 is connected to the control end of the second switch module 41 through an inverter INV, and the connection point is connected to the output end of the counter 43, specifically, the control end of the third switch module 42 is connected to the input end of the inverter INV first, then the output end of the inverter INV is connected to the control end of the second switch module 41, and the connection point is connected to the output end of the counter 43.
The input terminal of the counter 43, which is used as the control terminal of the switch switching module 40, is connected to the output terminal of the OSC circuit 01, and receives the oscillation signal of the ring oscillator 02 in the OSC circuit 01, and performs timing by using the oscillation signal, i.e., counts the oscillation period of the oscillation signal, so that the preset time is the time for counting the oscillation period of the oscillation signal to a preset value, i.e., the preset time is equal to the product of the oscillation period of the oscillation signal and the preset value.
Optionally, the preset value may be 4, or may be other values, which are not specifically limited herein, and all positive integers are within the protection scope of the present application.
For example, if the oscillation period is 0.5s and the preset value is 4, the preset time is 2s, that is, after the OSC circuit 01 is started for 5s, the switch switching module 40 switches the impedance module 10 to provide the bias current IBIAS for the OSC circuit 01 to: the OSC circuit 01 is provided with a bias current IBIAS by the current mirror module 30.
Before the preset time, the counter 43 outputs a third level signal, after the preset time, the signal output by the counter 43 is inverted from the third level signal to a fourth level signal, the control end of the second switch module 41 receives the fourth level signal, and the inverter INV inverts the fourth level signal to the third level signal and inputs the third level signal to the third switch module 42, so that the second switch module 41 is turned off, the third switch module 42 is turned on, that is, the first branch is turned on, and the current mirror module 30 provides the bias current IBIAS for the OSC circuit 01.
It should be noted that, in practical applications, the third level signal and the fourth level signal may be various level signals, such as a high level or a low level, but embodiments that can distinguish between the third level signal and the fourth level signal are within the protection scope of the present application, and are not specifically limited herein, and the types of the second switch module 41 and the third switch module 42 may be selected according to the application; preferably, the third level signal is a low level signal, and the fourth level signal is a high level signal.
The above is only a preferred embodiment of the internal structure of the switch switching module 40, and in practical applications, including but not limited to the above embodiments, the embodiments may be determined according to specific situations, and are not specifically limited herein, and are within the scope of the present application.
It should be noted that, in this embodiment, the connection between the control terminal of the switch switching module 40 and the output terminal of the OSC circuit 01 is only a preferred connection manner of the control terminal of the switch switching module 40, and in practical applications, including but not limited to the above-mentioned embodiments, it is determined according to specific situations, and is not limited herein, and is within the protection scope of the present application.
In practical applications, as shown in fig. 6, a feedback pin F is further disposed on the counter 43, and the feedback pin F of the counter 43 receives a signal output by its own output terminal, for example, a fourth level signal; before the preset time, the feedback pin F of the counter 43 receives the third level signal and still maintains itself in the working state, and after the preset time, the feedback pin F of the counter 43 receives the fourth level signal, and then closes itself, and stops working, so as to maintain the output of the fourth level signal from its output terminal.
In practical applications, as shown in fig. 6, the counter 43 is further provided with an enable state pin EN2, and the feedback pin EN2 of the counter 43 is connected to the enable state pin EN1 of the OSC circuit 01 to receive an enable state signal; when the enable state signal is the second level signal, that is, when the OSC circuit 01 is turned off, the counter 43 is reset.
It should be noted that the priority of the enable state signal received by the feedback pin EN2 of the counter 43 is higher than that of the signal output by the output terminal of the counter 43, for example, when the feedback pin F of the counter 43 receives the fourth level signal, the counter 43 is turned off, and when the enable state signal received by the feedback pin EN2 of the counter 43 becomes the second level signal at this time, the counter 43 is immediately reset, and the signal output by the output terminal thereof is also switched to the third level signal.
Alternatively, like the first switch module 20, the second switch module 41 or the third switch module 42 may be: the reverse conducting Transistor, for example, a MOS Transistor, a JEET (Junction Field-Effect Transistor), and an IGBT may also be: mechanical switches, such as relays, are not limited herein, and may be within the scope of the present application as the case may be.
The present embodiment further provides a specific implementation of the current mirror module 30, and the specific structure thereof is as shown in fig. 6, and includes: and a switching tube M.
The source electrode and the drain electrode of the switching tube M are respectively used as the input end and the output end of the current mirror image module; the gate of the switching tube M is connected to the gates of the output switching tubes MX and MY in the ring oscillator power supply branch 02 of the OSC circuit 01 to form a current mirror, and mirror-image output is performed on the current of the ring oscillator power supply branch 02 of the OSC circuit 01 at a preset ratio.
Optionally, the switch tube M may be an NMOS transistor or a PMOS transistor, which is not specifically limited herein, and it is within the protection scope of the present application according to specific situations, and it is not to be noticed that the switch tube M needs to be ensured to be the same as the output switch tubes MX and MY in the ring oscillator power supply branch 02 in the OSC circuit 01.
It should be noted that, when the current of the ring oscillator power supply branch 02 in the OSC circuit 01 is the current flowing through the first output switch tube MX, the preset ratio is a first preset ratio, and the first preset ratio is equal to the number ratio of the switch tube M to the first output switch tube MX in the ring oscillator power supply branch 02 in the OSC circuit 01; when the current of the ring oscillator power supply branch 02 in the OSC circuit 01 is the current flowing through the second output switching tube MY, the preset ratio is a second preset ratio, and the second preset ratio is equal to the number ratio of the switching tube M to the second output switching tube MY in the ring oscillator power supply branch 02 in the OSC circuit 01; the first preset proportion and the second preset proportion can be set according to actual conditions, and are not specifically limited herein and are within the protection scope of the present application.
Another embodiment of the present application provides a self-biased OSC circuit, and its specific structure can be seen in fig. 2 to 6, which includes the OSC circuit 01 and the bias circuit in the above embodiments.
The specific structure of the bias circuit has been described in detail in the above embodiments, which can be referred to the above embodiments, and is not described herein,
in this application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (12)
1. A bias circuit for use in an oscillator, OSC, circuit to provide a bias current, the bias circuit comprising: an impedance module and a first switch module; wherein:
the impedance module and the first switch module are connected in series between a power supply terminal of the OSC circuit and a bias current input terminal of the OSC circuit;
the control end of the first switch module receives the control signal output by the OSC circuit.
2. The bias circuit of claim 1, wherein the OSC circuit comprises an enable status pin, and wherein the control terminal of the first switch module is connected to the enable status pin of the OSC circuit.
3. The bias circuit of claim 1, wherein a first terminal of the impedance module is connected to a power supply terminal of the OSC circuit, a second terminal of the impedance module is connected to an input terminal of the first switch module, and an output terminal of the first switch module is connected to a bias current input terminal of the OSC circuit; alternatively, the first and second liquid crystal display panels may be,
an input terminal of the first switch module is connected to a power supply terminal of the OSC circuit, an output terminal of the first switch module is connected to a first terminal of the impedance module, and a second terminal of the impedance module is connected to a bias current input terminal of the OSC circuit.
4. The bias circuit of claim 2, further comprising: the switch comprises a switch switching module and a current mirror module; wherein:
the current mirror module is connected with a third switch module in the switch switching module in series to form a first branch circuit, and the impedance module is connected with a second switch module in the switch switching module in series to form a second branch circuit; the first branch circuit and the second branch circuit are connected in parallel, and the branch circuit and the first switch module after the parallel connection are connected in series between a power supply end and a bias current input end of the OSC circuit;
the current mirror module is used for proportionally mirroring the current value of a power supply branch circuit of a ring oscillator in the OSC circuit;
the switch switching module is configured to switch the impedance module to provide the bias current for the OSC circuit after the impedance module provides the bias current for the OSC circuit for a preset time: providing, by the current mirror module, a bias current for the OSC circuit.
5. The bias circuit according to claim 4, wherein the input terminal of the current mirror module is connected to the first terminal of the impedance module, and a connection point is used as a connection point for connecting the first branch and the second branch in parallel; the first input end of the switch switching module is connected with the second end of the impedance module; the second input end of the switch switching module is connected with the output end of the current mirror module; the output end of the switch switching module is used as the other connecting point of the first branch circuit and the second branch circuit which are connected in parallel; alternatively, the first and second electrodes may be,
the input end of the switch switching module is used as a connection point of the first branch circuit and the second branch circuit which are connected in parallel; the first output end of the switch switching module is connected with the first end of the impedance module; the second output end of the switch switching module is connected with the input end of the current mirror module; and the second end of the impedance module is connected with the output end of the current mirror module, and a connection point is used as the other connection point of the first branch circuit and the second branch circuit which are connected in parallel.
6. The bias circuit of claim 4, wherein the switching module comprises: the second switch module, the third switch module, a counter and an inverter; wherein:
the control end of the third switch module is connected with the output end of the phase inverter, the input end of the phase inverter and the control end of the second switch module are both connected with the output end of the counter, and the input end of the counter is used as the control end of the switch switching module and receives an oscillation signal of a ring oscillator in the OSC circuit;
the second switch module and the impedance module are connected in series to form the second branch circuit; the third switch module and the current mirror module are connected in series to form the first branch.
7. The bias circuit of claim 6, wherein the enable state pin of the counter is connected to an enable state pin of the OSC circuit;
a feedback pin of the counter receives a signal output by an output end of the counter;
the priority of the enable state signal received by the enable state pin of the counter is greater than that of the signal output by the output end of the counter.
8. The bias circuit of claim 7, wherein the predetermined time is a time when the counter counts an oscillation period of the oscillation signal to a predetermined value.
9. The bias circuit of claim 4, wherein the current mirror module comprises: a switching tube; wherein:
and the switching tube and an output switching tube in the ring oscillator power supply branch circuit form a current mirror.
10. The bias circuit of claim 9, wherein the number ratio of the switch tubes to the output switch tubes is a predetermined multiple.
11. The bias circuit according to any of claims 1-10, wherein the impedance module comprises: at least one impedance; wherein:
when the number of the impedances is more than 1, the impedances are connected in series and/or in parallel.
12. A self-biased OSC circuit, comprising: an OSC circuit and a biasing circuit as claimed in any one of claims 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110619514.5A CN115437453A (en) | 2021-06-03 | 2021-06-03 | Biasing circuit and self-biased OSC circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110619514.5A CN115437453A (en) | 2021-06-03 | 2021-06-03 | Biasing circuit and self-biased OSC circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115437453A true CN115437453A (en) | 2022-12-06 |
Family
ID=84271552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110619514.5A Pending CN115437453A (en) | 2021-06-03 | 2021-06-03 | Biasing circuit and self-biased OSC circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115437453A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127506A (en) * | 2007-09-29 | 2008-02-20 | 北京时代民芯科技有限公司 | A novel CMOS oscillator circuit |
| CN101409541A (en) * | 2008-11-18 | 2009-04-15 | 上海贝岭矽创微电子有限公司 | Annular oscillating circuit |
| CN101629973A (en) * | 2009-06-09 | 2010-01-20 | 中国人民解放军国防科学技术大学 | High-precision current sampling circuit without operational amplifier for low voltage power supply |
| CN101782634A (en) * | 2010-02-23 | 2010-07-21 | 南京大学 | On-chip all-in-one micro integrated magnetic sensor |
| CN101840241A (en) * | 2010-03-30 | 2010-09-22 | 北京中星微电子有限公司 | Differential current sampling circuit and linear voltage regulator |
| CN103248319A (en) * | 2012-04-25 | 2013-08-14 | 嘉兴联星微电子有限公司 | Low-power consumption oscillating circuit |
| US20150378386A1 (en) * | 2014-06-30 | 2015-12-31 | Chengdu Monolithic Power Systems Co., Ltd. | Trans-conductance regulation circuit, trans-conductance error amplifier and power converter |
| CN106100633A (en) * | 2016-08-11 | 2016-11-09 | 北京兆易创新科技股份有限公司 | A kind of crystal oscillator drive circuit |
| CN206698185U (en) * | 2016-02-25 | 2017-12-01 | 宗仁科技(平潭)有限公司 | A kind of oscillating circuit and oscillator |
| CN108809080A (en) * | 2017-04-28 | 2018-11-13 | 合肥格易集成电路有限公司 | A kind of biasing circuit, oscillator and charge pump |
| CN112615622A (en) * | 2020-12-26 | 2021-04-06 | 上海艾为电子技术股份有限公司 | Spread spectrum clock generator and electronic equipment |
-
2021
- 2021-06-03 CN CN202110619514.5A patent/CN115437453A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127506A (en) * | 2007-09-29 | 2008-02-20 | 北京时代民芯科技有限公司 | A novel CMOS oscillator circuit |
| CN101409541A (en) * | 2008-11-18 | 2009-04-15 | 上海贝岭矽创微电子有限公司 | Annular oscillating circuit |
| CN101629973A (en) * | 2009-06-09 | 2010-01-20 | 中国人民解放军国防科学技术大学 | High-precision current sampling circuit without operational amplifier for low voltage power supply |
| CN101782634A (en) * | 2010-02-23 | 2010-07-21 | 南京大学 | On-chip all-in-one micro integrated magnetic sensor |
| CN101840241A (en) * | 2010-03-30 | 2010-09-22 | 北京中星微电子有限公司 | Differential current sampling circuit and linear voltage regulator |
| CN103248319A (en) * | 2012-04-25 | 2013-08-14 | 嘉兴联星微电子有限公司 | Low-power consumption oscillating circuit |
| US20150378386A1 (en) * | 2014-06-30 | 2015-12-31 | Chengdu Monolithic Power Systems Co., Ltd. | Trans-conductance regulation circuit, trans-conductance error amplifier and power converter |
| CN206698185U (en) * | 2016-02-25 | 2017-12-01 | 宗仁科技(平潭)有限公司 | A kind of oscillating circuit and oscillator |
| CN106100633A (en) * | 2016-08-11 | 2016-11-09 | 北京兆易创新科技股份有限公司 | A kind of crystal oscillator drive circuit |
| CN108809080A (en) * | 2017-04-28 | 2018-11-13 | 合肥格易集成电路有限公司 | A kind of biasing circuit, oscillator and charge pump |
| CN112615622A (en) * | 2020-12-26 | 2021-04-06 | 上海艾为电子技术股份有限公司 | Spread spectrum clock generator and electronic equipment |
Non-Patent Citations (4)
| Title |
|---|
| SIEW-SEONG TAN等: "An Integrated Low-Noise Sensing Circuit With Efficient Bias Stabilization for CMOS MEMS Capacitive Accelerometers", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS》 * |
| 吴斯敏等: "一种嵌入Bicmos带隙电路的过温保护电路", 舰船电子工程, no. 04 * |
| 彭伟娣等: "一种低功耗CMOS晶振电路设计", 电子器件, no. 03 * |
| 高家豪等: "具有预偏置电压保护的软启动电路设计", 固体电子学研究与进展, no. 03 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3931588A (en) | Voltage controlled oscillator utilizing field effect transistors | |
| CN107681994B (en) | Oscillator circuit | |
| EP0735677A1 (en) | Oscillator circuit having oscillation frequency independent from the supply voltage value | |
| US5204612A (en) | Current source circuit | |
| CN104124921A (en) | Current mode comparator based low voltage low power consumption CMOS (Complementary Metal Oxide Semiconductors) relaxation oscillator and method | |
| JP4510054B2 (en) | Ultra low power RC oscillator | |
| JP5814542B2 (en) | Oscillator circuit | |
| EP0361529B1 (en) | Voltage controlled oscillator | |
| CN109672408B (en) | Low-power-consumption programmable crystal oscillator circuit capable of starting oscillation quickly | |
| US9154082B2 (en) | Input signal amplifier | |
| CN115437453A (en) | Biasing circuit and self-biased OSC circuit | |
| US6211744B1 (en) | Ring oscillator having an externally adjustable variable frequency | |
| CN110011644B (en) | Ring oscillator | |
| EP0779711A2 (en) | A timer circuit | |
| JP2007096410A (en) | Pulse signal generator and clock signal generator | |
| CN111106829B (en) | High-precision ring oscillation circuit and micro-control system | |
| CN211405972U (en) | CMOS-based temperature compensation FBAR crystal oscillator circuit | |
| TWI591459B (en) | Analog electronic clock | |
| TWI790325B (en) | Self-biased amplifier | |
| CN109245723B (en) | On-chip RC oscillator circuit | |
| JPH02147828A (en) | Temperature detection circuit | |
| JP4641221B2 (en) | Oscillation circuit and electronic equipment | |
| JP3635519B2 (en) | Oscillator circuit | |
| JPS60111528A (en) | Integrated circuit device | |
| CN219740325U (en) | Self-adaptive crystal oscillator starting circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |