CN109672408B

CN109672408B - Low-power-consumption programmable crystal oscillator circuit capable of starting oscillation quickly

Info

Publication number: CN109672408B
Application number: CN201811396584.3A
Authority: CN
Inventors: 汪涛
Original assignee: Hefei Chipsea Electronics Technology Co Ltd
Current assignee: Hefei Chipsea Electronics Technology Co Ltd
Priority date: 2018-11-22
Filing date: 2018-11-22
Publication date: 2023-02-03
Anticipated expiration: 2038-11-22
Also published as: CN109672408A

Abstract

The invention discloses a low-power consumption rapid oscillation starting programmable crystal oscillator circuit, which relates to the technical field of integrated circuits and comprises the following components: the independent current source is connected with the current control circuit, the current control circuit is connected with the amplifying circuit, a first output end of the crystal oscillator is connected with an input end of the amplifying circuit, a second output end of the crystal oscillator is connected with an output end of the amplifying circuit, the crystal oscillator is connected with a first comparator, a first comparator is connected with a second comparator, the second comparator is connected with the level conversion circuit, the level conversion circuit is connected with a first phase inverter, the first phase inverter is connected with a counter and an AND gate, the counter is connected with a logic digital circuit, the counter is connected with the AND gate, the AND gate is connected with a second phase inverter, the second phase inverter outputs signals, and the logic digital circuit is connected with the current control circuit. The invention has the advantages that: when the oscillation amplitude of the crystal oscillator is quite large, some switches are closed to maintain continuous oscillation, and the oscillation is started quickly through large current and then is changed into small current and low power consumption after the oscillation is started.

Description

Low-power-consumption programmable crystal oscillator circuit capable of starting oscillation quickly

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption rapid-oscillation-starting programmable crystal oscillator circuit.

Background

With the coming of the era of internet of things, the smart home and the intelligent health industry tend to bring about greater demands on the MCU chip. With the development of the single chip microcomputer technology (MCU chip), the rapid development of the semiconductor technology and the process enables the MCU product performance to be greatly improved so as to meet the requirements of the current development trend of the Internet of things, wherein the MCU product performance particularly has low power consumption and low cost and is an urgent requirement for the design of integrated circuits.

The crystal oscillator can provide high-precision clock signals for various electronic systems, but the requirements on the crystal oscillator circuit are different under different application environments. For example, portable battery powered mobile devices may even need to operate for several years, which places stringent demands on power consumption; in the internet of things system, switching is required to be continuously carried out between sleep and activation, and in the switching process, the switching time depends on the oscillation starting time of the crystal, so the oscillation starting time is as short as possible.

In the prior art, in order to reduce power consumption, a smaller current is provided, which results in a reduced gain and an increased oscillation starting time; in order to reduce the oscillation starting time, larger current is provided, so that the oscillation starting of the crystal oscillator is accelerated, but the power consumption is increased. This is a conflicting problem for crystal oscillator circuits.

At present, a pierce type oscillator circuit is commonly used as an amplifier circuit of a crystal oscillator. As shown in fig. 1 below, a negative resistance analysis method was used.

The small signal equivalent circuit shows that:

after simplification, the following steps are known:

at the oscillating operating frequency, one can calculate:

in the above formula

Is called frequency traction factor, 0-0.25%.

Since the Barkhausen criterion can now be equivalently expressed as:

that is:

Re(Z _C )+R _m ＝0 (7)

referring again to equation (2), since ZC is a "bilinear function" of gm, the trajectory of function ZC (gm) in the complex plane is a circle, as shown in fig. 2 (here we only consider the left half circle). When gm is "0" and "infinity", respectively, the difference between the maximum value and the minimum value of the imaginary part of ZC is the diameter of the circle, and the equivalent circuit of ZC is shown in the figure. The vertical black straight line in fig. 2 represents the locus of the function Zm (p), and the intersection points a and B of the two loci are the critical points of oscillation. When gm > gmA, the circuit will oscillate under the influence of noise or power supply jitter; when gm exceeds gmB, oscillation cannot be formed. When gm = gmopt, ZC will reach maximum negative impedance (a few k Ω or more). The critical transconductance value gmcrit of the oscillation can be solved by combining the equations (11) and (15), but only the smaller solution (gmA) is taken as a design value, because the p value corresponding to the B point is too large, and does not meet the requirement of an actual circuit.

The time constant of the Pierce crystal oscillating circuit is as follows:

the minus sign in the above formula is because Re (ZC) is a negative resistance, and it is apparent that the establishment time is shortest when Re (ZC) is the maximum value.

The derivative extremum of equation (11) can be obtained:

bringing (21) into (19) to obtain:

when CL1 and CL2 are much larger than C3, the bracket part in the equation (22) is approximately equal to 1, and since C3 is often several hundred times Cm, the time constant tends to be also hundreds times the oscillation period. The oscillation settling time is typically 5-15 r, i.e. the minimum oscillation settling time may be several thousand times the oscillation period.

It should be noted that we make two assumptions in the calculation process to arrive at the above results: firstly, re (ZC) takes the maximum negative value, and secondly, CL1 and CL2 are far larger than C3. However, these two assumptions are difficult to implement in a practical circuit. First, to obtain the maximum negative value of Re (ZC), gm is tens to hundreds times higher than gmcrit, and we can only take gm as ten times higher than gmcrit in design to be suitable. Secondly, from the viewpoint of loop gain, the values of CL1 and CL2 are limited, and may not be much larger than C3, and are generally more than 2 times of C3, which is more suitable. It is not surprising that the oscillation time is much longer than several thousand times the oscillation period.

Disclosure of Invention

The invention aims to solve the technical problem that the conventional crystal oscillator cannot achieve low-power-consumption rapid oscillation starting.

The invention solves the technical problems through the following technical scheme, and the specific technical scheme is as follows:

a low power fast start-up programmable crystal oscillator circuit, comprising: the feedback resistor is connected in parallel with two ends of the crystal oscillator, one end of the first capacitor C1 is connected with a first output end of the crystal oscillator, one end of the second capacitor C2 is connected with a second output end of the crystal oscillator, and the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded; further comprising: the circuit comprises an independent current source, a current control circuit, an amplifying circuit, a first comparator, a second comparator, a level conversion circuit, a first phase inverter, a counter, a logic digital circuit, an AND gate and a second phase inverter, wherein the independent current source is connected with the input end of the current control circuit, the output end of the current control circuit is connected with the driving end of the amplifying circuit, the first output end of a crystal oscillator is connected with the input end of the amplifying circuit, the second output end of the crystal oscillator is connected with the output end of the amplifying circuit, the first output end and the second output end of the crystal oscillator are respectively connected with the first input end and the second input end of the first comparator, the first output end and the second output end of the first comparator are respectively connected with the first input end and the second input end of the second comparator, the output end of the level conversion circuit is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the input end of the counter and the first input end of the AND gate, the first output end of the logic digital circuit is connected with the input end of the logic digital circuit, the second output end of the counter is connected with the second input end of the second phase inverter, and the output end of the logic digital circuit.

Furthermore, the independent current source comprises a first PMOS tube, a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube and a first resistor R1, wherein the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode thereof, the drain electrode of the tenth NMOS tube and the drain electrode of the fourth NMOS tube, the drain electrode of the first PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the fourth NMOS tube, the drain electrode of the third NMOS tube is connected with the grid electrode thereof, the grid electrode of the fourth NMOS tube, the grid electrode of the seventh NMOS tube and the grid electrode of the ninth NMOS tube, the source electrode of the fourth NMOS tube is connected with one end of the first resistor R1, the grid electrode of the fifth PMOS tube is connected with an enabling control signal, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eighth NMOS tube and the drain electrode of the ninth NMOS tube, the grid electrode of the eighth NMOS tube is connected with the drain electrode of the eighth NMOS tube and the grid electrode of the tenth NMOS tube, the source electrode of the fifth PMOS tube, the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with a power supply, and the source electrode of the eighth NMOS tube, the source electrode of the ninth NMOS tube, the source electrode of the tenth NMOS tube, the source electrode of the third NMOS tube and the other end of the first resistor R1 are grounded.

Furthermore, the ratio of the width-to-length ratio of the first PMOS transistor to the width-to-length ratio of the second PMOS transistor is 3.

Furthermore, the ratio of the width-to-length ratio of the third NMOS transistor to the width-to-length ratio of the fourth NMOS transistor is 1.

Furthermore, the sixth PMOS tube and the seventh PMOS tube are inverse ratio tubes.

Furthermore, the current control circuit comprises an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor and a transmission gate, wherein the gates of the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor and the sixteenth PMOS transistor are connected to the gate of the second PMOS transistor, the drains of the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor and the sixteenth PMOS transistor are respectively connected to the input terminal of one transmission gate, the drains of the eleventh PMOS transistor and the output terminals of all transmission gates are connected to the input terminal of the amplifying circuit, and the control terminal of the transmission gate is connected to the output terminal of the logic digital circuit.

Furthermore, the transmission gate is formed by a PMOS transistor and an NMOS transistor, the source of the PMOS transistor of the transmission gate is connected to the drain of the NMOS transistor and serves as the input terminal of the transmission gate, the drain of the PMOS transistor of the transmission gate is connected to the source of the NMOS transistor and serves as the output terminal of the transmission gate, and the gates of the PMOS transistor and the NMOS transistor serve as the control terminals of the transmission gate and are connected to the output terminal of the logic digital circuit.

Furthermore, the amplifying circuit comprises a seventeenth PMOS tube and an eighteenth NMOS tube, wherein the drain electrode of the seventeenth PMOS tube is connected with the drain electrode of the eighteenth NMOS tube, the gate electrode of the seventeenth PMOS tube is connected with the gate electrode of the eighteenth NMOS tube, the drain electrode of the eleventh PMOS tube and the output end of the transmission gate are both connected with the source electrode of the seventeenth PMOS tube, the gate electrode of the seventeenth PMOS tube and the gate electrode of the eighteenth NMOS tube are connected with the first output end of the crystal oscillator, and the drain electrode of the seventeenth PMOS tube and the drain electrode of the eighteenth NMOS tube are connected with the second output end of the crystal oscillator.

Furthermore, the first comparator comprises a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube and a twenty-fifth NMOS tube, wherein the grid electrode of the nineteenth PMOS tube is connected with the grid electrode of the second PMOS tube, the source electrode of the nineteenth PMOS tube is connected with a power supply, the drain electrode of the nineteenth PMOS tube is connected with the source electrode of the twentieth PMOS tube and the source electrode of the twenty-first PMOS tube, the drain electrode of the twentieth PMOS tube is connected with the drain electrode of the twenty-second NMOS tube and the drain electrode of the twenty-fourth NMOS tube, the drain electrode of the twenty-first PMOS tube is connected with the drain electrode of the twenty-fifth NMOS tube and the drain electrode of the twenty-third NMOS tube, the grid electrode of the twenty-second NMOS transistor is connected with the drain electrode of the twenty-second NMOS transistor and the grid electrode of the twenty-third NMOS transistor, the grid electrode of the twenty-fifth NMOS transistor is connected with the drain electrode of the twenty-fifth NMOS transistor and the grid electrode of the twenty-fourth NMOS transistor, the source electrode of the twenty-second NMOS transistor, the source electrode of the twenty-third NMOS transistor, the source electrode of the twenty-fourth NMOS transistor and the source electrode of the twenty-fifth NMOS transistor are grounded, the grid electrode of the twentieth PMOS transistor is connected with the second output end of the crystal oscillator, the grid electrode of the twenty-first PMOS transistor is connected with the first output end of the crystal oscillator, the drain electrode of the twenty-second NMOS transistor serves as the first output end of the first comparator, and the drain electrode of the twenty-fifth NMOS transistor serves as the second output end of the second comparator.

Furthermore, the second comparator comprises a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirty-seventh PMOS transistor, a thirty-eleventh NMOS transistor, a thirty-second PMOS transistor, and a thirty-third NMOS transistor, wherein the gate of the twenty-sixth PMOS transistor is connected to the drain thereof, the gate of the twenty-seventh PMOS transistor, and the drain of the twenty-eighth NMOS transistor, the drain of the twenty-seventh PMOS transistor is connected to the drain of the twenty-ninth NMOS transistor, the drain of the thirty-seventh PMOS transistor is connected to the drain of the thirty-ninth NMOS transistor, the gate of the thirty-fifth PMOS transistor, the gate of the thirty-sixth PMOS transistor, and the drain of the twenty-eighth NMOS transistor are connected, the gate of the thirty-second PMOS transistor, the gate of the thirty-third PMOS transistor are connected to the drain of the twenty-ninth NMOS transistor, the source of the thirty-sixth PMOS transistor, the source of the twenty-seventh PMOS transistor, the source of the thirty-second PMOS transistor, the source of the thirty-third PMOS transistor, and the thirty-third NMOS transistor are connected together, the source of the twenty-ninth PMOS transistor is used as the drain of the twenty-sixth PMOS transistor, the twenty-eighth NMOS transistor, the source of the twenty-ninth comparator, the twenty-eighth NMOS transistor, the twenty-ninth NMOS transistor, the source of the twenty-eighth NMOS transistor, the drain of the eleventh comparator, and the twenty-eighth NMOS transistor, and the eleventh comparator, and the twenty-eighth NMOS transistor are used as the source of the input terminal of the twenty-ninth comparator, and the twenty-ninth input terminal of the twenty-eighth NMOS transistor, and the twenty-eighth NMOS, and the twenty-ninth comparator, and the twenty-ninth input terminal of the twenty-eighth-ninth comparator, and the eleventh comparator.

Compared with the prior art, the invention has the following advantages:

1. the driving capacity can be adjusted according to the actual environment requirement of the application, and under the minimum driving capacity, the power consumption is less than 500nA; 2. when the crystal oscillation can generate clock signals, the amplitude of the oscillation is relatively large, and at the moment, some switches are closed, although the current is reduced, the oscillation can be maintained continuously, so that the oscillation can be started quickly with a large current, and the oscillation can be changed into a small current after the oscillation is started, and the power consumption is low. 3. The waveform generated by the oscillation core circuit is shaped, so that the slope of the rising edge or the falling edge is increased, and the power consumption can be reduced. 4. The second comparator is powered by a linear voltage stabilizer, and the generated comparison result is processed by a level converter, so that the power consumption can be further reduced.

Drawings

Fig. 1 is a simplified model of a Pierce crystal circuit and a small-signal equivalent circuit in the prior art.

FIG. 2 is a graph of complex plane analysis of ZC of the prior art.

Fig. 3 is a schematic diagram of a low power consumption fast start-up programmable crystal oscillator according to an embodiment of the present invention.

Fig. 4 is a low-power consumption fast start-up programmable crystal oscillator independent current source circuit according to an embodiment of the present invention.

Fig. 5 shows a current control circuit and an amplifying circuit of a low power consumption fast start-up programmable crystal oscillator according to an embodiment of the present invention.

Fig. 6 is a circuit diagram of a first comparator of a low power consumption fast start-up programmable crystal oscillator according to an embodiment of the invention.

Fig. 7 is a circuit diagram of a second comparator of a low power consumption fast start-up programmable crystal oscillator according to an embodiment of the present invention.

Detailed Description

The following examples are given for the detailed implementation and specific operation of the present invention, but the scope of the present invention is not limited to the following examples.

As shown in fig. 3, a low power consumption fast start-up programmable crystal oscillator circuit includes: the crystal oscillator XTAL comprises a crystal oscillator XTAL, a feedback resistor RF, a capacitor C1 and a capacitor C2, wherein the feedback resistor RF is connected in parallel with two ends of the crystal oscillator XTAL, one end of the capacitor C1 is connected with a first output end XI of the crystal oscillator XTAL, one end of a second capacitor C2 is connected with a second output end XO of the crystal oscillator XTAL, and the other end of the capacitor C1 and the other end of the capacitor C2 are grounded; the low-power consumption rapid start-up programmable crystal oscillator circuit further comprises: the circuit comprises an independent current source, a current control circuit 1, an amplifying circuit 2, a first comparator 3, a second comparator 4, a level conversion circuit 5, a first inverter 6, a counter 7, a logic digital circuit 8, an AND gate 9 and a second inverter 10, wherein the independent current source is connected with the input end of the current control circuit 1, the output end of the current control circuit 1 is connected with the driving end of the amplifying circuit 2, a first output end XI of a crystal oscillator XTAL is connected with the input end of the amplifying circuit 2, a second output end XO of the crystal oscillator XTAL is connected with the output end of the amplifying circuit 2, the first output end XI and the second output end XO of the crystal oscillator XTAL are respectively connected with the first input end and the second input end of the first comparator 3, the first output end and the second output end of the first comparator 3 are respectively connected with the 4 first input end and the second input end of the second comparator, the first output end and the second output end of the second comparator 4 are respectively connected with the first input end and the second input end of the level switching circuit 5, the output end of the level switching circuit 5 is connected with the input end of the first phase inverter 6, the output end of the first phase inverter 6 is connected with the input end of the counter 7 and the first input end 1 of the AND gate 9, the first output end of the counter is connected with the input end of the logic digital circuit, the second output end of the counter is connected with the second input end of the AND gate, the output end of the AND gate is connected with the input end of the second phase inverter, the output end of the second phase inverter outputs signals, and the logic digital circuit is connected with the control end of the current control circuit.

Specifically, according to the working principle of the crystal oscillator circuit, when enabled, the independent current source provides current for the circuit, XI and XO of the crystal oscillator start oscillation, when the amplitude reaches a certain value, the first comparator 3 starts working, then the shaping is continuously carried out through the second comparator 4, a square wave signal is output, the square wave signal passes through the level conversion circuit and the digital logic circuit, when the counter 7 is full, part of switches in the partial current control circuit are closed, and meanwhile, a clock signal is output.

As shown in fig. 4, the independent current source includes a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, and a first resistor R1, wherein the gate of the first PMOS transistor M1 is connected to the gate of the second PMOS transistor M2, the gate of the second PMOS transistor M2 is connected to the drain thereof, the drain of the tenth NMOS transistor M10, and the drain of the fourth NMOS transistor M4, the drain of the first PMOS transistor M1 is connected to the drain of the third NMOS transistor M3, the drain of the second PMOS transistor M2 is connected to the drain of the fourth NMOS transistor M4, the drain of the third NMOS transistor M3 is connected to the gate thereof, the gate of the fourth NMOS transistor M4, the gate of the seventh PMOS transistor M7, and the gate of the ninth NMOS transistor M9, the source of the fourth NMOS transistor M4 is connected to one end of the first resistor R1, the gate of the fifth PMOS transistor M5 is connected to the enable control signal, the drain of the fifth PMOS transistor M5 is connected to the source of the sixth PMOS transistor M6, the gate of the sixth PMOS transistor M6 is connected to the drain thereof, the drain of the sixth PMOS transistor M6 is connected to the source of the seventh PMOS transistor M7, the drain of the seventh PMOS transistor M7 is connected to the drain of the eighth NMOS transistor M8 and the drain of the ninth NMOS transistor M9, the gate of the eighth NMOS transistor M8 is connected to the drain thereof and the gate of the tenth NMOS transistor M10, the source of the fifth PMOS transistor M5, the source of the first PMOS transistor M1, the source of the second PMOS transistor M2, the source of the eighth NMOS transistor M8, the source of the ninth NMOS transistor M9, the source of the tenth NMOS transistor M10, the source of the third NMOS transistor M3, and the other end of the first resistor R1 are grounded. The ratio of the width-to-length ratio of the first PMOS transistor M1 to the width-to-length ratio of the second PMOS transistor M2 is 3. The ratio of the width-to-length ratio of the third NMOS transistor M3 to the width-to-length ratio of the fourth NMOS transistor M4 is 1. The sixth PMOS tube M6 and the seventh PMOS tube M7 are inverse ratio tubes.

The working principle of the independent current source is as follows: when the NMOS transistor is enabled, the grid electrode of the fifth PMOS transistor M5 is pulled down, the grid electrode and the drain electrode of the eighth NMOS transistor M8 are raised, the tenth NMOS transistor M10 is conducted, the grid electrode levels of the first PMOS transistor M1 and the second PMOS transistor M2 are pulled down, the grid electrode levels of the third NMOS transistor N3 and the fourth NMOS transistor M4 are forced to be raised and conducted, the grid electrode level of the seventh PMOS transistor M7 is raised, and the current of the branch circuit is limited; the grid end level of the ninth NMOS tube M9 is increased and conducted, the grid end voltage of the eighth NMOS tube is reduced, a feedback is formed, and finally the current source is stabilized.

As shown in fig. 5, the current control circuit 1 includes an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth PMOS transistor M16, and a transmission gate, gates of the eleventh PMOS transistor M11, the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, and the sixteenth PMOS transistor M16 are connected to a gate of the second PMOS transistor M2, drains of the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, and the sixteenth PMOS transistor M16 are respectively connected to an input terminal of one transmission gate, a drain of the eleventh PMOS transistor M11 and output terminals of all transmission gates are connected to an input terminal of the amplifying circuit 2, and a control terminal of the transmission gate is connected to an output terminal of the logic digital circuit 8.

The transmission gate is formed by a PMOS tube and an NMOS tube, the source electrode of the PMOS tube of the transmission gate is connected with the drain electrode of the NMOS tube and is used as the input end of the transmission gate, the drain electrode of the PMOS tube of the transmission gate is connected with the source electrode of the NMOS tube and is used as the output end of the transmission gate, and the grid electrodes of the PMOS tube and the NMOS tube are used as the control end of the transmission gate and are connected with the output end of the logic digital circuit. Specifically, in this embodiment, 5 transmission gates S1, S21, S22, S31, and S32 are used, where the transmission gate S1 is composed of a PMOS transistor S1N and an NMOS transistor S1P, the transmission gate S2 is composed of a PMOS transistor S21N and an NMOS transistor S21P, the transmission gate S22 is composed of a PMOS transistor S22N and an NMOS transistor S22P, the transmission gate S31 is composed of a PMOS transistor S31N and an NMOS transistor S21P, and the transmission gate S32 is composed of a PMOS transistor S32N and an NMOS transistor S32P. The transmission gate is a switch, and the on/off of the switches S1, S21, S22, S31, and S32 is controlled by a signal output from the logic digital circuit 8. Thereby achieving a controlled current.

The amplifying circuit 2 comprises a seventeenth PMOS tube M17 and an eighteenth NMOS tube M18, wherein the drain electrode of the seventeenth PMOS tube M17 is connected with the drain electrode of the eighteenth NMOS tube M18, the gate electrode of the seventeenth PMOS tube M17 is connected with the gate electrode of the eighteenth NMOS tube M18, the drain electrode of the eleventh PMOS tube M11 and the output end of the transmission gate are both connected with the source electrode of the seventeenth PMOS tube M17, the gate electrode of the seventeenth PMOS tube M17 and the gate electrode of the eighteenth NMOS tube M18 are connected with a first output end XI of the crystal oscillator, and the drain electrode of the seventeenth PMOS tube M17 and the drain electrode of the eighteenth NMOS tube M18 are connected with a second output end XO of the crystal oscillator. Two ends of the feedback resistor RF are respectively connected to the drain of the seventeenth PMOS transistor M17 and the drain of the eighteenth NMOS transistor M18, and the gate of the seventeenth PMOS transistor M17 and the gate of the eighteenth NMOS transistor M18.

Specifically, the current of the independent current source is mirrored to the branches of an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth PMOS transistor M15 and a sixteenth PMOS transistor M16, the current conduction of the branches of the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15 and the sixteenth PMOS transistor M16 is limited by the switch, the current flows through the drain of the seventeenth PMOS transistor M17 and the amplifier of the eighteenth NMOS transistor M18, and whether part of the switch is turned off or not can be reasonably selected according to the needs of the working occasion.

As shown in fig. 6, the first comparator 3 includes a nineteenth PMOS transistor M19, a twentieth PMOS transistor M20, a twenty-first PMOS transistor M21, a twenty-second NMOS transistor M22, a twenty-third NMOS transistor M23, a twenty-fourth NMOS transistor M24, a twenty-fifth NMOS transistor M25, a gate of the nineteenth PMOS transistor M19 is connected to a gate of the second PMOS transistor M2, a source of the nineteenth PMOS transistor M19 is connected to the power supply, a drain of the nineteenth PMOS transistor M19 is connected to a source of the twentieth PMOS transistor M20 and a source of the twenty-first PMOS transistor M21, a drain of the twentieth PMOS transistor M20 is connected to a drain of the twenty-second NMOS transistor M22 and a drain of the twenty-fourth NMOS transistor M24, a drain of the twenty-first PMOS transistor M21 is connected to a drain of the twenty-fifth NMOS transistor M25 and a drain of the twenty-third NMOS transistor M23, the gate of the twenty-second NMOS transistor M22 is connected to the drain thereof and the gate of the twenty-third NMOS transistor M23, the gate of the twenty-fifth NMOS transistor M25 is connected to the drain thereof and the gate of the twenty-fourth NMOS transistor M24, the source of the twenty-second NMOS transistor M22, the source of the twenty-third NMOS transistor M23, the source of the twenty-fourth NMOS transistor M24, and the source of the twenty-fifth NMOS transistor M25 are grounded, the gate of the twentieth PMOS transistor M20 is connected to the second output terminal XO of the crystal oscillator, the gate of the twenty-first PMOS transistor M21 is connected to the first output terminal XI of the crystal oscillator, the drain of the twenty-second NMOS transistor M22 is used as the first output terminal of the first comparator 3, and the drain of the twenty-fifth NMOS transistor M25 is used as the second output terminal of the second comparator 4.

Specifically, according to the working principle of the first comparator, the current of the independent power supply is mirrored to the nineteenth PMOS transistor M19, the first output terminal XI and the second output terminal XO of the crystal oscillator XTAL are used as the input of the first comparator 3 to preliminarily shape the signal, and VOUT1 and VOUT2 are respectively used as the first output and the second output of the first comparator.

As shown in fig. 7, the second comparator 4 includes a twenty-sixth PMOS transistor M26, a twenty-seventh PMOS transistor M27, a twenty-eighth NMOS transistor M28, a twenty-ninth NMOS transistor M29, a thirty-eighth PMOS transistor M30, a thirty-eleventh NMOS transistor M31, a thirty-second PMOS transistor M32, and a thirty-third NMOS transistor M33, the gate of the twenty-sixth PMOS transistor M26 is connected to the drain thereof, the gate of the twenty-seventh PMOS transistor M27, and the drain of the twenty-eighth NMOS transistor M28, the drain of the twenty-seventh PMOS transistor M27 is connected to the drain of the twenty-ninth NMOS transistor M29, the drain of the thirty-PMOS transistor M30 is connected to the drain of the thirty-eleventh NMOS transistor M31, the gate of the thirty-seventh PMOS transistor M30, and the gate of the thirty-eleventh NMOS transistor M31 are connected to the drain of the twenty-eighth NMOS transistor M28, the drain of the thirty-second PMOS transistor M32 is connected to the drain of the thirty-third PMOS transistor M33, the gate of the thirty-second PMOS transistor M32, the gate of the thirty-third PMOS transistor M33 and the drain of the twenty-ninth NMOS transistor M29 are connected, the source of the thirty-second PMOS transistor M30, the source of the twenty-sixth PMOS transistor M26, the source of the twenty-seventh PMOS transistor M27 and the source of the thirty-second PMOS transistor M32 are all wired voltage regulators, the source of the thirty-eleventh NMOS transistor M31, the source of the twenty-eighth NMOS transistor M28, the source of the twenty-ninth NMOS transistor M29 and the source of the thirty-third NMOS transistor M33 are grounded, the gate of the twenty-eighth NMOS transistor M28 is used as the first input terminal of the second comparator 4, the gate of the twenty-ninth NMOS transistor M29 is used as the second input terminal of the second comparator 4, the drain of the thirty-eleventh NMOS transistor M31 is used as the first output terminal of the second comparator 4, and the drain of the thirty-third NMOS transistor M33 is used as the second output terminal of the second comparator 4.

In this embodiment, the output of the first comparator 3 is used as the first input VIN1 and the second input VIN2 of the second comparator 4 to shape the signal waveform, the first output VOUT3 and the second output VOUT4 of the second comparator 4 are connected to the level conversion circuit, the voltage provided by the linear regulator is increased from V _ LDO to VDD, and then shaped by the first inverter 6, one path of clock signal passes through the switches S1, S21, S22, S31, and S32 of the counter 7 to control the current mirror, and meanwhile, the counter 7 generates a high level and the second path of clock signal to perform a logic and operation, and finally outputs the clock signal CLK.

In summary, the present application can adjust the driving capability according to the actual environmental requirements of the application, and the power consumption is less than 500nA at the minimum driving capability; when the crystal oscillation can generate clock signals, the amplitude of the oscillation is relatively large, and at this time, some switches are closed, although the current can be reduced, the continuous oscillation can be maintained, so that the oscillation can be started quickly with large current, and can be changed into small current after the oscillation is started, and the power consumption is low; the waveform generated by the oscillation core circuit is shaped, so that the slope of a rising edge or a falling edge is increased, and the power consumption can be reduced; the second comparator 4 is powered by a linear voltage regulator, and the generated comparison result passes through a level conversion circuit, so that the power consumption can be further reduced.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A low power fast start-up programmable crystal oscillator circuit, comprising: the feedback resistor is connected in parallel with two ends of the crystal oscillator, one end of the first capacitor C1 is connected with a first output end of the crystal oscillator, one end of the second capacitor C2 is connected with a second output end of the crystal oscillator, and the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded; it is characterized by also comprising: the circuit comprises an independent current source, a current control circuit, an amplifying circuit, a first comparator, a second comparator, a level conversion circuit, a first phase inverter, a counter, a logic digital circuit, an AND gate and a second phase inverter, wherein the independent current source is connected with the input end of the current control circuit, the output end of the current control circuit is connected with the driving end of the amplifying circuit, the first output end of a crystal oscillator is connected with the input end of the amplifying circuit, the second output end of the crystal oscillator is connected with the output end of the amplifying circuit, the first output end and the second output end of the crystal oscillator are respectively connected with the first input end and the second input end of the first comparator, the first output end and the second output end of the first comparator are respectively connected with the first input end and the second input end of the second comparator, the output end of the level conversion circuit is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the input end of the counter and the first input end of the AND gate, the first output end of the logic digital circuit is connected with the input end of the logic digital circuit, the second output end of the counter is connected with the second input end of the second phase inverter, and the output end of the logic digital circuit.

2. The low-power-consumption programmable crystal oscillator circuit with fast oscillation starting of claim 1, wherein the independent current source comprises a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and a first resistor R1, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the second PMOS transistor is connected to the drain of the second PMOS transistor, the drain of the tenth NMOS transistor, and the drain of the fourth NMOS transistor, the drain of the first PMOS transistor is connected to the drain of the third NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor, the drain of the third NMOS transistor is connected to the gate of the third PMOS transistor, the gate of the fourth NMOS transistor, the gate of the seventh PMOS transistor, and the gate of the ninth NMOS transistor, the source electrode of the fourth NMOS tube is connected with one end of the first resistor R1, the grid electrode of the fifth PMOS tube is connected with an enabling control signal, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eighth NMOS tube and the drain electrode of the ninth NMOS tube, the grid electrode of the eighth NMOS tube is connected with the drain electrode of the eighth NMOS tube and the grid electrode of the tenth NMOS tube, the source electrode of the fifth PMOS tube, the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with a power supply, and the source electrode of the eighth NMOS tube, the source electrode of the ninth NMOS tube, the source electrode of the tenth NMOS tube, the source electrode of the third NMOS tube and the other end of the first resistor R1 are grounded.

3. A low power consumption fast start-up programmable crystal oscillator circuit according to claim 2, wherein the ratio of the width to length ratio of the first PMOS transistor to the width to length ratio of the second PMOS transistor is 3.

4. A low power consumption fast start-up programmable crystal oscillator circuit as claimed in claim 2, wherein the ratio of the width to length ratio of the third NMOS transistor to the width to length ratio of the fourth NMOS transistor is 1.

5. The low power consumption fast start-up programmable crystal oscillator circuit according to claim 2, wherein the sixth and seventh PMOS transistors are inverting transistors.

6. The low-power-consumption programmable crystal oscillator circuit capable of starting oscillation quickly of claim 2, wherein the current control circuit comprises an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor and a transmission gate, gates of the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor and the sixteenth PMOS transistor are connected with gates of the second PMOS transistor, drains of the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor and the sixteenth PMOS transistor are respectively connected with an input terminal of one transmission gate, drains of the eleventh PMOS transistor and output terminals of all transmission gates are connected with input terminals of the amplifying circuit, and a control terminal of the transmission gate is connected with an output terminal of the logic digital circuit.

7. The low power consumption fast oscillation starting programmable crystal oscillator circuit according to claim 6, wherein the transmission gate is formed by a PMOS transistor and an NMOS transistor, the source of the PMOS transistor of the transmission gate is connected to the drain of the NMOS transistor and serves as the input terminal of the transmission gate, the drain of the PMOS transistor of the transmission gate is connected to the source of the NMOS transistor and serves as the output terminal of the transmission gate, and the gates of the PMOS transistor and the NMOS transistor serve as the control terminals of the transmission gate and are connected to the output terminal of the logic digital circuit.

8. The low-power-consumption programmable crystal oscillator circuit with fast oscillation start of claim 6, wherein the amplifying circuit comprises a seventeenth PMOS transistor and an eighteenth NMOS transistor, the drain of the seventeenth PMOS transistor is connected to the drain of the eighteenth NMOS transistor, the gate of the seventeenth PMOS transistor is connected to the gate of the eighteenth NMOS transistor, the drain of the eleventh PMOS transistor and the output of the transmission gate are both connected to the source of the seventeenth PMOS transistor, the gate of the seventeenth PMOS transistor and the gate of the eighteenth NMOS transistor are connected to the first output of the crystal oscillator, and the drain of the seventeenth PMOS transistor and the drain of the eighteenth NMOS transistor are connected to the second output of the crystal oscillator.

9. The low-power-consumption programmable crystal oscillator circuit with rapid start-up of oscillation of claim 2, wherein the first comparator comprises a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor and a twenty-fifth NMOS transistor, wherein the gate of the nineteenth PMOS transistor is connected with the gate of the second PMOS transistor, the source of the nineteenth PMOS transistor is connected with the power supply, the drain of the nineteenth PMOS transistor is connected with the source of the twentieth PMOS transistor and the source of the twenty-first PMOS transistor, the drain of the twentieth PMOS is connected with the drain of the twenty-second NMOS transistor and the drain of the twenty-fourth NMOS transistor, the drain electrode of the twenty-first PMOS tube is connected with the drain electrode of the twenty-fifth NMOS tube and the drain electrode of the twenty-third NMOS tube, the grid electrode of the twenty-second NMOS tube is connected with the drain electrode of the twenty-fifth NMOS tube and the grid electrode of the twenty-third NMOS tube, the grid electrode of the twenty-fifth NMOS tube is connected with the drain electrode of the twenty-fourth NMOS tube and the grid electrode of the twenty-fourth NMOS tube, the source electrode of the twenty-second NMOS tube, the source electrode of the twenty-third NMOS tube, the source electrode of the twenty-fourth NMOS tube and the source electrode of the twenty-fifth NMOS tube are grounded, the grid electrode of the twenty-fifth PMOS tube is connected with the second output end of the crystal oscillator, the grid electrode of the twenty-first PMOS tube is connected with the first output end of the crystal oscillator, the drain electrode of the twenty-second NMOS tube is used as the first output end of the first comparator, and the drain electrode of the twenty-fifth NMOS tube is used as the second output end of the second comparator.

10. The low-power consumption programmable crystal oscillator circuit capable of starting oscillation quickly of claim 1, wherein the second comparator comprises a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirty-sixth PMOS transistor, a thirty-eleventh NMOS transistor, a thirty-second PMOS transistor and a thirty-third NMOS transistor, the grid electrode of the twenty-sixth PMOS transistor is connected with the drain electrode thereof, the grid electrode of the twenty-seventh PMOS transistor and the drain electrode of the twenty-eighth NMOS transistor, the drain electrode of the twenty-seventh PMOS transistor is connected with the drain electrode of the twenty-ninth NMOS transistor, the drain electrode of the thirty-sixth PMOS transistor is connected with the drain electrode of the thirty-eleventh NMOS transistor, the grid electrode of the thirty-sixth PMOS transistor and the drain electrode of the twenty-eighth NMOS transistor are connected, the drain electrode of the thirty-second PMOS transistor is connected with the drain electrode of the thirty-third PMOS transistor, the grid electrode of a thirty-second PMOS tube and the grid electrode of a thirty-third PMOS tube are connected with the drain electrode of a twenty-ninth NMOS tube, the source electrode of the thirty-first PMOS tube, the source electrode of a twenty-sixth PMOS tube, the source electrode of a twenty-seventh PMOS tube and the source electrode of the thirty-second PMOS tube are all connected with a voltage stabilizer, the source electrode of a thirty-first NMOS tube, the source electrode of a twenty-eighth NMOS tube, the source electrode of a twenty-ninth NMOS tube and the source electrode of the thirty-third NMOS tube are grounded, the grid electrode of the twenty-eighth NMOS tube is used as a first input end of a second comparator, the grid electrode of the twenty-ninth NMOS tube is used as a second input end of the second comparator, and the drain electrode of the thirty-eleventh NMOS tube is used as a first output end of the second comparator and the drain electrode of the thirty-third NMOS tube is used as a second output end of the second comparator.