CN115422120A - SOC chip and method for releasing multi-stage clock on SOC chip - Google Patents

SOC chip and method for releasing multi-stage clock on SOC chip Download PDF

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CN115422120A
CN115422120A CN202211373259.1A CN202211373259A CN115422120A CN 115422120 A CN115422120 A CN 115422120A CN 202211373259 A CN202211373259 A CN 202211373259A CN 115422120 A CN115422120 A CN 115422120A
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clock
clock source
source module
soc chip
subsystem
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CN115422120B (en
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不公告发明人
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Moore Threads Technology Co Ltd
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Moore Threads Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention relates to an SOC chip and a method for releasing a multi-stage clock on the SOC chip. The SOC chip includes: a plurality of clock source modules located at different locations of the SOC chip, wherein a first clock source module of the plurality of clock source modules is configured to: providing a first control clock to a first subsystem associated with the first clock source module based on a first reference clock, and providing a second reference clock to a second clock source module of the plurality of clock source modules different from the first clock source module, wherein a frequency of the first control clock is higher than frequencies of the first reference clock and the second reference clock.

Description

SOC chip and method for releasing multi-stage clock on SOC chip
Technical Field
The present invention relates to the field of semiconductor chips, and more particularly, to a system on chip (SoC) chip and a method for releasing a multi-level clock on the SoC chip.
Background
A system on a chip (SoC) is a semiconductor technology used to integrate complex multi-functional systems into a single chip. The subsystems provided in the SoC may be designed to be operatively connected to each other through a system bus. In an SoC chip, a clock signal may be generated by a clock source module and then provided to various functional blocks including subsystems. Since the clock signal is related to the overall performance of the interconnect system (including the speed and power consumption of the SoC chip), efficient clocking of the clock signal is required.
In general, an SOC chip may contain multiple subsystems, where each subsystem may have one or more clock requirements at different frequencies. In general, a common scheme to cope with clock requirements of different frequencies may, for example, employ centralized clock control, i.e. the clock source of each subsystem comes from the same clock source module. In other words, multiple subsystems may be clocked (particularly high speed clocks) by a single clock source module, such that the clocks are routed too long. In addition, in this case, each of the plurality of subsystems will typically be turned on simultaneously. When it is desired not to boot a certain subsystem of the plurality of subsystems, specific software may typically be required to control the selection of the certain subsystem such that the certain subsystem is not booted, thereby affecting the boot time of the SOC chip.
Therefore, as the system scale of the SOC chip becomes larger, the above centralized clock control scheme may have the following disadvantages: the clock wiring is too long, the clock quality is influenced, and the power consumption is increased; a large number of high-speed clocks are concentrated together and output to each subsystem, so that the layout and wiring difficulty is increased; and software is needed to control the sequence of system clock release, which affects the starting time of the system.
Therefore, there is a need for improved clock signal management in SOC chips. It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present invention and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
Embodiments of the present invention aim to address one or more of the above disadvantages of centralized clock control in the prior art. The inventor innovatively proposes the following idea: in a large-scale SOC chip system, a distributed clock management system is adopted, that is, according to the SOC chip layout, a plurality of clock source modules are respectively placed at different positions of a chip, wherein the plurality of clock source modules can be cascaded through a low-speed reference clock, and each clock source module outputs a high-speed clock (also referred to as a control clock herein) to an adjacent subsystem. In this way, the solution according to embodiments of the invention improves the management of the clock signals in the SOC chip and thus improves the overall performance of the SOC chip.
According to a first aspect of embodiments of the present invention, there is provided an SOC chip including: a plurality of clock source modules located at different locations of the SOC chip, wherein a first clock source module of the plurality of clock source modules is configured to: providing a first control clock to a first subsystem associated with the first clock source module based on a first reference clock, and providing a second reference clock to a second clock source module of the plurality of clock source modules different from the first clock source module, wherein a frequency of the first control clock is higher than frequencies of the first reference clock and the second reference clock.
In some embodiments of the present invention, the first clock source module is used as a first stage clock source, wherein the first reference clock is located outside the SOC chip or inside the first clock source module.
In some embodiments of the present invention, the first clock source module is used as an intermediate level clock source, wherein the first reference clock is from a third clock source module of the plurality of clock source modules different from the first clock source module and the second clock source module.
In some embodiments of the invention, the second clock source module is used as a final stage clock source and is configured to: providing a second control clock to a second subsystem associated with the second clock source module and providing no reference clock to any clock source module based on the second reference clock, wherein the second control clock has a higher frequency than the second reference clock.
In some embodiments of the invention, the second clock source module is used as an intermediate stage clock source and is configured to: providing a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first clock source module and the second clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
In some embodiments of the invention, the second clock source module is used as a further intermediate stage clock source and is configured to: providing a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first, second, and third clock source modules, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
In some embodiments of the invention, the second clock source module comprises one or more of the plurality of clock source modules.
In some embodiments of the present invention, the SOC chip is a graphics card chip, and the first subsystem and/or the second subsystem is selected from at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem.
In some embodiments of the invention, each of the first reference clock, the second reference clock and the further reference clock has a frequency in the range of 1MHz to 50MHz, and each of the first control clock and the second control clock has a frequency in the range of 100MHz to 10 GHz.
According to a second aspect of embodiments of the present invention, there is provided a method for implementing multi-stage clock release on an SOC chip, the SOC chip including a plurality of clock source modules located at different locations, the method including, by a first clock source module of the plurality of clock source modules, based on a first reference clock: providing a first control clock to a first subsystem associated with the first clock source module and providing a second reference clock to a second clock source module of the plurality of clock source modules different from the first clock source module, wherein a frequency of the first control clock is higher than a frequency of the first reference clock and the second reference clock.
In some embodiments of the invention, the method further comprises: receiving the first reference clock from outside the SOC chip or from inside the first clock source module.
In some embodiments of the invention, the method further comprises: receiving the first reference clock from a third clock source module of the plurality of clock source modules that is different from the first clock source module and the second clock source module.
In some embodiments of the invention, the method further comprises: providing a second control clock from the second clock source module to a second subsystem associated with the second clock source module and providing no reference clock to any clock source module based on the second reference clock, wherein the second control clock has a frequency higher than the second reference clock.
In some embodiments of the invention, the method further comprises: providing, from the second clock source module, a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another one of the plurality of clock source modules that is different from the first clock source module and the second clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
In some embodiments of the invention, the method further comprises: providing, from the second clock source module, a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first clock source module, the second clock source module, and the third clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
According to a third aspect of embodiments of the present invention, there is provided a circuit system including the SOC chip described in the embodiments of the present invention.
According to a fourth aspect of embodiments of the present invention, a computer-readable medium, on which a computer program is stored, which, when being executed by a processor, carries out the method described in the above embodiments.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: by using distributed clock control on the SOC chip, the clock wiring distance on the SOC chip can be shortened, so that the power consumption is reduced and the clock quality is improved; and through the upper-level connection of a plurality of clock source modules on the SOC chip, the automation of multi-stage clock release can be realized, and the starting process is accelerated.
Additional features and advantages of the invention will be set forth in the detailed description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
Drawings
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. Embodiments are depicted in the drawings and are detailed in the description that follows. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 schematically shows a block diagram of an SOC chip according to the prior art.
FIG. 2 schematically shows a block diagram of an SOC chip according to one embodiment of the invention.
Fig. 3 schematically shows a block diagram of an SOC chip according to another embodiment of the present invention.
Fig. 4 schematically shows a block diagram of an SOC chip according to still another embodiment of the present invention.
Fig. 5 schematically shows a block diagram of an SOC chip according to yet another embodiment of the present invention.
Fig. 6 schematically shows a block diagram of one example of a clock source module in an SOC chip according to one embodiment of the present invention.
FIG. 7 schematically shows a flow diagram of one example of a method for implementing multi-stage clock release on a SOC chip, according to an embodiment of the invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations or operations have not been shown or described in detail to avoid obscuring aspects of the invention.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.
The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
In general, aspects of the invention relate to improving clock signal generation and management in SOC chips. Specifically, for example, in a large-scale SOC chip system, a distributed clock management system is adopted, that is, according to the SOC chip layout, a plurality of clock source modules are respectively disposed at different positions of the chip, wherein the plurality of clock source modules may be cascaded by low-speed reference clocks, and each clock source module outputs a high-speed clock (also referred to as a control clock herein) to an adjacent subsystem. In this way, the solution according to embodiments of the present invention improves the generation and management of clock signals in the SOC chip and thus improves the overall performance of the SOC chip. As used herein, the term "low speed clock" or "reference clock" refers to a clock signal used to cascade any two clock source modules in an SOC chip, generally having a frequency in the range of 1MHz to 50 MHz; while the term "high speed clock" or "control clock" refers to the clock signal used to provide to the subsystems in the SOC chip, typically in the frequency range of 100MHz to 10 GHz.
Fig. 1 schematically shows a block diagram of an SOC chip 100 according to the prior art. Referring to fig. 1, an SoC chip 100 according to the related art may include a plurality of subsystems 110, 120, 130, 140 and a single clock source module 10.
As shown in fig. 1, the clock source module 10 may be configured to provide corresponding control clock signals 101, 102, 103, 104 to a plurality of subsystems 110, 120, 130, 140, for example, wherein the control clock signals 101, 102, 103, 104 (or referred to as control clocks) may have different respective operating frequencies or may have partially or completely the same operating frequency. Clock source module 10 may be defined as a unit. Therefore, clock source module 10 may also be referred to as clock generation unit 120. The SoC chip 100 may perform various functions in the semiconductor system. For example, soC chip 100 may be an application processor. The SoC may be fabricated as a single chip and may be implemented as a package.
In the example of fig. 1, each subsystem 110, 120, 130, 140 may include various functional blocks for data communication performed in the SoC chip 100, such as a processing unit or processor, a plurality of cores included in the processing unit, a multi-format codec (MFC), a video module (e.g., a camera interface), a Joint Photographic Experts Group (JPEG) processor, a video processor, a mixer (mixer), a 3D image core, an audio system, a driver, a display driver, a volatile memory device, a non-volatile memory, a memory controller, an input and output interface block, and a cache memory. Although the example in fig. 1 shows four subsystems, the number of subsystems may vary depending on the application.
As can be seen in the example of fig. 1, each subsystem 110, 120, 130, 140 requires a separate clock wiring to obtain the respective control clock signal from the common clock source module 10, i.e. so-called centralized clocking. As described above, the above centralized clock control technique involves that each clock wiring needs to be sourced from a common clock source module 10, resulting in an excessively long total clock wiring, affecting clock quality and increasing power consumption. In addition, in the example of fig. 1, a plurality of control clocks, such as the control clocks 101, 102, 103, 104, are collectively output to the respective subsystems 110, 120, 130, 140, thereby increasing the difficulty of wiring, and the problem becomes more prominent particularly in the case where the control clocks 101, 102, 103, 104 are high-speed or have a high frequency. Furthermore, in this case of the above-described centralized clocking shown in fig. 1, each of the plurality of subsystems 110, 120, 130, 140 will typically be turned on simultaneously. When it is desired not to boot a certain subsystem of the plurality of subsystems 110, 120, 130, 140, software may typically be required to control the selection of the certain subsystem (i.e., to control the release of the clock) such that the certain subsystem is not booted, thereby affecting the boot time of the SOC chip 100.
Next, various aspects of the present invention are described in detail with reference to fig. 2 to 7.
FIG. 2 schematically shows a block diagram of an SOC chip 200 according to one embodiment of the invention. Compared to the SOC chip 100 in fig. 1, the SOC chip 200 according to an embodiment of the present invention may include two clock source modules 210, 230, wherein the two clock source modules 210, 230 are cascaded by a low-speed reference clock 211. In other words, the clock source module 210 as the previous stage clock source module can provide the low-speed reference clock 211 to the clock source module 230 as the next clock stage. In one example, the low speed reference clock 211 may, for example, have a frequency in the range of 1MHz to 50MHz, preferably having a frequency of 5, 10, 15, 20, 25, 30, 35, 40, and 45MHz, and so on.
In the embodiment shown in fig. 2, clock source module 210 may output a low-speed reference clock 211 and one or more high- speed control clocks 212, 213, e.g., based on an input reference clock 201. Like the low-speed reference clock 211, the incoming reference clock 201 may also have a frequency in the range of 1MHz to 50MHz, for example, preferably 5, 10, 15, 20, 25, 30, 35, 40, and 45MHz, and so on. According to an example, the input reference clock 201 may originate from, for example, inside the clock source module 210 (not shown in fig. 2) or from outside the SOC chip 200 or from a previous stage clock source module (not shown in fig. 2) within the SOC chip 200, depending on the specific implementation or application. That is, clock source module 210 may act as a primary clock source or may also act as an intermediate clock source.
In contrast, one or more of the high speed control clocks 212, 213 may have a higher frequency than the input reference clock 201 and the low speed reference clock 211, for example, a frequency in the range of 100MHz to 10GHz, preferably 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc. In the example shown in fig. 2, one or more high- speed control clocks 212, 213 may be provided, for example, to subsystem 220 and corresponding interface 222 (optional) associated with clock source module 210 or near or adjacent to clock source module 210. In some embodiments, one or more of the high speed control clocks 212, 213 may have different or the same respective operating frequencies.
In the example of fig. 2, subsystems 220 may be connected to system bus 280, e.g., via respective interfaces 222. Although fig. 2 illustrates the case where subsystem 220 does not include interface 222 and system bus 280, according to other embodiments, subsystem 220 may also be implemented to include at least a portion of interface 222 and system bus 280, or to include functional blocks for providing data over system bus 280 and functional blocks for receiving data over system bus 280. Accordingly, the sub-system 220 according to an example embodiment of the inventive concept may be defined differently.
As described above, the low-speed reference clock 211 may be provided from the clock source module 210 to the clock source module 230 as an input reference clock of the clock source module 230. As further shown in fig. 2, clock source module 230 may output one or more high- speed control clocks 231, 232, e.g., based on an input reference clock 211.
In the example of fig. 2, clock source module 230 may not output any reference clock to any other clock source module 230, i.e., as the last stage clock source. Of course, the clock source module 230 may also provide a low-speed reference clock to the next stage clock source, i.e., act as an intermediate stage clock source, as described further below with reference to fig. 3. Similarly, the one or more high speed control clocks 231, 232 may also have, for example, a frequency in the range of 100MHz to 10GHz, preferably having a frequency of 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc.
In the example of fig. 2, one or more high- speed control clocks 231, 232 may also be provided, for example, to a subsystem 240 associated with clock source module 230 or near or adjacent to clock source module 230 and a corresponding interface 242 (optional). In some embodiments, one or more of the high speed control clocks 231, 232 may also have different or the same respective operating frequencies.
In the example of fig. 2, the subsystems 240 may also be connected to the system bus 280, for example, by corresponding interfaces 242. Although fig. 2 illustrates the case where subsystem 240 does not include interface 242 and system bus 280, according to other embodiments, subsystem 240 may also be implemented to include at least a portion of interface 242 and system bus 280, or to include functional blocks for providing data over system bus 280 and functional blocks for receiving data over system bus 280. Accordingly, the subsystem 240 according to an example embodiment of the inventive concept may also be defined differently.
According to an example of the present invention, the SoC chip 200 shown in fig. 2 may be, for example, a graphics card chip, and the subsystems 220, 240 may each include, for example, at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem.
According to other examples of the invention, the subsystems 220, 240 may also include other various functional blocks such as a processing unit or processor, a plurality of cores included in the processing unit, a multi-format codec (MFC), a video module (e.g., a camera interface), a Joint Photographic Experts Group (JPEG) processor, a video processor, a mixer (mixer), a 3D image core, an audio system, a driver, a display driver, a volatile memory device, a non-volatile memory, a memory controller, an input and output interface block, and a cache memory.
According to other examples of the invention, when SoC chip 200 has a hierarchical bus structure, subsystems 220, 240 may include at least a portion of a local data bus. According to some example embodiments, each of the system bus and the local data bus may be defined as a functional block.
It will be appreciated that a variety of bus-based connection techniques may be used broadly with respect to the system bus 280. For example, with respect to the standard bus specification, the Advanced Microcontroller Bus Architecture (AMBA) protocol of advanced reduced instruction set machine (ARM) may be used. Bus types of the AMBA protocol may include an advanced high performance bus (AHB), an Advanced Peripheral Bus (APB), an advanced extensible interface (AXI), AXI4, and an AXI Coherency Extension (ACE). In the above bus type, AXI is an interface protocol between IPs, and provides a multiple outstanding address function (multi-outstanding address function) and a data interleaving function. In addition, other types of protocols such as open core protocols such as SONICs uNetwork, IBM CoreConnect, OCP-IP may also be used for the system bus.
It is to be appreciated that although two subsystems 220, 240 are shown in fig. 2 and one subsystem 220, 240 is provided with one clock source module 210, 230, respectively, example embodiments of the inventive concepts are not necessarily limited thereto and the number of subsystems 220, 240 may vary depending on the application. For example, clock source modules 210, 230 may each provide a control clock signal to some functional blocks of subsystems 220, 240, or may provide a control clock signal to two or more subsystems 220, 240. Further, each clock source module 210, 230 may provide clock signals having different signal characteristics.
Further, the clock source modules 210, 230 may be implemented as hardware, considering the configuration of the subsystems 220, 240. For example, the internal configuration of clock source modules 210, 230 may be designed in consideration of the characteristics of subsystems 220, 240.
Compared to the single clock source module 10 shown in fig. 1, the scheme shown in fig. 2 involves providing two clock source modules 210 and 230 at different positions of the SOC chip 200, and providing control clocks to their adjacent subsystems respectively, so as to avoid the overlong routing of clocks and the increase of power consumption. Meanwhile, due to the existence of the low-speed reference clock 211 between the clock source modules 210, 230 in fig. 2, the high- speed control clocks 212, 213 and the high- speed control clocks 231, 232 are not aggregated together to be output to the respective subsystems, which facilitates clock wiring. In addition, the cascade connection between the clock source modules 210 and 230 in fig. 2 realizes distributed clock control, for example, the clock source module 210 can control the clock release of the clock source module 230, so as to realize the automation of multi-stage clock release on hardware and accelerate the starting process. Therefore, according to example embodiments of the inventive concepts, the clock source modules 210, 230 are implemented based on the layout and/or configuration of the subsystems 220, 240 in the SOC chip 200, making it possible to manage the clock signals via hardware. Therefore, compared to software-based management, the possibility of occurrence of an error can be reduced and the clock signal can be appropriately turned on and off at a desired point in time, thereby achieving reduction in delay. Further, the Operating System (OS) and firmware for driving the SoC chip 200 do not have to have a complicated routine for turning on and off the clock signal for a plurality of functional blocks, and thus the number of software codes and the load of the CPU can be reduced accordingly.
Fig. 3 schematically shows a block diagram of an SOC chip 300 according to another embodiment of the present invention. Compared to the SOC chip 200 in fig. 2, the SOC chip 300 according to an embodiment of the present invention may include three clock source modules 310, 330, 350, wherein the three clock source modules 310, 330, 350 are cascaded by low-speed reference clocks 311, 333, respectively. In other words, clock source module 310 as the previous stage clock source module can provide low-speed reference clock 311 to clock source module 330 as the next clock stage, and clock source module 330 can provide low-speed reference clock 333 to clock source module 350. In one example, the low speed reference clocks 311, 333 may each have a frequency in the range of 1MHz to 50MHz, for example, preferably having a frequency of 5, 10, 15, 20, 25, 30, 35, 40, and 45MHz, and so on.
In the embodiment shown in fig. 3, clock source module 310 may also output a low-speed reference clock 311 and one or more high- speed control clocks 312, 313, e.g., based on the input reference clock 301. Like the low-speed reference clock 311, the input reference clock 301 may also have a frequency in the range of 1MHz to 50MHz, for example, preferably 5, 10, 15, 20, 25, 30, 35, 40, and 45MHz, and so on. According to an example, the input reference clock 301 may originate, for example, from within clock source module 310 (not shown in fig. 3) or from outside SOC chip 300 or from a previous stage clock source module within SOC chip 300 (not shown in fig. 3), depending on the particular implementation or application.
In contrast, one or more of the high speed control clocks 312, 313 may have a higher frequency than the input reference clock 301 and the low speed reference clock 311, e.g., a frequency in the range of 100MHz to 10GHz, preferably 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc. In the example shown in FIG. 3, one or more high- speed control clocks 312, 313 may be provided, for example, to subsystems 320 and corresponding interfaces 322 (optional) associated with clock source module 310 or near or proximate to clock source module 310. In some embodiments, one or more of the high speed control clocks 312, 313 may have different or the same respective operating frequencies.
In the example of fig. 3, subsystems 320 can be connected to system bus 380, for example, by respective interfaces 322. Although fig. 3 illustrates a case where subsystem 320 does not include interface 322 and system bus 380, according to other embodiments, subsystem 320 may also be implemented to include at least a portion of interface 322 and system bus 380, or to include functional blocks for providing data via system bus 380 and functional blocks for receiving data via system bus 380. Accordingly, the sub-system 320 according to an example embodiment of the inventive concept may be defined differently.
As described above, the low-speed reference clock 311 may be provided from the clock source module 310 to the clock source module 330 as an input reference clock of the clock source module 330. As further shown in fig. 3, the clock source module 330 may output one or more high- speed control clocks 331, 332, e.g., based on the input reference clock 311, and provide a low-speed reference clock 333 to the clock source module 350. In the example of fig. 3, clock source module 330 may act as an intermediate stage clock source. Similarly, the one or more high speed control clocks 331, 332 can, for example, have a frequency in the range of 100MHz to 10GHz, preferably having a frequency of 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc.
In the example of fig. 3, one or more high- speed control clocks 331, 332 may be provided, for example, to a subsystem 340 associated with clock source module 330 or near or adjacent to clock source module 330 and a corresponding interface 342 (optional). In some embodiments, one or more of the high- speed control clocks 331, 332 may also have different or the same respective operating frequencies.
In the example of fig. 3, subsystems 340 may also be connected to system bus 380, e.g., via a corresponding interface 342. Although fig. 3 illustrates the case where subsystem 340 does not include interface 342 and system bus 380, according to other embodiments, subsystem 340 may also be implemented to include at least a portion of interface 342 and system bus 380, or to include functional blocks for providing data over system bus 380 and functional blocks for receiving data over system bus 380. Accordingly, the sub-system 340 according to an example embodiment of the inventive concepts may also be defined differently.
SOC chip 300 in fig. 3 differs from SOC chip 200 in fig. 2 by further including clock source module 350 downstream from clock source module 330 and the associated one or more subsystems 360, 370. As described above, the low-speed reference clock 333 may be provided from the clock source module 330 to the clock source module 350 as an input reference clock of the clock source module 350. As further shown in fig. 3, clock source module 350 may output one or more high speed control clocks 351-354 and provide no low speed reference clocks to other clock source modules, e.g., based on an input reference clock 333. In the example of fig. 3, clock source module 350 may act as the last stage clock source. Similarly, the one or more high speed control clocks 351-354 may also have frequencies in the range of 100MHz to 10GHz, for example, preferably having frequencies of 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc.
In the example of fig. 3, one or more high-speed control clocks 351-354 may also be provided, for example, to subsystems 360, 370 and respective interfaces 362, 372 (optional) associated with clock source module 350 or near or adjacent to clock source module 350. In some embodiments, the one or more high speed control clocks 351-354 may also have different or the same operating frequencies.
In the example of fig. 3, subsystems 360 and 370 may also be connected to system bus 380, for example, by respective interfaces 362 and 372. Although fig. 3 shows a case where subsystems 360, 370 do not include interfaces 362, 372 and system bus 380, according to other embodiments, subsystems 360, 370 may also be implemented to include at least a portion of interfaces 362, 372 and system bus 380, or to include functional blocks for providing data over system bus 380 and functional blocks for receiving data over system bus 380. Accordingly, the subsystems 360, 370 according to example embodiments of the inventive concept may also be defined differently.
According to an example of the present invention, soC chip 300 shown in fig. 3 may be, for example, a graphics card chip, and subsystems 320, 340, 360, 370 may each include, for example, at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem.
According to other examples of the invention, the subsystems 320, 340, 360, 370 may also include other various functional blocks, such as a processing unit or processor, a plurality of cores included in the processing unit, a multi-format codec (MFC), a video module (e.g., a camera interface), a Joint Photographic Experts Group (JPEG) processor, a video processor, a mixer (mixer), a 3D image core, an audio system, drivers, display drivers, volatile memory devices, non-volatile memory, a memory controller, input and output interface blocks, and cache memory.
According to other examples of the invention, when SoC chip 300 has a hierarchical bus structure, subsystems 320, 340, 360, 370 may include at least a portion of a local data bus. According to some example embodiments, each of the system bus and the local data bus may be defined as a functional block.
It will be appreciated that a variety of bus-based connection techniques may be used broadly with respect to system bus 380. For example, with respect to the standard bus specification, the Advanced Microcontroller Bus Architecture (AMBA) protocol of advanced reduced instruction set machine (ARM) may be used. Bus types of the AMBA protocol may include an advanced high performance bus (AHB), an Advanced Peripheral Bus (APB), an advanced extensible interface (AXI), AXI4, and AXI Coherency Extension (ACE). In the above bus type, AXI is an interface protocol between IPs, and provides a multiple outstanding address function (multi-outstanding address function) and a data interleaving function. In addition, other types of protocols such as open core protocols such as SONICs uNetwork, IBM CoreConnect, OCP-IP may also be used for the system bus.
It is to be appreciated that although two subsystems 360, 370 near clock source module 350 and one subsystem 320, 340 near clock source modules 310, 330, respectively, are shown in fig. 3, example embodiments of the inventive concepts are not necessarily limited thereto and the number of subsystems 320, 340, 360, 370 may vary depending on the application. For example, clock source modules 310, 330, 350 may each provide a control clock signal to some functional blocks of the respective subsystem, or may provide a control clock signal to two or more subsystems. Further, each clock source module 310, 330, 350 may provide clock signals having different signal characteristics.
Further, the clock source modules 310, 330, 350 may be implemented as hardware, considering the configuration of the subsystems 320, 340, 360, 370. For example, the internal configuration of clock source modules 310, 330, 350 may be designed in consideration of the characteristics of subsystems 320, 340, 360, 370.
Also, compared to the single clock source module 10 shown in fig. 1, the solution shown in fig. 3 also involves providing three clock source modules 310, 330, 350 at different positions of the SOC chip 300 and respectively providing control clocks to the respective subsystem(s) adjacent thereto, avoiding clock routing too long and power consumption increase. Meanwhile, due to the existence of the low- speed reference clocks 311 and 333 between the clock source modules 310, 330 and 350 in fig. 3, the corresponding high- speed control clocks 312 and 313, the high- speed control clocks 331 and 332 and the high-speed control clocks 351 to 354 are not aggregated together to be output to each subsystem, thereby facilitating clock wiring. In addition, the cascade connection among the clock source modules 310, 330, and 350 in fig. 3 realizes distributed clock control, for example, the clock source module 310 may control the clock release of the clock source module 330, and then the clock source module 330 may control the clock release of the clock source module 350, so as to realize automation of multi-stage clock release on hardware, and accelerate the starting process. Therefore, according to example embodiments of the inventive concepts, the clock source module is implemented based on the layout and/or configuration of the respective subsystems in the SOC chip 300, making it possible to manage the clock signals via hardware. Therefore, compared to software-based management, the possibility of occurrence of an error can be reduced and the clock signal can be appropriately turned on and off at a desired point in time, thereby achieving reduction in delay. Further, the Operating System (OS) and firmware for driving the SoC chip 300 do not have to have a complicated routine for turning on and off the clock signal for a plurality of functional blocks, and thus the number of software codes and the load of the CPU can be reduced accordingly.
Fig. 4 schematically shows a block diagram of an SOC chip 400 according to yet another embodiment of the present invention. Compared to the SOC chip 200 in fig. 2, the SOC chip 400 according to an embodiment of the present invention may include three clock source modules 410, 430, 490, wherein the three clock source modules 410, 430, 490 are cascaded by low-speed reference clocks 411, 414, respectively. In other words, the clock source module 410 as the previous stage clock source module can provide the low-speed reference clock 411 to the clock source module 430 as the next stage clock and provide the low-speed reference clock 414 to the clock source module 490. In one example, the low speed reference clocks 411, 414 may each have a frequency in the range of 1MHz to 50MHz, for example, preferably having a frequency of 5, 10, 15, 20, 25, 30, 35, 40, and 45MHz, and so on.
In the embodiment shown in fig. 4, the clock source module 410 may also output a low-speed reference clock 411 and one or more high-speed control clocks 412, 413, e.g., based on the input reference clock 401. Like the low-speed reference clock 411, the incoming reference clock 401 may also have a frequency in the range of 1MHz to 50MHz, for example, preferably 5, 10, 15, 20, 25, 30, 35, 40, and 45MHz, and so on. According to an example, the input reference clock 401 may originate, for example, from within clock source module 410 (not shown in fig. 4) or from outside SOC chip 400 or from a previous stage clock source module within SOC chip 400 (not shown in fig. 4), depending on the particular implementation or application.
In contrast, one or more of the high speed control clocks 412, 413 may have a higher frequency than the input reference clock 401 and the low speed reference clock 411, for example, a frequency in the range of 100MHz to 10GHz, preferably 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc. In the example shown in fig. 4, one or more high-speed control clocks 412, 413 may be provided, for example, to subsystem 420 and corresponding interface 422 (optional) associated with clock source module 410 or near or adjacent to clock source module 410. In some embodiments, one or more of the high speed control clocks 412, 413 may have different or the same respective operating frequencies.
In the example of fig. 4, subsystems 420 may be connected to system bus 480, for example, by way of corresponding interfaces 422. Although fig. 4 illustrates the case where subsystem 420 does not include interface 422 and system bus 480, according to other embodiments, subsystem 420 may also be implemented to include at least a portion of interface 422 and system bus 480, or to include functional blocks for providing data via system bus 480 and functional blocks for receiving data via system bus 480. Accordingly, the sub-system 420 according to an example embodiment of the inventive concepts may be defined differently.
As described above, the low-speed reference clock 411 may be provided from the clock source module 410 to the clock source module 430 as an input reference clock of the clock source module 430. As further shown in fig. 4, clock source module 430 may output one or more high speed control clocks 431, 432 and provide no low speed reference clock to other clock source modules, e.g., based on an input reference clock 411. In the example of fig. 4, clock source module 430 may act as a last level clock source. Similarly, one or more high speed control clocks 431, 432 may also, for example, have a frequency in the range of 100MHz to 10GHz, preferably having a frequency of 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc.
In the example of fig. 4, one or more high- speed control clocks 431, 432 may also be provided, for example, to a subsystem 440 associated with clock source module 430 or near or adjacent to clock source module 430 and a corresponding interface 442 (optional). In some embodiments, one or more of the high- speed control clocks 431, 432 may also have different or the same respective operating frequencies.
In the example of fig. 4, subsystems 440 may also be connected to system bus 480, for example, by corresponding interfaces 442. Although fig. 4 illustrates the case where the subsystem 440 does not include the interface 442 and the system bus 480, the subsystem 440 may also be implemented to include at least a portion of the interface 442 and the system bus 480, or to include functional blocks for providing data through the system bus 480 and functional blocks for receiving data through the system bus 480, according to other implementations. Accordingly, the sub-system 440 according to an example embodiment of the inventive concept may also be defined differently.
SOC chip 300 in fig. 4 differs from SOC chip 200 in fig. 2 in that it also includes clock source module 490 downstream from clock source module 410 and associated system 496. As described above, the low-speed reference clock 414 may be provided from the clock source module 410 to the clock source module 490 as an input reference clock of the clock source module 490. As further shown in fig. 4, clock source module 490 may output one or more high speed control clocks 491, 492 based on the input reference clock 414, for example, and provide no low speed reference clocks to other clock source modules. In the example of fig. 4, clock source module 490 may act as the last stage clock source. Similarly, one or more of the high speed control clocks 491, 492 may also have a frequency in the range of 100MHz to 10GHz, for example, preferably having a frequency of 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc.
In the example of fig. 4, one or more high- speed control clocks 491, 492 may be provided, for example, to a subsystem 496 associated with clock source module 490 or near or adjacent to clock source module 490 and a corresponding interface 498 (optional). In some embodiments, one or more of the high speed control clocks 491, 492 may also have different respective or the same operating frequencies.
In the example of fig. 4, subsystems 496 may also be connected to system bus 480, e.g., via a corresponding interface 498. Although fig. 4 illustrates the subsystem 496 without the interface 498 and the system bus 480, the subsystem 496 may also be implemented to include at least a portion of the interface 498 and the system bus 480, or to include functional blocks for providing data via the system bus 480 and functional blocks for receiving data via the system bus 480, according to other implementations. Accordingly, the subsystems 496 according to example embodiments of the inventive concept may also be defined differently.
According to an example of the present invention, soC chip 400 shown in fig. 4 may be, for example, a graphics card chip, and subsystems 420, 440, 496 may each include, for example, at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem.
According to other examples of the invention, the subsystems 420, 440, 496 may also include other various functional blocks such as a processing unit or processor, a plurality of cores included in a processing unit, a multi-format codec (MFC), a video module (e.g., a camera interface), a Joint Photographic Experts Group (JPEG) processor, a video processor, a mixer (mixer), a 3D image core, an audio system, drivers, display drivers, volatile memory devices, non-volatile memory, a memory controller, input and output interface blocks, and cache memory.
According to other examples of the invention, when SoC chip 400 has a hierarchical bus structure, subsystems 420, 440, 496 may include at least a portion of a local data bus. According to some example embodiments, each of the system bus and the local data bus may be defined as a functional block.
It will be appreciated that a variety of bus-based connection techniques may be used broadly with respect to the system bus 480. For example, with respect to the standard bus specification, the Advanced Microcontroller Bus Architecture (AMBA) protocol of advanced reduced instruction set machine (ARM) may be used. Bus types of the AMBA protocol may include an advanced high performance bus (AHB), an Advanced Peripheral Bus (APB), an advanced extensible interface (AXI), AXI4, and an AXI Coherency Extension (ACE). In the above bus type, AXI is an interface protocol between IPs, and provides a multiple outstanding address function (multiplex addressing function) and a data interleaving function. In addition, other types of protocols such as the open core protocol of SONICs, uNetwork, IBM CoreConnect, OCP-IP may also be used for the system bus.
It is to be appreciated that although clock source module 410 is shown in fig. 4 as providing a low speed reference clock to two clock source modules 430, 490 (or referred to as slave clock source modules) and one subsystem 420, 440, 496 near clock source modules 410, 430, 490, respectively, example embodiments of the inventive concepts are not necessarily limited thereto and the number of slave clock source modules and the number of subsystems 420, 440, 496 may vary depending on the application. For example, clock source modules 310, 330, 350 may each provide a control clock signal to some functional blocks of the respective subsystem, or may provide a control clock signal to two or more subsystems. Further, each clock source module 310, 330, 350 may provide clock signals having different signal characteristics.
Further, clock source modules 410, 430, 490 may be implemented as hardware, considering the configuration of subsystems 420, 440, 496. For example, the internal configuration of clock source modules 410, 430, 490 may be designed in consideration of the characteristics of subsystems 420, 440, 496.
Also, compared to the single clock source module 10 shown in fig. 1, the solution shown in fig. 4 also involves providing three clock source modules 410, 430, 490 at different locations of the SOC chip 400 and respectively providing control clocks to the respective subsystem(s) adjacent thereto, avoiding clock routing and power consumption increase. Meanwhile, due to the presence of the low-speed reference clocks 411, 414 between the clock source modules 410, 430, 490 in fig. 4, the corresponding high-speed control clocks 412, 413, high- speed control clocks 431, 432, and high- speed control clocks 491, 492 are not clustered together for output to the various subsystems, facilitating clock routing. In addition, the cascade connection among the clock source modules 410, 430, 490 in fig. 4 also implements distributed clock control, for example, the clock source module 410 may control the clock release of the clock source module 430 and the clock source module 490, thereby implementing automation of multi-stage clock release on hardware and speeding up the start process. Therefore, according to example embodiments of the inventive concepts, the clock source module is implemented based on the layout and/or configuration of the respective subsystems in the SOC chip 400, making it possible to manage the clock signals via hardware. Therefore, compared to software-based management, the possibility of occurrence of an error can be reduced and the clock signal can be appropriately turned on and off at a desired point in time, thereby achieving reduction in delay. Further, the Operating System (OS) and firmware for driving the SoC chip 400 do not have to have a complicated routine for turning on and off the clock signal for a plurality of functional blocks, and thus the number of software codes and the load of the CPU can be reduced accordingly.
Fig. 5 schematically shows a block diagram of an SOC chip 500 according to yet another embodiment of the present invention. Compared to the SOC chip 300 in fig. 3, the SOC chip 500 according to an embodiment of the present invention may include four clock source modules 510, 530, 550, 590, wherein the four clock source modules 510, 530, 550, 590 are cascaded by low-speed reference clocks 511, 514, 533, respectively. In other words, the clock source module 510 as the previous stage clock source module can provide the low-speed reference clock 511 to the clock source module 530 as the next clock stage, and provide the low-speed reference clock 514 to the clock source module 590. In one example, the low speed reference clocks 511, 514 may each have a frequency in the range of 1MHz to 50MHz, for example, preferably 5, 10, 15, 20, 25, 30, 35, 40, and 45MHz, and so on.
In the embodiment shown in fig. 5, the clock source module 510 may also output a low-speed reference clock 511 and one or more high- speed control clocks 512, 513, e.g., based on the input reference clock 501. Like the low-speed reference clock 511, the input reference clock 501 may also have a frequency in the range of 1MHz to 50MHz, for example, preferably having a frequency of 5, 10, 15, 20, 25, 30, 35, 40, 45MHz, and so on. According to an example, the input reference clock 501 may originate, for example, from within the clock source module 510 (not shown in fig. 5) or from outside the SOC chip 500 or from a previous stage clock source module within the SOC chip 500 (not shown in fig. 5), depending on the particular implementation or application.
In contrast, one or more of the high speed control clocks 512, 513 may have a higher frequency than the input reference clock 501 and the low speed reference clock 511, for example, a frequency in the range of 100MHz to 10GHz, preferably 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc. In the example shown in fig. 5, one or more high- speed control clocks 512, 513 may be provided, for example, to a subsystem 520 and corresponding interface 522 (optional) associated with clock source module 510 or near or adjacent to clock source module 510. In some embodiments, one or more of the high speed control clocks 512, 513 may have different or the same respective operating frequencies.
In the example of fig. 5, subsystems 520 may be connected to system bus 580, for example, by corresponding interfaces 522. Although fig. 5 illustrates the case where subsystem 520 does not include interface 522 and system bus 580, according to other embodiments, subsystem 520 may also be implemented to include at least a portion of interface 522 and system bus 580, or to include functional blocks for providing data via system bus 580 and functional blocks for receiving data via system bus 580. Accordingly, the sub-system 520 according to an example embodiment of the inventive concept may be defined differently.
As described above, the low-speed reference clock 511 may be provided from the clock source module 510 to the clock source module 530 as an input reference clock of the clock source module 530. As further shown in fig. 5, clock source module 530 may output one or more high- speed control clocks 531, 532, e.g., based on an input reference clock 511, and provide a low-speed reference clock 533 to clock source module 550. In the example of fig. 5, clock source module 530 may act as an intermediate stage clock source and clock source module 550 acts as a final stage clock source. Similarly, the one or more high speed control clocks 531, 532 may also have frequencies in the range of 100MHz to 10GHz, for example, preferably 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc.
In the example of fig. 5, one or more high- speed control clocks 531, 532 may also be provided, for example, to a subsystem 540 associated with clock source module 530 or near or adjacent to clock source module 530 and a corresponding interface 542 (optional). In some embodiments, one or more of the high speed control clocks 531, 532 may also have different or the same respective operating frequencies.
In the example of fig. 5, subsystems 540 may also be connected to system bus 580, for example, by corresponding interfaces 542. Although fig. 5 shows the subsystem 540 without the interface 542 and the system bus 580, the subsystem 540 may also be implemented to include at least a portion of the interface 542 and the system bus 580, or to include functional blocks for providing data over the system bus 580 and functional blocks for receiving data over the system bus 580, according to other embodiments. Accordingly, the subsystem 540 according to an example embodiment of the inventive concept may also be defined differently.
Note that, with regard to clock source module 550 and its corresponding arrangement, reference may be made to clock source module 450 and its corresponding arrangement in fig. 3 above, and further detailed description is omitted here. The same or similar reference numerals refer to the same or similar elements.
SOC chip 500 in fig. 5 differs from SOC chip 300 in fig. 3 in further including clock source module 590 located downstream from clock source module 510 and associated system 596. As described above, the low-speed reference clock 514 can be provided from the clock source module 510 to the clock source module 590 as an input reference clock of the clock source module 590. As further shown in fig. 5, clock source module 590 may output one or more high- speed control clocks 591, 592, e.g., based on input reference clock 514 and no low-speed reference clocks to other clock source modules. In the example of fig. 5, clock source module 590 may act as the last stage clock source. Similarly, one or more of the high- speed control clocks 591, 592 can also, for example, have a frequency in the range of 100MHz to 10GHz, preferably having a frequency of 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc.
In the example of fig. 5, one or more high- speed control clocks 591, 592 may also be provided, for example, to subsystem 596 and corresponding interface 598 (optional) associated with clock source module 590 or near or adjacent to clock source module 590. In some embodiments, one or more of the high- speed control clocks 591, 592 may also have different or the same respective operating frequencies.
In the example of fig. 5, subsystems 596 may also be connected to system bus 580, for example, through a corresponding interface 598. Although fig. 5 illustrates the case where subsystem 596 does not include interface 598 and system bus 580, according to other embodiments, subsystem 596 may also be implemented to include at least a portion of interface 598 and system bus 580, or to include functional blocks for providing data over system bus 580 and functional blocks for receiving data over system bus 580. Therefore, the subsystem 596 according to an exemplary embodiment of the present inventive concept may also be defined differently.
According to an example of the present invention, the SoC chip 500 shown in fig. 5 may be, for example, a graphics card chip, and the subsystems 520, 540, 560, 570, 596 may each include, for example, at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem.
According to other examples of the invention, the subsystems 520, 540, 560, 570, 596 may also include other various functional blocks such as a processing unit or processor, a plurality of cores included in a processing unit, a multi-format codec (MFC), a video module (e.g., a camera interface), a Joint Photographic Experts Group (JPEG) processor, a video processor, a mixer (mixer), a 3D image core, an audio system, drivers, display drivers, volatile memory devices, non-volatile memory, a memory controller, an input and output interface block, and cache memory.
According to other examples of the invention, when SoC chip 500 has a hierarchical bus structure, subsystems 520, 540, 560, 570, 596 may include at least a portion of a local data bus. According to some example embodiments, each of the system bus and the local data bus may be defined as a functional block.
It will be appreciated that a variety of bus-based connection techniques may be used broadly with respect to the system bus 580. For example, with respect to the standard bus specification, the Advanced Microcontroller Bus Architecture (AMBA) protocol of advanced reduced instruction set machine (ARM) may be used. Bus types of the AMBA protocol may include an advanced high performance bus (AHB), an Advanced Peripheral Bus (APB), an advanced extensible interface (AXI), AXI4, and an AXI Coherency Extension (ACE). In the above bus type, AXI is an interface protocol between IPs, and provides a multiple outstanding address function (multiplex addressing function) and a data interleaving function. In addition, other types of protocols such as open core protocols such as SONICs uNetwork, IBM CoreConnect, OCP-IP may also be used for the system bus.
It is to be appreciated that although clock source module 510 is shown in fig. 5 as providing a low-speed reference clock to two clock source modules 530, 590 (or referred to as slave clock source modules) and one or more subsystems 520, 540, 560, 570, 596 near clock source modules 510, 530, 550, 590, respectively, example embodiments of the inventive concepts are not necessarily limited thereto and the number of slave clock source modules and the number of subsystems 520, 540, 560, 570, 596 may vary depending on the application. For example, clock source modules 510, 530, 550, 590 may each provide a control clock signal to some functional blocks of the respective subsystem, or may provide a control clock signal to two or more subsystems. Further, each clock source module 510, 530, 550, 590 may provide clock signals having different signal characteristics.
Further, the clock source module 510, 530, 550, 590 may be implemented as hardware considering the configuration of the subsystems 520, 540, 560, 570, 596. For example, the internal configuration of clock source modules 510, 530, 550, 590 may be designed in consideration of the characteristics of subsystems 520, 540, 560, 570, 596.
Also, compared to the single clock source module 10 shown in fig. 1, the solution shown in fig. 5 also involves providing four clock source modules 510, 530, 550, 590 at different positions of the SOC chip 500 and respectively providing control clocks to the respective sub-system(s) adjacent thereto, avoiding the clock wiring being too long and power consumption being increased. Meanwhile, due to the existence of the low-speed reference clocks 511, 514, 533 between the clock source modules 510, 530, 550, 590 in fig. 5, the corresponding high- speed control clocks 512, 513, high- speed control clocks 531, 532, high-speed control clocks 551 to 554 and high- speed control clocks 591, 592 are not aggregated together to be output to each subsystem, which facilitates clock wiring. In addition, the cascade connection between the clock source modules 510, 530, 550, 590 in fig. 5 also implements distributed clock control, for example, the clock source module 510 may control the clock release of the clock source module 530 and the clock source module 590, and then the clock source module 530 may control the clock release of the clock source module 550, thereby implementing automation of multi-stage clock release on hardware and speeding up the starting process. Therefore, according to example embodiments of the inventive concepts, the clock source module is implemented based on the layout and/or configuration of the respective subsystems in the SOC chip 500, making it possible to manage the clock signals via hardware. Therefore, compared to software-based management, the possibility of occurrence of an error can be reduced and the clock signal can be appropriately turned on and off at a desired point in time, thereby achieving reduction in delay. Further, an Operating System (OS) and firmware for driving the SoC chip 500 do not have to have a complicated routine for turning on and off a clock signal for a plurality of functional blocks, and thus the number of software codes and the load of the CPU can be reduced accordingly.
Although several arrangements of clock source modules in an SOC chip have been described with reference to fig. 2-5, embodiments of the present invention also include other distributions and/or combinations not mentioned in this specification, such as a cascading-by-cascading approach of four clock source modules. As long as there is a cascade of any two clock source modules.
Fig. 6 schematically shows a block diagram of one example of a clock source module 600 in an SOC chip according to one embodiment of the present invention. As shown in fig. 6, clock source module 600 may, for example, include a reference clock 610 external to clock source module 600 and a reference clock 620 internal to clock source module 600 (the latter being optional). According to an example, the external reference clock 610 and the internal reference clock 620 may be generated by, for example, a crystal oscillator or an RC oscillator. According to one example, the frequency of a crystal oscillator or RC oscillator may be generally in the range of 1 to 50MHz. According to other examples, the external reference clock 610 may be, for example, from other clock source signals (e.g., other clock source modules).
As shown in fig. 6, clock source module 600 may further include frequency dividers 621, 624, multiplexers 622, 640, phase-locked loop (PLL) circuit 623, configuration register 630, and low-speed clock signal output 650 and high-speed clock signal output 660. According to one example, phase-locked loop (PLL) circuit 623 may, for example, generate a stable multiplied clock. For example, if the input frequency of the phase-locked loop (PLL) circuit 623 is 16MHz, the output frequency of the phase-locked loop (PLL) circuit 623 can be up to 32MHz, 64MHz, 128MHz, etc. Frequency dividers 621, 624 may, for example, cause the output signal frequency to be an integer fraction of the input signal frequency.
According to the example of fig. 6, multiplexers 622, 640, phase-locked loop (PLL) circuitry 623, frequency divider 624, and configuration register 630 may be used, for example, to generate a high-speed clock signal output 660, forming the control clocks for use by the various subsystems of fig. 2-5. As described above, the high speed clock signal output 660 may, for example, have a frequency in the range of 100MHz to 10GHz, preferably having a frequency of 150MHz, 200MHz, 250MHz, 300MHz, 400MHz, 500MHz, 600MHz, 700MHz, 800MHz, 900MHz, 1GHz, 2GHz, 3GHz, 4GHz, 5GHz, 6GHz, 7GHz, 8GHz, etc.
In contrast, according to the example of fig. 6, the internal reference clock 620, the divider 621, and the configuration register 630 may be used, for example, to generate the low-speed clock signal output 650, or the external reference clock 610 may be used, for example, to generate the low-speed clock signal output 650, thereby forming a low-speed reference clock for use by the various clock source modules in fig. 2-5. As described above, the low speed reference clock 650 may, for example, have a frequency in the range of 1MHz to 50MHz, preferably having a frequency of 5, 10, 15, 20, 25, 30, 35, 40, and 45MHz, etc.
FIG. 7 schematically shows a flow diagram of one example of a method 700 for implementing multi-stage clock release on a SOC chip, according to an embodiment of the invention. As shown in fig. 7, the method for implementing multi-stage clock release on an SOC chip may include steps S710 to S720, and optional steps S701, 730, and S740, where the SOC chip includes a plurality of clock source modules located at different positions. The description above for the SOC chip of fig. 2-5 applies equally to method 700.
Specifically, in step S710, a first control clock (e.g., control clock 512) is provided by a first clock source module (e.g., clock source module 510) of a plurality of clock source modules (e.g., four clock source modules 510, 530, 550, 590 in fig. 5) to a first subsystem (e.g., subsystem 520) associated with the first clock source module (e.g., clock source module 510) based on a first reference clock (e.g., reference clock 501).
In step S720, a first clock source module (e.g. clock source module 510) of a plurality of clock source modules (e.g. four clock source modules 510, 530, 550, 590 in fig. 5) provides a second reference clock (e.g. reference clock 511) to a second clock source module (e.g. clock source module 530) of the plurality of clock source modules different from the first clock source module (e.g. clock source module 510) based on the first reference clock (e.g. reference clock 501), wherein the frequency of the first control clock (e.g. control clock 512) is higher than the frequency of the first reference clock (e.g. reference clock 501) and the second reference clock (e.g. reference clock 511). The description above with respect to fig. 2-5 applies equally to the description in method 700 and will not be described in further detail herein.
In optional step S701, the method 700 may further optionally include: the first reference clock (e.g., reference clock 501) is received from outside the SOC chip (e.g., SOC chip 500) or from inside the first clock source module (e.g., clock source module 510) or from a previous stage clock source module (not shown in fig. 5) within the SOC chip. According to the example of fig. 5, a first reference clock (e.g., reference clock 501) may originate, for example, from within the first clock source module (e.g., clock source module 510) (not shown in fig. 5) or from outside SOC chip 500 or from a previous level clock source module within SOC chip 500 (not shown in fig. 5), depending on the particular implementation or application.
In step S730, the method 700 may further optionally further include: based on the second reference clock (in fig. 4, for example, reference clock 411), a second control clock (for example, control clock 431) is provided from the second clock source module (in fig. 4, for example, clock source module 430) to a second subsystem (in fig. 4, for example, subsystem 440) associated with the second clock source module and no reference clock is provided to any clock source module, wherein the frequency of the second control clock (for example, control clock 431) is higher than the frequency of the second reference clock (in fig. 4, for example, reference clock 411).
In step S740, the method 700 may further optionally include: based on the second reference clock (taking fig. 5 as an example, such as reference clock 511), providing a second control clock (taking fig. 5 as an example, such as control clock 531) from the second clock source module (taking fig. 5 as an example, such as clock source module 530) to a second subsystem (taking fig. 5 as an example, such as subsystem 540) associated with the second clock source module, and providing another reference clock (taking fig. 5 as an example, such as reference clock 533) to another clock source module (taking fig. 5 as an example, such as clock source module 550) of the plurality of clock source modules different from the first clock source module and the second clock source module, wherein the frequency of the second control clock (taking fig. 5 as an example, such as control clock 531) is higher than the frequency of the second reference clock (taking fig. 5 as an example, such as reference clock 511) and the another reference clock (taking fig. 5 as an example, such as reference clock 533).
As described with reference to fig. 2-5, in one example of method 700, the SOC chip may be, for example, a graphics card chip, and the first subsystem and/or the second subsystem may be, for example, selected from at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem. In one example of method 700, each of the first reference clock, the second reference clock, and the another reference clock has a frequency in a range of 1MHz to 50MHz, and each of the first control clock and the second control clock has a frequency in a range of 100MHz to 10 GHz.
Optionally, in addition to the steps shown in fig. 7, according to an embodiment of the present invention, if the second clock source module includes a plurality of clock source modules of the plurality of clock source modules, the method 700 for implementing multi-stage clock release on the SOC chip according to an embodiment of the present invention may further include the following steps (not shown in fig. 7): and respectively providing low-speed reference clocks for the plurality of second clock source modules.
As described above, the present invention improves clock signal management in SOC chips. The invention adopts a distributed clock management system, namely a plurality of clock source modules are respectively arranged at different positions of a chip according to the layout of an SOC chip, wherein the plurality of clock source modules can be cascaded through low-speed reference clocks, and each clock source module outputs a high-speed clock (also called a control clock in the text) to an adjacent subsystem. In this way, the solution according to embodiments of the invention improves the management of the clock signals in the SOC chip and thus improves the overall performance of the SOC chip.
Specifically, a plurality of clock source modules are arranged at different positions of the SOC chip and respectively provide high-speed control clocks for respective sub-systems (one or more) adjacent to the clock source modules, so that the overlong routing of clocks and the increase of power consumption are avoided. Meanwhile, due to the existence of the low-speed reference clocks among the plurality of clock source modules, corresponding high-speed control clocks are not gathered together to be output to each subsystem, and the clock wiring is facilitated. In addition, the cascade connection among a plurality of clock source modules realizes the distributed clock control, thereby realizing the automation of multi-stage clock release on hardware and accelerating the starting process.
As another aspect, the present application also provides a computer-readable medium, which may be contained in the computing device described in the above embodiments; or may exist separately and not be incorporated into the computing device. The computer readable medium carries one or more programs which, when executed by the computing apparatus, cause the computing apparatus to implement the method for implementing multi-level clock release on an SOC chip as in the embodiment shown in fig. 7.
It should be noted that the computer readable medium shown in the present invention can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present invention, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present invention, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described units may also be disposed in a processor. Wherein the names of the elements do not in some way constitute a limitation on the elements themselves.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit according to an embodiment of the invention. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiment of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiment of the present invention.
Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the present disclosure.
Example 1 an SOC chip, comprising: a plurality of clock source modules located at different locations of the SOC chip, wherein a first clock source module of the plurality of clock source modules is configured to: providing a first control clock to a first subsystem associated with the first clock source module based on a first reference clock, and providing a second reference clock to a second clock source module of the plurality of clock source modules different from the first clock source module, wherein a frequency of the first control clock is higher than frequencies of the first reference clock and the second reference clock.
Example 2 the SOC chip according to example 1, wherein the first clock source module is used as a first stage clock source, wherein the first reference clock is located outside the SOC chip or inside the first clock source module.
Example 3 the SOC chip according to example 1, wherein the first clock source module is used as an intermediate-level clock source, wherein the first reference clock is from a third clock source module different from the first clock source module and the second clock source module among the plurality of clock source modules.
Example 4 the SOC chip according to any one of examples 1 to 3, wherein the second clock source module is used as a final stage clock source and is configured to: providing a second control clock to a second subsystem associated with the second clock source module and providing no reference clock to any clock source module based on the second reference clock, wherein the second control clock has a higher frequency than the second reference clock.
Example 5 the SOC chip according to any one of examples 1 to 2, wherein the second clock source module is used as an intermediate-stage clock source and is configured to: providing a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first clock source module and the second clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
Example 6 the SOC chip according to example 3, wherein the second clock source module is used as an additional intermediate stage clock source, and is configured to: providing a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first, second, and third clock source modules, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
Example 7 the SOC chip according to any one of examples 1 to 6, wherein the second clock source module includes one or more of the plurality of clock source modules.
Example 8 the SOC chip of any of examples 1-7, wherein the SOC chip is a graphics card chip, and the first subsystem and/or the second subsystem is selected from at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem.
Example 9 the SOC chip of any of examples 1-8, wherein each of the first reference clock, the second reference clock, and the another reference clock has a frequency in a range of 1MHz to 50MHz, and each of the first control clock and the second control clock has a frequency in a range of 100MHz to 10 GHz.
Example 10 a method for implementing multi-stage clock release on a SOC chip including a plurality of clock source modules located at different locations, the method comprising, by a first clock source module of the plurality of clock source modules, based on a first reference clock: providing a first control clock to a first subsystem associated with the first clock source module and providing a second reference clock to a second clock source module of the plurality of clock source modules different from the first clock source module, wherein a frequency of the first control clock is higher than a frequency of the first reference clock and the second reference clock.
Example 11. The method of example 10, further comprising: receiving the first reference clock from outside the SOC chip or from inside the first clock source module.
Example 12. The method of example 10, further comprising: receiving the first reference clock from a third clock source module of the plurality of clock source modules that is different from the first clock source module and the second clock source module.
Example 13. The method of any of examples 10-12, further comprising: providing a second control clock from the second clock source module to a second subsystem associated with the second clock source module and providing no reference clock to any clock source module based on the second reference clock, wherein the second control clock has a frequency higher than the second reference clock.
Example 14. The method of any of examples 10-11, further comprising: providing, from the second clock source module, a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first clock source module and the second clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
Example 15. The method of example 12, further comprising: providing, from the second clock source module, a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first clock source module, the second clock source module, and the third clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
Example 16 the method of example 10, wherein the second clock source module includes one or more of the plurality of clock source modules.
Example 17. The method of any of examples 10 to 16, wherein the SOC chip is a graphics card chip, and the first subsystem and/or the second subsystem is selected from at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem.
Example 18. The method of any of examples 10 to 17, wherein each of the first reference clock, the second reference clock, and the another reference clock has a frequency in a range of 1MHz to 50MHz, and each of the first control clock and the second control clock has a frequency in a range of 100MHz to 10 GHz.
Example 19. A circuitry comprising the SOC chip of any of claims 1-8.
Example 20 a computer readable medium having stored thereon a computer program which, when executed by a processor, implements a method according to any of examples 1 to 9.
Terms such as "first," "second," and the like, are used to describe various elements, regions, sections, etc., and are not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (16)

1. An SOC chip, comprising:
a plurality of clock source modules located at different locations of the SOC chip,
wherein a first one of the plurality of clock source modules is to: providing a first control clock to a first subsystem associated with the first clock source module and a second reference clock to a second clock source module of the plurality of clock source modules different from the first clock source module based on a first reference clock,
wherein the frequency of the first control clock is higher than the frequency of the first reference clock and the second reference clock.
2. The SOC chip of claim 1, wherein the first clock source module is used as a first stage clock source, wherein the first reference clock is located outside of the SOC chip or inside of the first clock source module.
3. The SOC chip of claim 1, wherein the first clock source module is used as an intermediate level clock source, wherein the first reference clock is from a third clock source module of the plurality of clock source modules that is different from the first clock source module and the second clock source module.
4. The SOC chip of any of claims 1-3, wherein the second clock source module is to serve as a final stage clock source and to: providing a second control clock to a second subsystem associated with the second clock source module and providing no reference clock to any clock source module based on the second reference clock, wherein the second control clock has a higher frequency than the second reference clock.
5. The SOC chip of any of claims 1-2, wherein the second clock source module is to function as an intermediate level clock source and to: providing a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first clock source module and the second clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
6. The SOC chip of claim 3, wherein the second clock source module is used as an additional intermediate stage clock source and is configured to: providing a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first, second, and third clock source modules, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
7. The SOC chip of claim 1, wherein the second clock source module comprises one or more of the plurality of clock source modules.
8. The SOC chip of claim 4, wherein the SOC chip is a graphics card chip, and the first subsystem and/or the second subsystem is selected from at least one of an image rendering subsystem, a video codec subsystem, a display control subsystem, a cache control subsystem, and a system management subsystem.
9. A method for implementing multi-level clock release on a SOC chip, the SOC chip including a plurality of clock source modules located at different locations, the method comprising: by a first clock source module of the plurality of clock source modules, based on a first reference clock:
providing a first control clock to a first subsystem associated with the first clock source module, and
providing a second reference clock to a second one of the plurality of clock source modules different from the first clock source module,
wherein the frequency of the first control clock is higher than the frequency of the first reference clock and the second reference clock.
10. The method of claim 9, further comprising: receiving the first reference clock from outside the SOC chip or from inside the first clock source module.
11. The method of claim 9, further comprising: receiving the first reference clock from a third clock source module of the plurality of clock source modules that is different from the first clock source module and the second clock source module.
12. The method according to any one of claims 9-11, further comprising: providing a second control clock from the second clock source module to a second subsystem associated with the second clock source module and providing no reference clock to any clock source module based on the second reference clock, wherein the second control clock has a frequency higher than the second reference clock.
13. The method according to any one of claims 9-10, further comprising: providing, from the second clock source module, a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another one of the plurality of clock source modules that is different from the first clock source module and the second clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
14. The method of claim 11, further comprising: providing, from the second clock source module, a second control clock to a second subsystem associated with the second clock source module based on the second reference clock, and providing another reference clock to another clock source module of the plurality of clock source modules that is different from the first clock source module, the second clock source module, and the third clock source module, wherein a frequency of the second control clock is higher than frequencies of the second reference clock and the another reference clock.
15. A method according to claim 9 wherein said second clock source module comprises one or more of said plurality of clock source modules.
16. A circuit system comprising the SOC chip according to any one of claims 1 to 8.
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