CN218383770U - Clock circuit, chip, mainboard and computer equipment - Google Patents

Abstract

The embodiment of the application provides a clock circuit, chip, mainboard and computer equipment, and this clock circuit includes: the first off-chip clock input end of the USB module comprises at least two first ports which are interconnected; any first port is connected with a first reference clock signal; the USB module is used for outputting a first clock signal to an internal clock input end of the SATA module and an internal clock input end of the PRG based on the first reference clock signal; the PRG is configured to output a second clock signal to the PCIE module based on the first clock signal. Thus, the number of input reference clocks required can be reduced, thereby reducing the number of clocks required to be provided at the board level, the design complexity of the motherboard, and ultimately the cost.

Description

Clock circuit, chip, mainboard and computer equipment

Technical Field

The present application relates to the field of chip clock technology, and in particular, to a clock circuit, a chip, a motherboard, and a computer device.

Background

As integrated circuit processes develop, more and more Input Output (IO) interfaces are integrated into one chip. The IO interface integrated into one chip includes both a high-speed interface and a low-speed peripheral interface. The IO interfaces have different requirements for the reference clock, and therefore, a System On Chip (SOC) chip or a bridge chip needs to input the reference clock to control the operation timing of each component inside the SOC chip or the bridge chip.

At present, a Universal Serial Bus (USB) physical layer PHY in a clock circuit needs four 12MHz crystal oscillators, which results in a high demand on the number of input reference clocks, further increases the number of clocks required to be provided by a board level, and increases the design complexity and cost of a motherboard.

SUMMERY OF THE UTILITY MODEL

In view of the above problems, the embodiments of the present application are proposed to provide a clock circuit that overcomes the above problems and solves the above problems, so as to reduce the number of required input reference clocks, thereby reducing the number of clocks required to be provided by the board stage, the design complexity of the main board, and ultimately the cost.

In order to solve the above problem, in a first aspect, an embodiment of the present application discloses a clock circuit, including: USB module, SATA module, PRG, PCIE module; the first off-chip clock input end of the USB module comprises at least two first ports which are interconnected; any one of the first ports receives a first reference clock signal; the USB module is used for outputting a first clock signal to an internal clock input end of the SATA module and an internal clock input end of the PRG based on the first reference clock signal;

the PRG is configured to output a second clock signal to the PCIE module based on the first clock signal.

Optionally, the clock circuit further comprises: the system comprises an HT module, a bus controller, a multiplexer and a frequency divider; a second off-chip clock input end and a third off-chip clock input end of the HT module are respectively and correspondingly connected with a second reference clock signal and a third reference clock signal;

the HT module is configured to output a third clock signal to an on-chip clock input terminal of the multiplexer based on the first reference clock signal and/or based on the second reference clock signal;

the second reference clock signal receives an off-chip clock input of the multiplexer; the output end of the multiplexer is connected with the frequency divider; the multiplexer is used for outputting a fourth clock signal to the input end of the frequency divider based on the third clock signal and/or the second reference clock signal;

the output end of the frequency divider is connected with the bus controller; and the frequency divider is used for dividing the frequency of the fourth clock signal and outputting a fifth clock signal to the bus controller.

Optionally, the clock circuit further comprises a GNET module, at least two phase locked loops, and other on-chip modules or controllers; the GNET module is connected with the USB module; the output end of the multiplexer is connected with the at least two phase-locked loops;

the USB module is further used for outputting the first clock signal to a clock signal input end of the GNET module;

the multiplexer is further used for outputting the second clock signal to the at least two phase-locked loops;

each phase-locked loop is used for generating clock signals of different frequency bands to corresponding other on-chip modules or controllers based on the input second clock signals.

Optionally, the bus controller is configured to output, to the outside of the chip, a synchronous clock corresponding to the bus controller in the device to be connected outside the chip.

Optionally, the PRG is further configured to output at least two sixth clock signals off-chip; each sixth clock signal is synchronous with a clock signal corresponding to a PCIE module in the off-chip device to be connected.

Optionally, a third off-chip clock input of the SATA module includes at least two second ports that are interconnected; the SATA module is further configured to receive an input fourth reference clock signal from any of the second ports.

Optionally, the PRG includes a fourth external clock input terminal, and the PRG is further configured to output the second clock signal to the PCIE module based on a fifth reference clock signal input from the fourth external clock input terminal.

In a second aspect, an embodiment of the present application further discloses a chip including the clock circuit described in the first aspect of the embodiment of the present application.

In a third aspect, an embodiment of the present application further provides a motherboard including the chip described in the second aspect of the embodiment of the present application.

In a fourth aspect, an embodiment of the present application additionally provides a computer device, including the control motherboard according to the third aspect of the embodiment of the present application.

The embodiment of the application has the following advantages:

in the embodiment of the application, any first port of the USB module is connected to the third reference clock signal, and due to the interconnection relationship between at least two first ports, each first port is connected to the first reference clock signal when one of the ports is connected to the first reference clock signal. Therefore, the USB module can realize the input of the reference clock signals by a plurality of ports only by one path of external reference clock signal, and does not need four or more paths to realize the input of a plurality of reference clock signals, so that the requirement on the number of the input reference clock signals is reduced, the clock number required to be provided by a board level and the design complexity of a mainboard are further reduced, and the cost is finally reduced.

Drawings

FIG. 1 is a schematic diagram of a clock circuit according to the related art;

fig. 2 is a schematic structural diagram of a clock circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a structure of another clock circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of another clock system according to an embodiment of the present disclosure.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

Currently, the IO Interface Integrated into one chip includes both an I/O Interface of a Peripheral Component Interconnect Express (PCIE), SATA, USB, and a network Interface at a high speed, and an I/O Interface of a Low speed Interface such as a bus controller (LPC), a Serial Peripheral Interface (SPI), a General Purpose Input/Output (GPIO), a Universal Asynchronous Receiver/Transmitter (UART), an I/O Interface of an Integrated Circuit bus (I2C), and the like. The reference clock requirements of the IO interfaces are different, which puts higher requirements on the design of the SOC chip or the bridge chip.

On the one hand, the SOC chip or the bridge itself requires a reference clock input, and in order to reduce the chip cost and increase the ease of use of the chip, the number of input reference clocks needs to be reduced.

On the other hand, in order to simplify the design of the motherboard, reduce the cost of the whole system, and improve the system performance, the clock frequency and the number requirements are defined by some standard interfaces, and in order to support the standard interfaces, the SOC chip or the bridge chip is required to output a clock signal meeting the protocol specification.

Fig. 1 is a schematic diagram of a structure of a clock circuit in the related art, as shown in fig. 1, the clock circuit includes: 5 Phase Locked Loops (PLLs) and 4 clock dividers for generating the respective clock signals required inside the chip.

Where each PLL can provide up to 3 clock output signals. The 5 PLLs are PLL _0 to PLL _4 104; the purposes are respectively as follows:

PLL _0 100 is a PLL of a device for generating a USB/SATA clock signal of 60MHz (megahertz) to 125MHz and a gigabit Access Control (GMAC) clock signal of 125MHz based on an input 100MHz single-ended clock signal; the device can be a USB, SATA or network device; based thereon, the generated USB clock signal may be used to provide a clock signal input to the USB controller, the generated SATA clock signal may be used to provide a clock signal input to the SATA controller, and the generated GMAC clock signal may be used to provide a clock signal input to the gigabit controller.

PLL _1 is a graphics PLL for generating a Graphics Processing Unit (GPU) clock signal of 100MHz to 600MHz, a Display Controller (DC) clock signal of 100MHz to 300MHz, and a video memory clock signal of 400MHz to 667MHz based on an input 100MHz single-ended clock signal;

PLL _1 102 is a system PLL for generating 200MHz-600MHz crossbar switching matrix (XBAR) signals, 24MHz High fidelity Audio (HAD) bitclk signals and 1MHz-100MHz programmable single-ended clock flex clkout signals based on an input 100MHz single-ended clock signal;

PLL _1 and PLL _1 102 and 103 are two pixel PIX PLLs, respectively, for generating two independent pixel clock signals of 10MHz-200MHz based on an input 100MHz single-ended clock signal, respectively, to support two-way independent display.

The clock circuit further includes: 2 dividers DIV2 104 and DIV2 105, a tripler DIV3 106, a quarter DIV4 107;

the DIV2 104 may divide an input 100MHz single-ended clock signal, and input the divided clock signal to the USB controller; the DIV2 105 may divide an input 100MHz single-ended clock signal, and input the divided clock signal into a Serial Peripheral Interface (SPI) and other devices (miscellaneous, MISC), respectively; DIV3 106 can divide the frequency of an input 100MHz single-ended clock signal and output 33MHz CLKOUT33M off-chip for an off-chip device to provide a 33MHz clock signal; DIV4 107 may divide the input 100MHz single-ended clock signal to output 25MHz CLKOUT25M off-chip for the off-chip devices to provide the 25MHz clock signal.

Meanwhile, the 100MHz single-ended clock signal may be directly input to a PHY corresponding to an HT interface (hereinafter referred to as HT PHY), a PHY corresponding to an SATA interface (hereinafter referred to as SATA PHY), and a PHY corresponding to a PCIE interface (hereinafter referred to as PCIE PHY); the corresponding PHY of the LPC interface (hereinafter LPC PHY) is clocked off-chip with a single end at 33 MHz.

It is understood that each of the SATA PHY and the PCIE PHY actually includes 4 independent PHYs; for example, the PCIE PHY includes PCIE _1 sub PHY, PCIE _2 sub PHY, PCIE _3 sub PHY, and PCIE _4 sub PHY.

In this way, in order to improve the reliability of the clock circuit, it is necessary to provide one (2 × 4= 8) differential clock signal of 100MHz for each independent sub-PHY of the SATA PHY and the PCIE PHY.

Further, it is also necessary to provide a 12MHz crystal oscillator for each physical layer of the USB PHY.

In practical applications, the requirements for the input reference clock signal are as follows:

the 1.100MHz single-ended clock signal is used as a reference clock input signal of the chip, and each path of clock signal required in the chip is generated after the PLL;

a 2.100MHz differential clock signal as a reference clock signal for the HT PHY;

a 3.100MHz differential clock signal as a reference clock signal of the SATA PHY;

a 4.100MHz differential clock signal, which is used as a reference clock signal of a PCIE PHY, if a chip includes multiple PCIE PHYs, then multiple reference clock input signals are required; that is, each pcie phy has a reference clock input signal corresponding to it.

A 5.12MHz crystal oscillator that outputs a reference clock signal as the USB PHY;

a 6.33MHz single-ended clock signal as a reference clock signal of the LPC interface;

meanwhile, the chip outputs a plurality of paths of reference clock signals, and can be used by other chips on the mainboard:

1.25MHz single ended clock signal

2.33MHz single ended clock signal

3.100MHz single ended clock signal

4. The programmable single-ended clock (clkoutdlex) signal.

It can be seen that in the related art, multiple reference clock input signals are required, and more requirements are put forward on the design of a mainboard; the output clock signals are single-ended clock signals, which cannot be used by various mainstream interfaces (such as PCIE), and in order to meet these application scenarios, a clock chip meeting requirements needs to be added at a board level, which greatly increases the complexity of the motherboard and increases the circuit cost.

Based on the above technical problem, an embodiment of the present application provides a clock circuit, as shown in fig. 2, the clock circuit includes: the USB module 201, the SATA module 202, the PRG203 and the PCIE module 204; a first off-chip clock input end of the USB module 201 includes at least two first ports that are interconnected;

any one of the first ports receives a first reference clock signal; the USB module 201 is configured to output a first clock signal to an internal clock input terminal of the SATA module 202 and an internal clock input terminal of the PRG203 based on the first reference clock signal;

the PRG203 is configured to output a second clock signal to the PCIE module 204 based on the first clock signal.

It is understood that the USB module 201, the SATA module 202, and the PCIE module 204 include interfaces for interacting with an off-chip device. Illustratively, the USB module 201 includes a USB interface for interaction between the chip and the off-chip device, and similarly, the SATA module 202 includes a SATA interface for interaction between the chip and the off-chip device, and the PCIE module 204 includes a PCIE interface for interaction between the chip and the off-chip device.

In the embodiment of the present application, the USB module includes a USB PHY (i.e., a USB physical layer), and the first port is located on the USB physical layer; any first port of the USB module is connected with the third reference clock signal, and as the first ports are mutually connected, under the condition that one port is connected with the first reference clock signal, each port is connected with the first reference clock signal. Therefore, the USB module only needs one external reference clock signal instead of four or more external reference clock signals, so that the number of the input reference clocks is reduced, the number of clocks required to be provided by the board level and the design complexity of the motherboard are further reduced, and finally the cost is reduced.

Fig. 3 is a schematic diagram of a structure of another clock circuit according to an embodiment of the present disclosure, and as shown in fig. 3, the clock circuit includes: a USB module 301, a SATA module 302, a PRG 303, a PCIE module 304, an HT module 305, an LPC 306, a multiplexer 307, and a frequency divider 308; a first off-chip clock input terminal of the USB module 301 includes at least two first ports that are interconnected;

any first port is connected with a first reference clock signal; the USB module 301 is configured to output a first clock signal to an internal clock input terminal of the SATA module 302 and an internal clock input terminal of the PRG 303 based on the first reference clock signal;

the PRG 303 is configured to output a second clock signal to the PCIE module 304 based on the first clock signal;

the HT module 305 is configured to output a third clock signal to the on-chip clock input terminal of the multiplexer 307 based on the second reference clock signal and/or based on the third reference clock signal;

the second reference clock signal is connected to an off-chip clock input terminal of the multiplexer 307; the output end of the multiplexer 307 is connected with the frequency divider 308; the multiplexer 307, configured to output a fourth clock signal to the input terminal of the frequency divider 308 based on the third clock signal and/or the second reference clock signal;

the output end of the frequency divider 308 is connected with the LPC 306; the frequency divider 308 is configured to divide the frequency of the fourth clock signal and output a fifth clock signal to the LPC 306.

In one possible embodiment, the modules in the HT module 301, the USB module 302, the SATA module 303, and the PCIE module 305 may be configured to control or recover a physical signal external to the chip.

In some possible embodiments, multiplexer 307 may be a two-input single-output multiplexer. For example, the multiplexer 307 may multiplex the clock signal 1 and the clock signal 2 input from the two input terminals together; in the absence of the input clock signal 1, the multiplexer 307 outputs a clock signal 2.

In some possible embodiments, the first reference clock signal may be a 25MHz differential clock signal; the source of the third reference clock signal may be an off-chip clock signal source or generated by another chip. The second reference clock signal may be a 100MHz single ended clock signal; the third reference clock signal may be a differential clock signal of 200MHz or 100 MHz; correspondingly, the signal sources of the second reference clock signal and the third reference clock signal may also be a crystal oscillator or an off-chip clock signal source or other chip generation. Here, it is not particularly limited.

In one possible embodiment, the third clock signal may be a differential clock signal of 100MHz or 200 MHz; the fourth clock signal may be a single-ended clock signal of 100 MHz; the fifth clock signal may be a 33.3MHz single ended clock signal; the first clock signal may be a 25MHz differential clock signal; the second clock signal may be a 100MHz differential clock signal.

In one embodiment, divider 308 may be a divide-by-three divider.

It is understood that the three-frequency divider may divide the frequency of the input clock signal equally into 3-frequency clock signals; for example, a 100MHz clock signal input to the divide-by-three divider will output a 33.3MHz clock signal.

In the embodiment of the present application, multiple kinds of input signal redundancy can be performed on the HT module, so as to improve the reliability of the HT module.

An embodiment of the present application further provides another clock circuit, where the clock circuit includes: the system comprises an HT module, a USB module, an SATA module, a PRG module, a PCIE module, LPC, a multiplexer, a frequency divider, a GNET module connected with the USB module, at least two phase-locked loops connected with the output end of the multiplexer, and other on-chip modules or controllers; a first off-chip clock input end of the USB module comprises at least two first ports which are interconnected; a second off-chip clock input end and a third off-chip clock input end of the HT module are respectively and correspondingly connected with a second reference clock signal and a third reference clock signal;

any first port is connected with a first reference clock signal; the USB module is configured to output a first clock signal to an internal clock input terminal of the SATA module, an internal clock input terminal of the PRG, and a clock signal input terminal of the gigabit ethernet network GNET module based on the first reference clock signal;

the PRG is used for outputting a second clock signal to the PCIE and outputting at least two sixth clock signals to the outside of the chip based on the first clock signal; each sixth clock signal is synchronous with a clock signal corresponding to a PCIE module in the off-chip equipment to be connected;

the HT module is used for outputting a third clock signal to an on-chip clock input end of the multiplexer based on a second reference clock signal and/or a third reference clock signal;

the second reference clock signal is connected with an off-chip clock input end of the multiplexer; the output end of the multiplexer is connected with the frequency divider; the multiplexer is used for outputting a fourth clock signal to the input end of the frequency divider and the at least two phase-locked loops based on the third clock signal and/or the second reference clock signal;

each phase-locked loop is used for generating clock signals of different frequency bands to corresponding other on-chip physical layers or controllers based on the input second clock signals;

the output end of the frequency divider is connected with the LPC; the frequency divider is used for dividing the frequency of the fourth clock and outputting a fifth clock signal to the LPC;

and the LPC is used for outputting a synchronous clock corresponding to the LPC in the equipment to be connected outside the chip to the outside of the chip.

In some embodiments, the sixth clock signal may be a 100MHz differential clock signal; the at least two sixth clock signals may be eight or six sixth clock signals.

It is understood that other on-chip modules may include a High-Definition Multimedia Interface (HDMI) module; other on-chip controllers may include DC, GPU, GMAC, PIX, etc. included in FIG. 1; divisible dividers frescale, rapidIO, etc. not included in fig. 1 may also be included.

In one possible embodiment, the at least two phase-locked loops may be four phase-locked loops; each phase locked loop can output signals of at most three different frequency bands. For example, the at least two phase-locked loops include a first phase-locked loop, which may output clock signals of 100MHz to 400MHz to a DC/Video Processing Unit (VPU), respectively; clock signals of 100MHz-600MHz are sent to a GPU; outputting a clock signal of 0.8GHz-1.2GHz to a graphics memory (GMEM).

It can be seen that, through the USB physical layer, a fourth clock signal may also be provided to the clock signal input terminal of the GNET module, so as to ensure the operation of the GNET physical layer; meanwhile, each phase-locked loop in at least two phase-locked loops generates clock signals of different frequency bands to corresponding other on-chip physical layers or controllers based on the input second clock signals.

Furthermore, the LPC outputs a synchronous clock corresponding to a bus controller module in the device to be connected outside the chip, so that an integrated chip where a clock circuit is located can be directly connected with the bus controller module in the device to be connected, and clock synchronization is well realized;

meanwhile, the output end of the PRG outputs at least two sixth clock signals to the outside of the chip, and each sixth clock signal is synchronous with the clock signal corresponding to the PCIE physical layer in the device to be connected outside the chip, so that the integrated chip where the clock circuit is located can be directly connected with the PCIE PHY in the device to be connected, and the clock synchronization is well realized.

The embodiment of the application provides another clock circuit, which comprises a USB module, an SATA module, a PRG module and a PCIE module; the first off-chip clock input end of the USB module comprises at least two first ports which are interconnected; a third off-chip clock input end of the SATA module comprises at least two second ports which are interconnected; the PRG includes a fourth off-chip clock input;

any first port is connected with a first reference clock signal; the USB module is used for outputting a first clock signal to an internal clock input end of the SATA module and an internal clock input end of the PRG based on the first reference clock signal;

the SATA module is further used for receiving an input fourth reference clock signal from any one of the second ports;

the PRG is used for outputting a second clock signal to the PCIE module based on the first clock signal;

the PRG is further configured to output the second clock signal to the PCIE module based on a fifth reference clock signal input from the fourth off-chip clock input terminal.

In one possible embodiment, the fourth reference clock signal may be a 25MHz differential clock signal; the fifth reference clock signal may be a 100MHz differential clock signal; the fifth clock signal may be a 100MHz differential clock signal.

In some other possible embodiments, the PCIE module may also include a fifth external clock input; correspondingly, the PCIE module may also receive a sixth reference clock signal input by the fifth external clock input terminal. Here, the sixth reference signal clock signal may be a differential clock signal of 156.25 MHz.

In this embodiment, since the third off-chip clock input end of the SATA module includes at least two second ports that are interconnected, each port of the SATA module receives a fourth reference clock when the SATA module receives an input fourth reference clock signal from any of the second ports. Therefore, a clock signal can be input from any second port, the redundancy of the SATA module clock signal is realized, and the reliability of the SATA module clock is improved;

furthermore, the PRG outputs the fifth clock signal to the PCIE module based on the fifth reference clock signal input from the fourth external clock input terminal, so that the clock signal redundancy of the PRG can be realized by the fifth reference clock signal, and the reliability of the PRG clock is improved.

Fig. 3 is a schematic diagram of a structure of another clock circuit according to an embodiment of the present disclosure, and as shown in fig. 3, the circuit includes 5 PLLs and 4 clock dividers as in fig. 1 and 2.

The 5 PLLs are PLL0 400, PLL1& PLL _ ssc 401, PLL2 402, PLL3 403 and PLL4 404, respectively;

the 100MHz single-ended clock is connected with a first input port 1 of the HT PHY and a first input end of the multiplexer MUX; the 200/100MHz differential clock is connected with a second input end of the HT PHY; the output end of the HT PHY is connected with the second input end of the MUX; the output end of the MUX is used as CLKOUT100M output off-chip, and the output end of the MUX is respectively connected with the input ends of PLL0 400, PLL1& PLL _ ssc 401, PLL2 402, PLL3 403, PLL4 404 and DIV 4; DIV4 outputs CLKOUT25M off-chip.

The first output terminal of PLL0 400 outputs the 125MHz clock signal to GMAC and front, which outputs the clock signal to USB2; the second output end of the PLL0 400 outputs a clock signal of 125MHz-250MHz to the USB3/SATA3; a third output of PLL0 400 outputs a clock signal of 250MHz-330MHz to RapidIO.

The first output terminal of the PLL1& PLL _ ssc 401 outputs a clock signal of 100MHz-400MHz to the DC/VPU; a second output terminal of the PLL1& PLL _ ssc 401 outputs a clock signal of 100MHz-600MHz to the GPU; a second output of PLL1& PLL _ ssc 401 outputs GMEM at 0.8GHz-1.2 GHz.

The output end of the PLL3 403 outputs a clock signal of 10MHz-350MHz to the HDMI PHY and the PIX0; the output of the PLL4 404 outputs a 10MHz-350MHz clock signal to the HDMI PHY and PIX1.

A first output terminal of the PLL2 402 outputs a 24MHz clock signal to High fidelity Audio (HDA); a second output end of the PLL2 402 outputs a clock signal of 0.4GHz-1GHz to the XBAR; a third output terminal of PLL2 402 outputs a 1MHz-100MHz clock signal CLKFLEX off-chip.

The clock input end of the USB3PHY is connected with a 25MHz differential clock signal or a crystal oscillator which can output the 25MHz differential clock signal; the USB3PHY outputs 25MHz clock signals to 4 USB2 PHYs, one GMAC PHY, a SATA 3PHY and a PCIE Reference clock Generator (PRG) respectively; SATA3 can also receive the 25MHz difference clock outside the chip; the PRG also receives an off-chip 100MHz differential clock; the PRG outputs a 100MHz clock signal to the PICE _ F0 PHY, the PICE _ F1PHY, the PICE _ H PHY, and the PICE _ G1 PHY.

In contrast to fig. 1, fig. 3 optimizes the input reference clock, see table 1 below.

TABLE 1

From table 1 in conjunction with fig. 3, it can be seen that:

the system reference clock of the bridge chip has two options, one is to select the single-ended input clock SYS _ CLKIN, and the other is to select the differential input clock of the HT PHY.

The HT PHY reference clock has two options: an external 200MHz/100MHz differential input reference clock; the 100MHz single ended input reference clock of the system is used.

Alternatively, when the chip where the clock circuit is located includes 4 PHYs (PICE _ F0 PHY, PICE _ F1PHY, PICE _ H PHY, and PICE _ G1 PHY), they share the internal reference clock. At this time, there are two options for the PCIE PHY reference clock: an external 100MHz differential input (PCIE REFCLKp/n), and a 25MHz reference clock (USB CLKINP/n) for the USB PHY.

The reference clock of the USB PHY has the following two options: externally connecting a 25MHz crystal; and a 25MHz differential input clock is externally connected. The reference clock of the USB PHY is provided to the GNET PHY and the PRG, and is transmitted to the PCIE PHY through the PRG for use, so that the USB PHY reference clock may not be connected to the reference clock only when all modules using the reference clock are not in operation.

The SATA PHY reference clock has two sources: an external 25MHz differential input (SATA CLKINP/n); the 25MHz reference clock of the USB PHY (USB CLKINP/n).

The GMAC PHY reference clock has two sources: a 25MHz reference clock using USB PHY (USB CLKINP/n); the GMAC controller clock generated by internal PLL0 301 is used.

As can be seen from the above description, the embodiments of the present application can be applied to different application scenarios. In a simplest scenario, the scheme of the embodiment of the application may support only SYS _ CLKIN and a 25MHz crystal (USB) as clock inputs, and other clocks including an HT reference clock, a PCIE reference clock, and a SATA reference clock may not be connected as needed. The setting can greatly reduce the requirement on a clock chip during board level design, and reduce the board level design cost and complexity.

In the embodiment of the present application, the output reference clock is shown in table 2 below.

TABLE 2

As can be seen from table 2, the four output clocks CLKOUT33M, CLKOUT100M, CLKOUT25M, and clkoutelflex are identical to those output in fig. 1. However, the following improvements exist in the embodiments of the present application:

1. the LPC clock is changed from input to output, and the chip directly outputs the reference clock to the equipment, so that the board-level clock chip is saved.

2. And outputting the multi-path PCIE differential reference clock. The requirement for a PCIE reference clock is high and is generally generated by a specific clock chip. The scheme also can save a plurality of clock chips by adopting a direct chip output mode.

Besides the advantages, the mode that the chip directly outputs the reference clock can ensure that the chip and the equipment have the same clock source, and is more beneficial to the stable operation of the system.

On the basis of the above embodiments, an embodiment of the present application provides a chip, where the chip includes any one of the clock circuits described above. Wherein the chip comprises an SOC chip and a bridge chip.

The embodiment of the application further provides a mainboard, and the mainboard comprises the chip. The chip can take a circuit board as a carrier, and a processor, a power circuit and the like are fixed on the circuit board in a welding mode to form an expansion mainboard. The motherboard reduces the number of clocks that need to be provided at the board level.

An embodiment of the present application further provides a computer device, where the computer device includes any one of the clock circuit, the chip, or the motherboard. The clock circuit, the chip or the mainboard can be applied to a general computer or an industrial control computer so as to reduce the complexity of clock design and achieve the effect of saving cost.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrases "comprising one of \ 8230; \8230;" does not exclude the presence of additional like elements in a process, method, article, or terminal device that comprises the element.

The clock circuit, the chip, the motherboard and the computer device provided by the present application are introduced in detail, and specific examples are applied herein to explain the principle and the implementation of the present application, and the description of the above embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A clock circuit, comprising: USB module, SATA module, PRG, PCIE module; the first off-chip clock input end of the USB module comprises at least two first ports which are interconnected;

any one of the first ports receives a first reference clock signal; the USB module is used for outputting a first clock signal to an internal clock input end of the SATA module and an internal clock input end of the PRG based on the first reference clock signal;

the PRG is configured to output a second clock signal to the PCIE module based on the first clock signal.

2. The clock circuit of claim 1, further comprising: the system comprises an HT module, a bus controller, a multiplexer and a frequency divider; a second off-chip clock input end and a third off-chip clock input end of the HT module respectively and correspondingly receive a second reference clock signal and a third reference clock signal;

the HT module is configured to output a third clock signal to an on-chip clock input terminal of the multiplexer based on the second reference clock signal and/or based on the third reference clock signal;

the second reference clock signal is connected with an off-chip clock input end of the multiplexer; the output end of the multiplexer is connected with the frequency divider; the multiplexer is used for outputting a fourth clock signal to the input end of the frequency divider based on the third clock signal and/or the second reference clock signal;

the output end of the frequency divider is connected with the bus controller; and the frequency divider is used for dividing the frequency of the fourth clock signal and outputting a fifth clock signal to the bus controller.

3. The clock circuit of claim 2, further comprising a GNET module, at least two phase locked loops, and other on-chip modules or controllers; the GNET module is connected with the USB module; the output end of the multiplexer is connected with the at least two phase-locked loops;

the USB module is further used for outputting the first clock signal to a clock signal input end of the GNET module;

the multiplexer is further configured to output the fourth clock signal to the at least two phase-locked loops;

each phase-locked loop is used for generating clock signals of different frequency bands to corresponding other on-chip modules or controllers based on the input fourth clock signal.

4. The clock circuit according to claim 2, wherein the bus controller is configured to output a synchronous clock corresponding to the bus controller in the off-chip device to be connected to the off-chip device.

5. The clock circuit of claim 1 or 2, wherein the PRG is further configured to output at least two sixth clock signals off-chip; each sixth clock signal is synchronous with a clock signal corresponding to a PCIE module in the off-chip device to be connected.

6. The clock circuit of claim 1 or 2, wherein the third off-chip clock input of the SATA module comprises at least two second ports interconnected; the SATA module is further configured to receive an input fourth reference clock signal from any of the second ports.

7. The clock circuit of claim 1 or 2, wherein the PRG comprises a fourth off-chip clock input, and wherein the PRG is further configured to output the second clock signal to the PCIE module based on a fifth reference clock signal input from the fourth off-chip clock input.

8. A chip comprising a clock circuit as claimed in any one of claims 1 to 7.

9. A motherboard comprising the chip of claim 8.

10. A computer device, characterized in that it comprises a motherboard as claimed in claim 9.

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