CN116415442A - Simulation system, simulation method, and simulation device - Google Patents

Simulation system, simulation method, and simulation device Download PDF

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Publication number
CN116415442A
CN116415442A CN202310436363.9A CN202310436363A CN116415442A CN 116415442 A CN116415442 A CN 116415442A CN 202310436363 A CN202310436363 A CN 202310436363A CN 116415442 A CN116415442 A CN 116415442A
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module
interface
simulation
clock
fpgas
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韩彬
周建文
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Beijing Eswin Computing Technology Co Ltd
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Beijing Eswin Computing Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The embodiment of the disclosure provides a simulation system, a simulation method, simulation equipment and a computer storage medium. Wherein, the emulation system includes: at least two field-editable logic gate arrays (FPGAs) and a clock control module, wherein the FPGAs comprise asynchronous transmission interfaces; the clock control module is connected with each FPGA and is configured to synchronously provide a unified clock signal for the asynchronous transmission interfaces of each FPGA so as to synchronize communication processes between different FPGAs through the asynchronous transmission interfaces.

Description

Simulation system, simulation method, and simulation device
Technical Field
The disclosure relates to the technical field of display, in particular to a simulation system, a simulation method and simulation equipment.
Background
The development process of the System On Chip (SOC) is most important to verify the environment, and verification of the register transfer level (Register Transfer Level, RTL) often consumes a long period due to the limitation of the number and performance of the servers and the thread running mechanism of the CPU itself. In order to accelerate RTL front-end verification, hardware accelerator and field programmable gate array (Field Programmable Gate Array, FPGA) prototype verification are two means of RTL verification acceleration commonly used in the industry, and the latter can lead software layout driving and firmware to accelerate product development and marketing in advance.
Disclosure of Invention
The embodiment of the disclosure provides a simulation system, a simulation method and simulation equipment.
In a first aspect, embodiments of the present disclosure provide a simulation system, comprising: at least two field-editable logic gate arrays (FPGAs) and a clock control module, wherein the FPGAs comprise asynchronous transmission interfaces;
the clock control module is connected with each FPGA and is configured to synchronously provide a unified clock signal for the asynchronous transmission interfaces of each FPGA so as to synchronize communication processes between different FPGAs through the asynchronous transmission interfaces.
In some embodiments, the asynchronous transfer interface comprises: serDes interface.
In some embodiments, the FPGA further comprises: a simulation function module configured to perform a function simulation;
the SerDes interface includes: a data conversion module and an interface module;
the data conversion module is configured to convert the first parallel data sent by the simulation function module into first serial data and send the first serial data to the interface module; and the simulation function module is further configured to convert the second serial data sent by the interface module into second parallel data and send the second parallel data to the simulation function module;
the interface module is configured to send the third serial data sent by the data conversion module to interface modules of other FPGAs; and the data conversion module is also configured to send fourth serial data sent by the interface modules of other FPGAs to the data conversion module.
In some embodiments, the unified clock signal comprises: a reference clock and a parallel clock;
the clock control module is specifically configured to provide the reference clock to the interface module, so that the interface module provides a corresponding fast clock to the data conversion module according to the reference clock.
In some embodiments, the frequency of the parallel clock is less than or equal to 50MHz.
In a second aspect, an embodiment of the present disclosure provides a simulation method applied to the simulation system provided in the first aspect, where the method includes:
and according to the unified clock signals provided by the clock control module to the asynchronous transmission interfaces of the FPGAs synchronously, the synchronous communication process between different FPGAs is carried out through the asynchronous transmission interfaces.
In some embodiments, the asynchronous transfer interface comprises: serDes interface.
In some embodiments, the FPGA further comprises: a simulation function module configured to perform a function simulation; the SerDes interface includes: a data conversion module and an interface module;
the method further comprises the steps of:
the data conversion module converts the first parallel data sent by the simulation function module into first serial data and sends the first serial data to the interface module;
the data conversion module converts the second serial data sent by the interface module into second parallel data and sends the second parallel data to the simulation functional module;
the interface module sends the third serial data sent by the data conversion module to interface modules of other FPGAs;
and the interface module sends fourth serial data sent by the interface modules of other FPGAs to the data conversion module.
In some embodiments, the unified clock signal comprises: a reference clock and a parallel clock;
the step of synchronously providing a unified clock signal to the asynchronous transmission interfaces of each FPGA according to the clock control module to enable synchronous communication processes between different FPGAs through the asynchronous transmission interfaces comprises the following steps:
and synchronizing the reference clocks provided to the interface modules of the FPGAs according to the clock control module, so that the interface modules provide corresponding fast clocks to the data conversion modules according to the reference clocks.
In some embodiments, the parallel clock has a frequency less than or equal to 50MHz.
In a third aspect, an embodiment of the present disclosure provides an emulation apparatus, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory in communication via the bus when the computer device is running, the machine-readable instructions when executed by the processor performing the steps of the simulation method as provided in the second aspect.
In a fourth aspect, embodiments of the present disclosure provide a computer non-transitory readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the simulation method as provided in the second aspect.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
fig. 1 is a schematic structural diagram of a simulation system according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a simulation device provided in an embodiment of the present disclosure.
Fig. 3 is a schematic structural view of a computer non-transitory readable storage medium provided in an embodiment of the present disclosure.
Detailed Description
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
FPGA prototype verification is already the dominant and mature chip verification method of current prototype verification, which verifies the functions of ASIC by migrating RTL to Field Programmable Gate Array (FPGA), and after the basic function verification of chip passes, the development of driver can be started, and the development of driver and application can be performed until the chip product is finalized (Tape Out) and back-sliced. After the chip is reworked, the application program can be directly used for simple adaptation based on the drive of the FPGA version, namely, the method can be applied to an SOC chip, and the Time control of the SOC chip product on the Market (Time-to-mark) is perfect.
However, for large-scale SOC chip front-end verification, one FPGA often cannot be accommodated, and multiple FPGAs must be interconnected to verify the entire design, in which case the large-scale design needs to be partitioned (Partition). Segmentation introduces new problems that do not exist in the chip, and many times take much effort to implement a usable segmentation scheme, limited only by the capacity of the FPGA and not the way it has to be handled. The biggest problem introduced by segmentation is that the demand for I/O is rapidly increased, although the FPGA has more than 1000 available I/Os, if a complete SoC is split into a plurality of parts with comparable scale, the number of interconnection signals between each part is often far more than 1000, so when the number of I/Os is limited, time division multiplexing (Time Division Multiplex, TDM) is needed, namely, a plurality of parallel signals in the FPGA are converted into high-speed serial signals, transmitted to another FPGA through FPGAI/O, then demultiplexed and converted into parallel signals, and the signals are transferred from one FPGA to another FPGA.
In the related art, the FPGA with larger scale is Ultrascale+device VU19P which is pushed out by Xilinx, is a TSMC 16nm process, the scale of the FPGA is 4 times that of the prior generation VU440, the power consumption and PR algorithm are greatly optimized, and the FPGA adopted by the HAPS 100 of Synopsys is VU19P, but the scale of the FPGA is still insufficient to bear the ultra-large scale SOC chip resources.
In response to the above problems, the problem can be solved by a proto compiler provided by Synopsys and a high-speed time division multiplexing (High Statistical Time Division Multiplexing, HSTDM) synchronous segmentation technique. After the ProtoCompiler software is screened, a signal parallel-to-serial circuit is automatically added in the design, and after the signal parallel-to-serial circuit is transmitted at a high speed through the inter-FPGA chip LVDS at a 1.6G difference, the signal transmitted by the FPGA1 is obtained through serial conversion at the opposite-end FPGA, so that the inter-chip interconnection is realized.
Specifically, the interconnection between FPGAs can be achieved through a parallel transmission interface of system synchronization or source synchronization, but as the interface frequency increases, the following several factors limit the continuous increase of the effective data window width: the propagation delay of the clock to the two chips is unequal; propagation delays of bits (bits) of parallel data are not equal; the propagation delay of the clock is inconsistent with the propagation delay of the data. Although the clock delay difference can be compensated by using the phase-locked loop circuit, the amount of change in the clock delay and the amount of change in the data delay are different when PVT (Process, voltage, temperature) is changed, which results in an even more disadvantageous increase in the width of the data window. In summary, the bandwidth of the synchronous transmission interface in the interconnection between FPGA chips is limited.
Thus, while introducing HSTDM solves the I/O bottleneck, the multiplexer Mux and demultiplexer De-Mux introduce additional delay, resulting in a Path (Path) across the FPGA (Cross-FPGA) being a Critical Path (Critical Path), further reducing the operational frequency of the FPGA. On the other hand, since the module is often increased or decreased in SOC prototype verification, frequent modification of the segmentation scheme is required, and since the segmentation logic selects a specific port, the timing is not well converged.
In order to solve at least one of the above technical problems, an embodiment of the present disclosure provides a simulation system, so that synchronous communication processes between different FPGAs are implemented through an asynchronous transmission interface.
Fig. 1 is a schematic structural diagram of a simulation system according to an embodiment of the present disclosure, where, as shown in fig. 1, the simulation system includes at least two field-editable logic gate arrays FPGAs and a clock control module 3.
Wherein the FPGA comprises an asynchronous transmission interface; the clock control module 3 is connected with each FPGA, and the clock control module 3 is configured to synchronously provide a unified clock signal for the asynchronous transmission interfaces of each FPGA so as to synchronize the communication processes between different FPGAs through the asynchronous transmission interfaces.
In view of the fact that the bandwidth of the synchronous transmission interface in interconnection between the FPGA chips is limited, in the embodiment of the present disclosure, the FPGA is provided with the asynchronous transmission interface, and in order to ensure consistency of each FPGA chip in the simulation system, the simulation system provided in the embodiment of the present disclosure further includes a clock control module, which generates clock signals required by all FPGA chips in the simulation system through a unified clock generation mechanism, so that clocks of all FPGA chips are kept synchronous, and further when the simulation system is applied to FPGA prototype verification, the SOC chips can still maintain an original synchronous relationship after being logically divided into a plurality of FPGA chips.
In some embodiments, the asynchronous transfer interface comprises: serDes interface 2.
It should be understood that SerDes (Serializer-Deserializer) is an acronym for Serializer and Deserializer, where the Serializer may be the transmitting end in SerDes interface 2 and the Deserializer may be the receiving end in SerDes interface 2.
In some embodiments, as shown in fig. 1, the FPGA further comprises: a simulation function module 1 configured to perform a function simulation; the SerDes interface 2 includes: a data conversion module 21 and an interface module 22.
The data conversion module 21 is configured to convert the first parallel data sent by the simulation function module 1 into first serial data, and send the first serial data to the interface module 22; and is further configured to convert the second serial data sent by the interface module 22 into second parallel data and send the second parallel data to the simulation function module 1; the interface module 22 is configured to send the third serial data sent by the data conversion module 21 to the interface modules 22 of other FPGAs; and is further configured to send fourth serial data sent by the interface module 22 of the other FPGA to the data conversion module 21.
In particular, the interaction between the emulation functional module 1 and the SerDes interface 2 is mainly the cut data signal and the clock of the data signal.
When the SerDes interface 2 is used as a transmitting end, the interface module 22 mainly synchronizes the data of the user clock to the SerDes clock, so that the accuracy of data acquisition is ensured. Firstly, a differential signal of a user clock is generated through a clock control module 3 to generate a synchronous signal of data, then the user data signal is beaten by a SerDes clock to reduce metastable state of sampling the data signal, and finally stable data can be obtained by sampling the user data at rising edge and falling edge of the data signal. And, the data conversion module 21 may be used for parallel-serial conversion, for example, a 64bit RAW interface is adopted, parallel data is sent out in a fast clock frequency and dual-edge serial data format, and finally, stability of data transmission between boards is ensured by a single-end-to-differential mode, so as to realize parallel input of wider data signals.
When the SerDes interface 2 is used as a receiving end, the interface module 22 uses the SerDes clock to splice the data of the user, and the frequency of the SerDes clock is 64 times of the frequency of the user clock, so that the data of the user reaches a stable state before the rising edge of the user clock, and the user clock is directly used for sampling without data synchronization. Meanwhile, the data conversion module 21 may be used for serial-to-parallel conversion, which also adopts a 64bit RAW interface, and the serial-to-parallel conversion sub-module and the parallel-to-serial conversion sub-module are operated in a reverse direction, which is used for recovering serial and double-edge data after delay into parallel single-edge data.
In some embodiments, the unified clock signal generated by the clock control module 3 comprises: a reference clock and a parallel clock; the clock control module 3 is specifically configured to provide a reference clock to the interface module 22, for the interface module 22 to provide a corresponding fast clock to the data conversion module 21 according to the reference clock.
Specifically, the clock control module 3 mainly provides a slow clock and a differential reference clock for data transmission of the SerDes interface 2, so that the SerDes interface 2 generates a fast clock based on clock multiplication determined by the slow clock, and transmits parallel data at the frequency of the fast clock.
In some embodiments, the frequency of the parallel clock provided by the clock control module is less than or equal to 50MHz.
In one example, the communication bandwidth of the SerDes interface 2 is 37.5GBPS, and the clock emulating the data signal in the functional module 1 tends to be constrained by the transmission delay of the SerDes. According to the SerDes loop performance test of the FPGA, the communication delay of the SerDes in the standard mode is 27ns, and the unidirectional transmission delay is about 14ns; in addition, considering ns-level delay on interconnection lines between different FPGAs and the establishment period of receiving data by the opposite-end FPGAs, the overall delay of unidirectional data transmission is within 20ns, and at this time, the clock frequency of the corresponding data signal can be operated at 50Hz.
Based on this, the frequency of the parallel clock provided by the clock control module 3 is less than or equal to 50MHz, and the delay of the slow clock is greater than or equal to 20ns. At this time, the delay of the data signal covers the communication clock delay of the SerDes interface 2, so as to synchronize the throughput of the SerDes interface 2, avoid the phenomenon of frequency offset, and finally realize the synchronization of the communication processes among different FPGAs.
Table 1 shows the number of interconnected I/os that a SerDes interface provided in an embodiment of the present disclosure can carry under different data signal clocks. In one example, on the premise that the communication bandwidth of the SerDes interface is 37.5GBPS and the clock frequency of the data signals in the simulation data module is 50MHz, the number of parallel interconnection I/Os which can be set on the FPGA is 750, and on the premise that 80 SerDes interfaces can be integrated on the FPGA chip, the total number of extensible interconnection I/Os is 60000. Similarly, on the premise that the communication bandwidth of the SerDes interface is 37.5GBPS and the clock frequency of the data signals in the simulation data module is 10MHz, the number of parallel interconnection I/Os which can be set on the FPGA is 3750, and on the premise that 80 SerDes interfaces can be integrated on the FPGA chip, the total number of extensible interconnection I/Os is 30 ten thousand. When the clock frequency of the data signals in the simulation data module is 20MHz, the number of the expandable interconnection I/O on the FPGA chip integrated with 80 SerDes interfaces is 15 ten thousand; when the clock frequency of the data signals in the simulation data module is 5MHz, the number of the expandable interconnection I/O integrated with 80 SerDes interfaces on the FPGA chip is 60 ten thousand; when the clock frequency of the data signals in the simulation data module is 1MHz, the number of the expandable interconnection I/O integrated with 80 SerDes interfaces on the FPGA chip is 30 ten thousand.
TABLE 1
Bandwidth frequency 50MHz 20MHz 10MHz 5MHz 1MHz
Number of interconnected I/O 60000 15 ten thousand (ten thousand) 30 ten thousand 60 ten thousand (60) 30 ten thousand
In the related art, a Low-voltage differential signaling terminal (Low-Voltage Differential Signaling, LVDS) can be adopted between two FPGAs in an FPGA prototype verification platform to realize synchronous transmission, and related data indicates that on the premise that a data signal clock is 10MHz, the LVDS interface can only make 80 interconnection I/O lines, and even if 1000 LVDS single-ended interfaces are arranged, the quantity of interconnection I/Os which can be carried is 80000. Compared with the FPGA inter-chip interconnection segmentation scheme which can be realized by the SEDRES interface provided by the embodiment of the disclosure, the method has a huge gap.
In summary, in the simulation system provided by the embodiment of the present disclosure, an asynchronous transmission interface, i.e., a SerDes interface, is provided on an FPGA, so that the number of wires of hardware can be reduced, fewer chip pins are used, meanwhile, the I/O bottleneck brought by the TDM technology is solved, and the throughput of the SerDes interface is synchronized by controlling an external clock source signal, so that the synchronization of the communication processes between different FPGAs is further realized.
Based on the same inventive concept, the embodiments of the present disclosure further provide a simulation method, which is applied to the simulation system, and the method includes:
and according to the unified clock signals provided by the clock control module to the asynchronous transmission interfaces of the FPGAs, the synchronous communication process between different FPGAs is carried out through the asynchronous transmission interfaces.
In some embodiments, the unified clock signal comprises: a reference clock and a parallel clock; providing a unified clock signal for the asynchronous transmission interfaces of all FPGAs according to the synchronization of the clock control module, so that the synchronous communication process between different FPGAs is carried out through the asynchronous transmission interfaces, comprising the following steps:
the reference clocks provided to the interface modules 22 of each FPGA are synchronized according to the clock control module, so that the interface modules 22 provide the corresponding fast clocks to the data conversion module 21 according to the reference clocks.
The principle of the problem solved by the simulation method in the embodiments of the present disclosure is similar to that of the problem solved by the simulation system in the embodiments of the present disclosure, and will not be described herein.
Fig. 2 is a schematic structural diagram of an emulation device provided in an embodiment of the present disclosure, and as shown in fig. 2, the emulation device 100 includes: a memory 101, a processor 102 and a bus 103, the memory 101 having stored thereon a computer program, wherein the computer program when executed by the processor 102 implements the simulation method described above. The processor 102 communicates with the memory 101 via a bus 103 such that the processor 102 executes the execution instructions mentioned in the method embodiments above. Wherein the processor 102 may employ FPGA chips within the simulation system provided in embodiments of the present disclosure.
Furthermore, the simulation equipment can reduce the number of hardware wires and use fewer chip pins by arranging an asynchronous transmission interface, namely a SerDes interface, on the FPGA, meanwhile, the I/O bottleneck brought by the TDM technology is solved, the throughput of the SerDes interface is synchronized by controlling an external clock source signal, and the synchronization of communication processes among different FPGAs is further realized.
The simulation device 100 may be a computing device such as a desktop computer, a notebook computer, a palm computer, and a cloud server. The emulation device 100 may include, but is not limited to, a processor 102 and a memory 101. It will be appreciated by those skilled in the art that fig. 2 is merely an example of the emulation device 100 and does not constitute a limitation of the emulation device 100, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the emulation device 100 may further include an input-output device, a network access device.
The processor 102 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. The general purpose processor 102 may be a microprocessor or the processor may be any conventional processor or the like.
The memory 101 may be an internal storage unit of the emulation device 100, such as a hard disk or a memory of the emulation device 100. The memory 101 may also be an external storage device of the emulation device 100, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the emulation device 100. Further, the memory 101 may also include both an internal memory unit and an external memory device of the emulation device 100. The memory 101 is used for storing the computer program as well as other programs and data required by the terminal device. The memory 101 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
Fig. 3 is a schematic structural diagram of a computer non-transitory readable storage medium provided in an embodiment of the disclosure, as shown in fig. 3, a computer program 201 is stored on the computer readable storage medium 200, where the computer program 201 implements the above simulation method when executed by a processor. Computer-readable storage media 200 includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims (10)

1. A simulation system, the simulation system comprising: at least two field-editable logic gate arrays (FPGAs) and a clock control module, wherein the FPGAs comprise asynchronous transmission interfaces;
the clock control module is connected with each FPGA and is configured to synchronously provide a unified clock signal for the asynchronous transmission interfaces of each FPGA so as to synchronize communication processes between different FPGAs through the asynchronous transmission interfaces.
2. The emulation system of claim 1, wherein the asynchronous transfer interface comprises: serDes interface.
3. The simulation system of claim 2 wherein the FPGA further comprises: a simulation function module configured to perform a function simulation;
the SerDes interface includes: a data conversion module and an interface module;
the data conversion module is configured to convert the first parallel data sent by the simulation function module into first serial data and send the first serial data to the interface module; and the simulation function module is further configured to convert the second serial data sent by the interface module into second parallel data and send the second parallel data to the simulation function module;
the interface module is configured to send the third serial data sent by the data conversion module to interface modules of other FPGAs; and the data conversion module is also configured to send fourth serial data sent by the interface modules of other FPGAs to the data conversion module.
4. A simulation system according to claim 3, wherein the unified clock signal comprises: a reference clock and a parallel clock;
the clock control module is specifically configured to provide the reference clock to the interface module, so that the interface module provides a corresponding fast clock to the data conversion module according to the reference clock.
5. The simulation system of claim 4, wherein the frequency of the parallel clock is less than or equal to 50MHz.
6. A simulation method applied to the simulation system of any one of claims 1 to 5, the method comprising:
and according to the unified clock signals provided by the clock control module to the asynchronous transmission interfaces of the FPGAs synchronously, the synchronous communication process between different FPGAs is carried out through the asynchronous transmission interfaces.
7. The emulation method of claim 6, wherein the asynchronous transfer interface comprises: serDes interface.
8. The simulation method of claim 7, wherein the FPGA further comprises: a simulation function module configured to perform a function simulation; the SerDes interface includes: a data conversion module and an interface module;
the method further comprises the steps of:
the data conversion module converts the first parallel data sent by the simulation function module into first serial data and sends the first serial data to the interface module;
the data conversion module converts the second serial data sent by the interface module into second parallel data and sends the second parallel data to the simulation functional module;
the interface module sends the third serial data sent by the data conversion module to interface modules of other FPGAs;
and the interface module sends fourth serial data sent by the interface modules of other FPGAs to the data conversion module.
9. The simulation method according to claim 8, wherein the unified clock signal includes: a reference clock and a parallel clock;
the step of synchronously providing a unified clock signal to the asynchronous transmission interfaces of each FPGA according to the clock control module to enable synchronous communication processes between different FPGAs through the asynchronous transmission interfaces comprises the following steps:
and synchronizing the reference clocks provided to the interface modules of the FPGAs according to the clock control module, so that the interface modules provide corresponding fast clocks to the data conversion modules according to the reference clocks.
10. An emulation apparatus, comprising: a processor, a memory and a bus, said memory storing machine readable instructions executable by said processor, said processor and said memory communicating over the bus when the computer device is running, said machine readable instructions when executed by said processor performing the steps of the simulation method according to any of claims 6-9.
CN202310436363.9A 2023-04-21 2023-04-21 Simulation system, simulation method, and simulation device Pending CN116415442A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117217142A (en) * 2023-09-13 2023-12-12 沐曦集成电路(上海)有限公司 Chip joint simulation method based on time division multiplexing, electronic equipment and medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117217142A (en) * 2023-09-13 2023-12-12 沐曦集成电路(上海)有限公司 Chip joint simulation method based on time division multiplexing, electronic equipment and medium
CN117217142B (en) * 2023-09-13 2024-04-19 沐曦集成电路(上海)有限公司 Chip joint simulation method based on time division multiplexing, electronic equipment and medium

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