CN115422100A - Direct memory access control device, data transmission method and data transmission system - Google Patents

Abstract

The application relates to the field of integrated circuits, and relates to a direct memory access control device, a data transmission method and a data transmission system, wherein the direct memory access control device comprises a direct memory access controller and a microcontroller, the direct memory access controller is connected with a system bus, and the system bus is also connected with a main controller; and the microcontroller is used for controlling the direct memory access controller to carry out data transmission according to an operation instruction configured by the main controller so as to replace the main controller when the direct memory access controller is required to carry out data transmission. Therefore, the microcontroller replaces the main controller to control the direct memory access controller, the problem that the main controller is often required to participate in the data transmission process of the direct memory access controller is solved, and the working efficiency of the system is improved.

Description

Direct memory access control device, data transmission method and data transmission system

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a direct memory access control device, a data transmission method, and a data transmission system.

Background

A Direct Memory Access (DMA) controller is an interface circuit that allows hardware devices of different speeds to communicate with each other without relying on a large interrupt load on the host controller. In the data transmission process of the DMA controller, the main controller is not required to directly control data transmission, so that the main controller can process other processes and can perform parallel operation with the data transmission process, and therefore, the performance of the whole system can be improved by transmitting data through the DMA controller.

However, in the process of data transmission by the DMA controller, the DMA controller has a large occupation demand on the main controller, for example, the main controller is often required to update the descriptor table, which reduces the efficiency of the main controller and further reduces the working efficiency of the system. In addition, for the functions that cannot be realized by the DMA controller, the control right of the system bus needs to be handed over to the host controller, and after the host controller completes the functions, the control right of the system bus needs to be handed over to the DMA controller.

Therefore, how to improve the working efficiency of the system becomes an urgent problem to be solved.

Disclosure of Invention

The microcontroller controls the direct memory access controller to carry out data transmission according to an operation instruction configured by the main controller, so that the microcontroller replaces the main controller to control the direct memory access controller, the problem that the main controller is often required to participate in the data transmission process of the direct memory access controller is solved, and the working efficiency of the system is improved.

In a first aspect, the present application provides a direct memory access control apparatus, including a direct memory access controller and a microcontroller, where the direct memory access controller is connected to a system bus, and the system bus is further connected to a main controller;

and the microcontroller is used for controlling the direct memory access controller to carry out data transmission according to the operation instruction configured by the main controller so as to replace the main controller when the direct memory access controller is required to carry out data transmission.

In a second aspect, the present application further provides a data transmission method applied in the above direct memory access control apparatus, where the method includes:

when the direct memory access controller is required to be used for data transmission, the microcontroller acquires an operation instruction configured by the main controller;

and the microcontroller controls the direct memory access controller to transmit data according to the operation instruction configured by the main controller.

In a third aspect, the present application further provides a data transmission system, where the data transmission system includes a main controller and the above direct memory access control device, and the main controller is integrated on the direct memory access control device, or the main controller is disposed outside the direct memory access control device.

The application discloses a direct memory access control device, a data transmission method and a data transmission system, wherein the direct memory access control device comprises a direct memory access controller and a microcontroller, the direct memory access controller is connected with a system bus, and the system bus is also connected with a main controller; and the microcontroller is used for controlling the direct memory access controller to carry out data transmission according to an operation instruction configured by the main controller so as to replace the main controller when the direct memory access controller is required to carry out data transmission. According to the embodiment of the application, the microcontroller controls the direct memory access controller to carry out data transmission according to the operation instruction configured by the main controller, the microcontroller can replace the main controller to control the direct memory access controller, the problem that the main controller is often required to participate in the data transmission process of the direct memory access controller is solved, resources of the main controller do not need to be occupied, and the working efficiency of the system is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a data transmission system provided in an embodiment of the present application;

fig. 2 is a schematic diagram of another data transmission system provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of another data transmission system provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of another data transmission system provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of another data transmission system provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of another data transmission system provided in the embodiment of the present application;

fig. 7 is a schematic flow chart of a data transmission method provided in an embodiment of the present application;

FIG. 8 is a schematic flow chart diagram illustrating sub-steps of a data transmission provided in an embodiment of the present application;

fig. 9 is a schematic flow chart of another data transmission method provided in the embodiment of the present application;

fig. 10 is a schematic flow chart of another data transmission method provided in the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The flowcharts shown in the figures are illustrative only and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution order may be changed according to the actual situation.

It is to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The embodiment of the application provides a direct memory access control device, a data transmission method and a data transmission system. The data transmission method is applied to a direct memory access control device, and the direct memory access control device comprises a direct memory access controller and a microcontroller. In the embodiment of the application, the microcontroller controls the direct memory access controller to carry out data transmission according to the operation instruction configured by the main controller, so that the microcontroller replaces the main controller to control the direct memory access controller, the problem that the main controller is often required to participate in the data transmission process of the direct memory access controller is solved, and the working efficiency of the system is improved.

Illustratively, the host controller may include, but is not limited to, a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an ARM (Advanced RISC Machine) processor, an Application Specific Integrated Circuit (ASIC), and a Field Programmable Gate Array (FPGA), among others. In the embodiment of the application, the main controller is used for controlling the dma controller to transfer the operation instruction pre-configured by the main controller to the first storage of the microcontroller, and starting the microcontroller, and the microcontroller controls the dma controller to transmit data according to the operation instruction, so that the microcontroller replaces the main controller to control the dma controller to transmit data.

It should be noted that the microcontroller may be a microprocessor built in the dma controller, and the function of the microcontroller is similar to that of the main controller, and the microcontroller has instruction capability and strong expandability, and can replace the main controller to complete functions that cannot be realized by the dma controller; at the same time, the microcontroller occupies very few resources and can operate at a higher frequency.

Referring to fig. 1, fig. 1 is a schematic diagram of a data transmission system 10 according to an embodiment of the present application. As shown in fig. 1, the data transmission system 10 includes a main controller 11 and a dma controller 12, both the main controller 11 and the dma controller 12 are connected to a system bus, wherein the dma controller 12 includes a dma controller 120 and a microcontroller 121.

By way of example, the System Bus may include, but is not limited to, an Advanced System Bus (ASB), an Advanced Peripheral Bus (APB), an Advanced High-performance Bus (AHB), and an Advanced Trace Bus (ATB).

The data transmission System 10 may be, for example, a SoC (System on a Chip) System, a SiP (System In a Package) System, or other types of systems, such as a Field Programmable Gate Array (FPGA) heterogeneous System. In the embodiment of the present application, how to transmit data will be described by taking the data transmission system 10 as an example of a system on chip.

Specifically, the microcontroller 121 is configured to control the dma controller 120 to perform data transmission according to an operation instruction configured by the host controller 11 to replace the host controller 11 when data transmission by the dma controller 120 is required.

For example, the host controller 11 may be integrated with the dma controller 12, and the host controller 11 may be disposed outside the dma controller 12.

Referring to fig. 2, fig. 2 is a schematic diagram of another data transmission system 10 according to an embodiment of the present disclosure. As shown in fig. 2, the microcontroller 121 includes a first memory 1210, and the first memory 1210 is used for storing operation instructions configured by the main controller 11.

The operation instruction includes an operation instruction pre-configured by the main controller 11, and is stored in a memory corresponding to the main controller 11, for example, in the second memory 13, and the operation instruction can be called and executed by the microcontroller 12. Of course, the operation instruction may also be stored in the first storage 1210 of the microcontroller 12 in advance, and the microcontroller 12 may directly read and execute the operation instruction in the first storage 1210 after being started, so that the direct memory access controller 120 is not required to transfer the operation instruction in the second storage 13 to the first storage 1210, thereby saving system resources.

In an embodiment of the application, the operation instruction includes at least a first instruction. For example, the first instruction may be a data transfer instruction for controlling the dma controller 120 to perform data transfer.

In some embodiments, the microcontroller 121 is configured to read and execute a first instruction from the first storage 1210 to control the dma controller 120 to perform data transmission.

By reading and executing the first instruction from the first memory 1210 by the microcontroller 121, the microcontroller 121 can control the dma controller 120 to transmit data instead of the main controller 11, without occupying resources of the main controller 11, thereby improving the working efficiency of the system.

In this embodiment, the operation instruction may further include a second instruction, and the second instruction is an instruction for operating the dma controller 120. Illustratively, the second instruction may include one or more of a wait instruction, a query instruction, a pointer jump instruction, an access instruction, and a stop instruction.

In some embodiments, the microcontroller 121 is configured to execute the second instruction, so as to replace the main controller 11 to complete the operation corresponding to the second instruction.

Illustratively, the microcontroller 121 is configured to execute the second instruction, and may obtain a control right of the system bus, and complete an operation corresponding to the second instruction by calling the system bus.

By executing the second instruction by the microcontroller 121 instead of the main controller 11 to complete the operation corresponding to the second instruction, the microcontroller 121 can acquire the control right of the system bus to complete the operation corresponding to the second instruction during the data transmission of the dma controller 120, without repeatedly handing over the control right of the system bus to the main controller 11, thereby solving the problem of low system working efficiency caused by repeatedly handing over the control right of the system bus to the main controller 11.

As shown in fig. 2, the memory access control device 12 further includes a second storage 13, the second storage 13 is connected to the system bus, and the second storage 13 is used for storing the operation instruction.

In some embodiments, the dma controller 120 is further configured to transfer the operation instructions to the first storage 1210.

In the embodiment of the present application, the dma controller 120 may be connected to the host controller 11 through a system bus, and the host controller 11 may control the dma controller 120 to transfer the operation instructions in the second storage 13 to the first storage 1210.

As shown in fig. 2, the second storage 13 may be disposed outside the direct memory access control device 12, but it is understood that the second storage 13 may also be disposed in the direct memory access control device 12.

In the embodiment of the present application, the operation instruction in the second storage 13 is carried to the first storage 1210 in the microcontroller 121 by the dma controller 120, and the microcontroller 121 executes the operation instruction, so that the microcontroller 121 can replace the main controller 11 to control the dma controller 120 to transmit data, the problem that the main controller 11 is often required to participate in the process of transmitting data by the dma controller 120 is solved, the resource of the main controller 11 does not need to be occupied, and the working efficiency of the system is improved.

Referring to fig. 3, fig. 3 is a schematic diagram of another data transmission system 10 according to an embodiment of the present application. As shown in fig. 3, the second storage 13 may be integrated on the direct memory access control device 12. Of course, the host controller 11 may also be integrated with the dma controller 12.

In one embodiment, as shown in fig. 3, the dma control apparatus 12 further includes a format conversion module 122, where the format conversion module 122 is configured to perform format conversion on the operation instruction to obtain target data, and a data format of the target data matches a data format required by the first storage 1210.

The format conversion module 122 may be a separate module in the dma controller 12, may be integrated on the dma controller 120, and of course, may be integrated on the microcontroller 121.

Illustratively, the format conversion module 122 is an independent module, when the dma controller 120 carries the operation command to the first storage 1210 of the microcontroller 121, the dma controller 120 first sends the operation command to the format conversion module 122, the format conversion module 122 performs format conversion on the operation command to obtain the target data, and the format conversion module 122 then carries the target data to the first storage 1210 of the microcontroller 121.

For example, the format conversion module 122 is a module integrated on the microcontroller 121, and the dma controller 120 can transfer the operation instruction to the microcontroller 121, perform format conversion on the operation instruction by the format conversion module 122 in the microcontroller 121 to obtain the target data, and then transfer the target data to the first storage 1210.

For example, the format of the target data may be a string format, an array format, a json format, or the like.

By arranging the format conversion module 122, the format conversion module 122 is used for converting the format of the operation instruction to obtain the target data, the data format of the target data is ensured to be matched with the data format required by the first memory 1210, and the situation that the microcontroller 121 cannot identify the data in the first memory 1210 can be avoided.

In one embodiment, as shown in fig. 4, the dma controller 12 further includes an arbiter 123, the microcontroller 121 is connected to the system bus through the arbiter 123, and the main controller 11 is connected to the system bus through the arbiter 123. The dma controller 12 includes a first control path and a second control path for controlling the dma controller 120, wherein the first control path is that the microcontroller 121 accesses the dma controller 120 through the arbiter 123 and the system bus, and the second control path is that the main controller 11 accesses the dma controller 120 through the arbiter 123 and the system bus.

In the embodiment of the present application, the arbiter 123 is configured to: when receiving the commands sent by the main controller 11 and the microcontroller 121 at the same time, the commands of the main controller 11 are processed with priority.

For example, when the arbiter 123 receives the instructions sent by the main controller 11 and the microcontroller 121 at the same time, the arbiter 123 may process the instructions of the main controller 11 preferentially and then the instructions of the microcontroller 121.

By setting the arbiter 123 to process the instruction of the main controller 11 preferentially, it is achieved that the main controller 11 can be accessed at any time when the microcontroller 121 controls the dma controller 120 to perform data transmission, and the working efficiency of the main controller 11 can be ensured.

In one embodiment, as shown in fig. 5, the external device 14 is further connected to the system bus, and the main controller 11 and the microcontroller 121 can access the external device 14 through the system bus; the dma controller 120 may perform data transmission with the external device 14 through the system bus, for example, the dma controller 120 may transmit data in the memory inside the system on chip to the external device 14 through the system bus, or may transmit data stored in the external device 14 to the memory inside the system on chip through the system bus. The memory inside the system on chip may be the first memory 1210, the second memory 13, or another memory, which is not limited herein.

In the embodiment of the present application, as shown in fig. 1 to 5, the main controller 11 may send a start instruction to the dma controller 120 through the system bus to start the dma controller 120; after the dma controller 120 is started, the host controller 11 may send a command transfer request to the dma controller 120 via the system bus, so that the dma controller 120 transfers the operation commands in the second memory 13 to the first memory 1210 of the microcontroller 121 according to the command transfer request. The command transfer request is used to instruct the dma controller 120 to transfer the operation command in the second storage 13.

The pre-transfer of the microcontroller 121 into the first memory 1210 of the microcontroller 121 instead of the instructions executed by the main controller 11 can be realized by sending an instruction transfer request from the main controller 11 to the dma controller 120.

Illustratively, when receiving an instruction carrying request sent by the host controller 11, the dma controller 120 sends a first bus occupation request to the host controller 11 according to the instruction carrying request, where the first bus occupation request is used to request the host controller 11 to switch the dma controller 120 from the slave operating state to the host operating state; after entering the host operating state, the dma controller 120 transfers the operating commands in the second memory 13 to the first memory 1210 in the microcontroller 121 via the system bus.

The slave operation state is that the dma controller 120 is a slave of the system bus before obtaining the control right of the system bus, cannot control the system bus, and is controlled by the master controller 11. In this operating state, the main controller 11 can write various parameters and instructions required for data transmission into various registers of the dma controller 120 to control the transmission process, and can also read the registers to obtain the state of the dma controller 120. The host operating state means that after the control right of the bus is obtained and data transmission is started, the dma controller 120 is used as a host of the system bus, and can independently control the system bus, start the whole process of controlling data transfer according to the information configured by the host controller 11, and abandon the control right of the system bus until the transmission is completed.

In some embodiments, as shown in fig. 6, the microcontroller 121 is connected to the main controller 11, and the microcontroller 121 is configured to receive a start instruction of the main controller 11 and start according to the start instruction to execute the first instruction. The microcontroller 121 may be connected to the main controller 11 through a system bus, and the microcontroller 121 may also be connected to the main controller 11 through a preset signal line.

For example, as shown in fig. 6, the main controller 11 may send a start instruction to the microcontroller 121 through a preset signal line to start the microcontroller 121. In addition, the main controller 11 may also send a boot instruction to a boot register in the microcontroller 121 through the system bus to activate the boot register, thereby enabling the microcontroller 121 to boot. Wherein the enable register may be a predefined register for enabling the microcontroller 121.

It should be noted that, in the embodiment of the present application, the host controller may first start the dma controller 120 and then start the microcontroller 121, and of course, the host controller may first start the microcontroller 121 and then start the dma controller 120. The microcontroller 121 is activated by sending an activation instruction from the host controller 11 to the microcontroller 121, so that the control right of the host controller 11 to the dma controller 120 can be handed over to the microcontroller 121, and the dma controller 120 is controlled by the microcontroller 121 to perform data transmission.

When the first command is a data transfer command, the microcontroller 121 executes the data transfer command to control the dma controller 120 to perform data transfer. Specifically, the microcontroller 121 may send a data transmission request to the dma controller 120 through the system bus, and the dma controller 120 sends a second bus occupation request to the microcontroller 121 according to the data transmission request; the microcontroller 121 controls the dma controller 120 to enter the host operating state from the slave operating state according to the second bus occupation request; after entering the host operating state, the dma controller 120 performs data transmission via the system bus.

The microcontroller 121 may first send a data transmission request to the arbiter 123, and the arbiter 123 sends the data transmission request to the dma controller 120 through the system bus.

For example, the data transfer modes of the dma controller 120 may include a peripheral-to-memory mode, a memory-to-peripheral mode, and a memory-to-memory mode. Wherein, the peripheral-to-memory mode refers to transmitting data in the external device to an internal memory of the system on chip; the memory-to-peripheral mode refers to transmitting data in an internal memory of the system on chip to an external device; the memory-to-memory mode refers to transferring data in a first internal memory of the system-on-chip to a second internal memory of the system-on-chip.

Illustratively, the direct memory access controller 120 may include a data buffer register; when the dma controller 120 performs data transmission, the dma controller obtains data from a source address through a system bus and stores the data in a data buffer register; the dma controller 120 then sends the data in the data buffer to the target address via the system bus.

It should be noted that, when the data transmission mode is the peripheral to memory mode, the source address is an address of the external device 14 for storing data, and the destination address is an address of the internal memory for storing data; when the data transfer mode is the memory-to-peripheral mode, the source address is an address where data is stored in the internal memory, and the destination address is an address where data is stored in the external device 14.

In some embodiments, when the operation instruction includes a second instruction, the microcontroller 121 is configured to execute the second instruction, instead of the main controller 11 completing an operation corresponding to the second instruction.

It should be noted that the second instruction is an instruction that cannot be executed by the dma controller 120; the second instruction is originally executed by the main controller 11, and in the embodiment of the present application, by transferring the second instruction to the first storage 1210 of the microcontroller 121, the microcontroller 121 can replace the main controller 11 to complete the operation corresponding to the second instruction, and further, during the data transmission of the dma controller 120, the control right of the system bus does not need to be repeatedly handed over to the main controller 11, thereby solving the problem of low working efficiency of the system caused by the need of repeatedly handing over the control right of the system bus to the main controller 11.

For example, the microcontroller 121 may read the second instructions in the first memory 1210 in a time sequence.

For example, when the second instruction is a wait instruction, the microcontroller 121 performs a wait operation.

For another example, when the second instruction is an access instruction, the microcontroller 121 performs an access operation. The access instruction may include a peripheral access instruction, and of course, may also be other types of access instructions. For example, when the access command is a peripheral access command, the microcontroller 121 executes the peripheral access command to access the external device through the system bus.

In some embodiments, when the microcontroller 121 receives the instruction of the main controller 11, the microcontroller 121 preferentially executes the instruction of the main controller 11. For example, when a stop instruction of the main controller 11 is received, the microcontroller 121 stops operating. By the microcontroller 121 preferentially executing the instruction sent by the main controller 11, the main controller 11 can control the microcontroller 121 at any time during the period that the microcontroller 121 controls the dma controller 120 to transmit data, thereby ensuring the control right of the main controller 11.

The dma controller 12 provided in the foregoing embodiment reads and executes the first instruction from the first storage 1210 through the microcontroller 121, so that the microcontroller 121 can replace the main controller 11 to control the dma controller 120 to transmit data, and resources of the main controller 11 do not need to be occupied, thereby improving the working efficiency of the system; by executing the second instruction by the microcontroller 121 instead of the main controller 11 to complete the operation corresponding to the second instruction, the microcontroller 121 can acquire the control right of the system bus to complete the operation corresponding to the second instruction during the data transmission of the dma controller 120, and the control right of the system bus does not need to be repeatedly handed over to the main controller 11, thereby solving the problem of low working efficiency of the system caused by the need of repeatedly handing over the control right of the system bus to the main controller 11; by arranging the format conversion module, the format conversion module 122 is used for converting the format of the operation instruction to obtain target data, the data format of the target data is ensured to be matched with the data format required by the first memory 1210, and the situation that the microcontroller 121 cannot identify the data in the first memory 1210 can be avoided; by setting the arbiter 123 to process the instruction of the main controller 11 preferentially, it is achieved that the main controller 11 can be accessed at any time when the microcontroller 121 controls the dma controller 120 to perform data transmission, and the working efficiency of the main controller 11 can be ensured.

Referring to fig. 7, fig. 7 is a schematic flowchart of a data transmission method according to an embodiment of the present application. The data transmission method can be applied to the direct memory access control device provided by the embodiment, and can realize that the microcontroller replaces the main controller to control the direct memory access controller to transmit data without occupying resources of the main controller, thereby improving the working efficiency of the system.

As shown in fig. 7, the data transmission method includes step S201 and step S202.

Step S201, when data transmission needs to be performed by using the dma controller, the microcontroller acquires an operation instruction configured by the main controller.

It should be noted that, when data transmission needs to be performed by using the dma controller, the external device requests to transmit data to the memory, or requests to transmit data from the memory to the memory of the external device; of course, the host controller on the soc may transmit data in the memory to the external device, or transmit data from the external device to the memory.

For example, the microcontroller may read instructions stored in a first memory in the microcontroller when obtaining operating instructions configured by the host controller. The instructions stored in the first memory are pre-configured and stored in the second memory by the main controller, and the main controller controls the direct memory access controller to transfer from the second memory to the first memory.

Illustratively, the operation instruction may include a first instruction and a second instruction, where the first instruction may be a data transfer instruction, and the first instruction is used to control the dma controller to perform data transfer; the second instruction is an instruction for operating the DMA controller, and is used for the microcontroller to replace the main controller to execute corresponding operation.

The microcontroller acquires the operation instruction configured by the main controller, and subsequently, the microcontroller can control the direct memory access controller to transmit data according to the operation instruction.

Step S202, the microcontroller controls the direct memory access controller to transmit data according to the operation instruction configured by the main controller.

For example, the microcontroller may control the dma controller to perform data transfer according to the data transfer instruction. In the embodiment of the present application, a detailed description will be given of controlling the dma controller to perform data transfer.

Referring to fig. 8, fig. 8 is a schematic flow chart of a data transmission sub-step according to an embodiment of the present application, which may specifically include the following steps S2021 to S2023.

Step S2021, the microcontroller sends a data transmission request to the dma controller, and the dma controller sends a bus occupation request to the microcontroller according to the data transmission request.

For example, the microcontroller may send a data transmission request to the dma controller via the system bus, and the dma controller sends a bus occupation request to the microcontroller according to the data transmission request. The microcontroller may send the data transmission request to the arbiter first, and the arbiter sends the data transmission request to the dma controller through the system bus.

Step S2022, the microcontroller controls the dma controller to enter the host operating state from the slave operating state according to the bus occupation request.

For example, the microcontroller may grant the controller of the system bus to the dma controller, so that the dma controller can independently control the system bus to start transmitting data.

Step S2023, after the dma controller enters the host operating state, performing data transmission through the system bus.

For example, the dma controller may transfer data via the system bus based on different data transfer modes. The data transfer mode may include a peripheral-to-memory mode, a memory-to-peripheral mode, and a memory-to-memory mode, among others.

For example, the dma controller may transfer data in the external device to the internal memory of the system on chip through the system bus. For another example, the dma controller may transmit data in the internal memory of the system on chip to an external device through the system bus.

In the data transmission method provided by the embodiment, the microcontroller acquires the operation instruction configured by the main controller, and subsequently, the microcontroller can control the direct memory access controller to transmit data according to the operation instruction; the microcontroller sends a data transmission request to the direct memory access controller, so that the microcontroller replaces the main controller to control the direct memory access controller to transmit data, the problem that the main controller is often required to participate in the data transmission process of the direct memory access controller is solved, the resources of the main controller are not required to be occupied, and the working efficiency of the system is improved.

Referring to fig. 9, fig. 9 is a diagram of another data transmission method according to an embodiment of the present application, including step S203 and step S204.

In step S203, the dma controller transfers the operation command in the second storage to the first storage of the microcontroller, where the operation command at least includes the first command.

In the embodiment of the application, the main controller can send a starting instruction to the direct memory access controller through the system bus so as to start the direct memory access controller; after the dma controller is started, the host controller may send an instruction transfer request to the dma controller through the system bus, so that the dma controller transfers the operation instruction in the second storage to the first storage of the microcontroller according to the instruction transfer request.

It should be noted that the main controller may start the dma controller first and then start the microcontroller, and of course, the main controller may start the microcontroller first and then start the dma controller.

Illustratively, when receiving an instruction carrying request sent by a main controller, a direct memory access controller sends a bus occupation request to the main controller according to the instruction carrying request, wherein the bus occupation request is used for requesting the main controller to switch the working state of the direct memory access controller from a slave machine working state to a host machine working state; and after the direct memory access controller enters the working state of the host, the operating instruction in the second memory is carried to the first memory in the microcontroller through the system bus.

The operation instruction includes at least a first instruction, where the first instruction may be a data transfer instruction, and the first instruction is used to control the dma controller to perform data transfer.

By carrying the operation instruction in the second memory to the first memory in the microcontroller by the dma controller, the subsequent microcontroller can execute the first instruction to control the dma controller to perform data transmission.

And step S204, the microcontroller reads the first instruction from the first memory and executes the first instruction.

In the embodiment of the present application, after the dma controller carries the operation command in the second storage to the first storage of the microcontroller, if the microcontroller is not started, the main controller needs to start the microcontroller, so that the microcontroller executes the first command.

It should be noted that the main controller may send an activation instruction to the microcontroller through a preset signal line, so as to activate the microcontroller. In addition, the main controller can also send a start instruction to a start register in the microcontroller through the system bus to activate the start register, so that the microcontroller is started. Wherein the start register may be a predefined register for starting the microcontroller.

Illustratively, when the first instruction is a data transfer instruction, the microcontroller executes the data transfer instruction to control the dma controller to perform data transfer.

The microcontroller replaces the main controller to control the controller to transmit data by executing the data transmission instruction, so that the resources of the main controller are not occupied, and the working efficiency of the system is improved.

In some embodiments, the data transmission method provided in the embodiments of the present application may further include: the microcontroller executes the second instruction to replace the main controller to finish the operation corresponding to the second instruction.

It should be noted that, in the embodiment of the present application, the operation instruction may include a second instruction in addition to the first instruction. The second instruction is an instruction for operating the DMA controller, and is used for the microcontroller to perform corresponding operations instead of the main controller. Wherein the second instruction may include one or more of a wait instruction, a query instruction, a pointer jump instruction, an access instruction, and a stop instruction.

Illustratively, the microcontroller performs a wait operation when the second instruction is a wait instruction.

Illustratively, the microcontroller performs the access operation when the second instruction is an access instruction. The access instruction may include a peripheral access instruction, and of course, may also be another type of access instruction. For example, when the access instruction includes a peripheral access instruction, the microcontroller executes the peripheral access instruction to access the external device through the system bus.

It should be noted that the second instruction is an instruction that cannot be executed by the dma controller; in the embodiment of the present application, the microcontroller executes the second instruction instead of the main controller to complete the operation corresponding to the second instruction, so that the control right of the system bus does not need to be repeatedly handed over to the main controller during the data transmission of the dma controller, and the problem of low working efficiency of the system caused by the need of repeatedly handing over the control right of the system bus to the main controller is solved.

For example, the microcontroller may read each second instruction in the first memory in time sequence.

For example, when the second instruction is a wait instruction, the microcontroller performs a wait operation. For another example, when the second instruction is an access instruction, the microcontroller performs an access operation. The access instruction may include a peripheral access instruction, and of course, may also be another type of access instruction. For example, when the access command is a peripheral access command, the microcontroller executes the peripheral access command to access the external device through the system bus.

The microcontroller executes the second instruction to replace the main controller to finish the operation corresponding to the second instruction, so that the microcontroller acquires the control right of the system bus to finish the operation corresponding to the second instruction during the data transmission of the direct memory access controller, the control right of the system bus does not need to be repeatedly handed over to the main controller, and the problem of low working efficiency of the system caused by the fact that the control right of the system bus needs to be repeatedly handed over to the main controller is solved.

In some embodiments, the dma control device further comprises a format conversion module; the data transmission method provided by the embodiment of the application further comprises the following steps: and calling a format conversion module, and performing format conversion on the operation instruction to obtain target data, wherein the data format of the target data is matched with the data format required by the first memory.

The format conversion module may be a separate module in the dma controller, may be integrated into the dma controller, or may be integrated into the microcontroller.

Illustratively, the format conversion module is an independent module, and when the dma controller transfers the operation command to the first memory of the microcontroller, the dma controller first sends the operation command to the format conversion module, the format conversion module performs format conversion on the operation command to obtain the target data, and the format conversion module transfers the target data to the first memory of the microcontroller.

For example, the format conversion module is a module integrated on the microcontroller, the dma controller may transfer the operation instruction to the microcontroller, the format conversion module in the microcontroller performs format conversion on the operation instruction to obtain the target data, and then the target data is transferred to the first storage.

For example, the format of the target data may be a string format, an array format, a json format, or the like.

The format conversion module is used for carrying out format conversion on the operation instruction to obtain target data, the data format of the target data is ensured to be matched with the data format required by the first memory, and the situation that the microcontroller cannot identify the data in the first memory can be avoided.

In some embodiments, the dma control device further comprises an arbiter; the data transmission method provided by the embodiment of the application further comprises the following steps: when the arbiter receives the instructions sent by the main controller and the microcontroller at the same time, the control arbiter processes the instructions of the main controller preferentially.

For example, when the arbiter receives the commands sent by the main controller and the microcontroller at the same time, the arbiter may process the commands of the main controller first and then the commands of the microcontroller. So that the working efficiency of the main controller can be ensured.

The arbiter preferentially processes the instruction of the main controller, so that the main controller can be conveniently accessed at any time during the period that the microcontroller controls the direct memory access controller to transmit data, and the working efficiency of the main controller can be ensured.

Referring to fig. 10, fig. 10 is a schematic flow chart of another data transmission method according to an embodiment of the present application, and as shown in fig. 10, the data transmission method may specifically include the following steps:

step S301: the main controller initiates an instruction carrying request to carry the operation instruction into a first memory of the microcontroller.

Step S302: the arbiter determines the source of the command transfer request and preferentially processes the request from the host controller.

Step S303: the arbiter transmits the instruction-handling request to the system bus.

Step S304: and the direct memory access controller obtains an instruction carrying request through a system bus and carries the operating instruction in the second memory to the first memory of the microcontroller.

Step S305: the main controller starts the microcontroller, and the microcontroller starts to work.

Step S306: the microcontroller reads and analyzes the instruction in the first memory.

Step S307: the microcontroller determines whether the instruction content is the first instruction or the second instruction, if the instruction content is the first instruction, step S308 is executed, and if the instruction content is the second instruction, step S309 is executed.

Step S308: the microcontroller sends a data transmission request to the dma controller, and the dma controller starts to carry data.

Step S309: the microcontroller executes a second instruction, the second instruction including one or more of a wait instruction, a query instruction, a pointer jump instruction, an access instruction, and a stop instruction.

In step S302: the arbiter may receive instructions from the microcontroller in addition to the host controller.

For example, during the period when the dma controller starts to carry data in step S308 or the microcontroller executes the second command in step S309, the microcontroller preferentially executes the command of the master controller when the microcontroller receives the command of the master controller. For example, when a stop command of the main controller is received, the microcontroller stops operating. The microcontroller preferentially executes the instruction sent by the main controller, so that the main controller can control the microcontroller at any time during the period that the microcontroller controls the direct memory access controller to transmit data, and the control right of the main controller is ensured.

The first instruction and the second instruction in the second storage are conveyed to the first storage in the microcontroller by the direct memory access controller according to the instruction conveying request of the main controller, so that the microcontroller replaces the main controller to control the direct memory access controller to transmit data and replaces the main controller to finish the operation corresponding to the second instruction according to the first instruction, the problem that the main controller is often required to participate in the data transmission process of the direct memory access controller is solved, the resource of the main controller is not required to be occupied, and the working efficiency of the system is improved.

In the data transmission method provided in the foregoing embodiment, the direct memory access controller transfers the operation instruction in the second storage to the first storage in the microcontroller, and the subsequent microcontroller may execute the first instruction to control the direct memory access controller to perform data transmission; the microcontroller replaces the main controller to control the controller to transmit data by executing the data transmission instruction, so that the resources of the main controller are not occupied, and the working efficiency of the system is improved; the microcontroller executes the second instruction to replace the main controller to finish the operation corresponding to the second instruction, so that the microcontroller acquires the control right of the system bus to finish the operation corresponding to the second instruction during the data transmission of the direct memory access controller, the control right of the system bus does not need to be repeatedly handed over to the main controller, and the problem of low working efficiency of the system caused by the fact that the control right of the system bus needs to be repeatedly handed over to the main controller is solved; the format conversion module is used for carrying out format conversion on the operation instruction to obtain target data, the data format of the target data is ensured to be matched with the data format required by the first memory, and the situation that the microcontroller cannot identify the data in the first memory can be avoided; the arbiter preferentially processes the instruction of the main controller, so that the main controller can be conveniently accessed at any time during the period that the microcontroller controls the direct memory access controller to transmit data, and the working efficiency of the main controller can be ensured.

One of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.

In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (17)

1. A direct memory access control device is characterized in that the direct memory access control device comprises a direct memory access controller and a microcontroller, wherein the direct memory access controller is connected with a system bus, and the system bus is also connected with a main controller;

and the microcontroller is used for controlling the direct memory access controller to carry out data transmission according to the operation instruction configured by the main controller so as to replace the main controller when the direct memory access controller is required to carry out data transmission.

2. The dma control apparatus according to claim 1, wherein the microcontroller comprises a first memory; the first memory is used for storing operation instructions configured by the main controller, and the operation instructions at least comprise first instructions;

the microcontroller is configured to read and execute the first instruction from the first storage to control the dma controller to perform data transmission.

3. The dma control apparatus according to claim 2, further comprising a second memory, the second memory being connected to the system bus, the second memory being configured to store the operation instruction;

the direct memory access controller is further configured to move the operation command to the first storage.

4. The dma control apparatus according to claim 2, wherein the operation commands further include a second command, the microcontroller is configured to execute the second command to replace the main controller to complete an operation corresponding to the second command, and the second command is a command that does not operate the dma controller.

5. The dma control apparatus according to claim 4, wherein the second instruction comprises one or more of a wait instruction, a query instruction, a pointer jump instruction, an access instruction, and a stop instruction.

6. The dma control apparatus of claim 5, wherein the access command comprises a peripheral access command, and the microcontroller executes the peripheral access command to access an external device via the system bus.

7. The dma controller according to any of claims 1-6, wherein the microcontroller is connected to the master controller, and the microcontroller is configured to receive a start command from the master controller and start according to the start command.

8. The direct memory access control device according to any one of claims 1 to 6, further comprising:

and the format conversion module is used for carrying out format conversion on the operation instruction to obtain target data, and the data format of the target data is matched with the data format required by the first memory.

9. The direct memory access control device according to any one of claims 1 to 6, further comprising:

the microcontroller is connected with the system bus through the arbiter, and the main controller is connected with the system bus through the arbiter;

the direct memory access control device comprises a first control path and a second control path, wherein the first control path and the second control path are used for controlling the direct memory access controller, the first control path is used for the microcontroller to access the direct memory access controller through the arbiter and the system bus, and the second control path is used for the main controller to access the direct memory access controller through the arbiter and the system bus.

10. The dma control apparatus according to claim 9, wherein the arbiter is configured to: and when receiving the instructions sent by the main controller and the microcontroller at the same time, preferentially processing the instructions of the main controller.

11. A data transfer method applied to the direct memory access control apparatus according to any one of claims 1 to 10, the method comprising:

when the direct memory access controller is required to be used for data transmission, the microcontroller acquires an operation instruction configured by the main controller;

and the microcontroller controls the direct memory access controller to transmit data according to the operation instruction configured by the main controller.

12. The data transmission method according to claim 11, wherein the microcontroller comprises a first memory, the main controller configures operation instructions and stores the operation instructions in a second memory, and the second memory is connected with the system bus; the method further comprises the following steps:

the direct memory access controller carries the operation instructions in the second memory to a first memory of the microcontroller, and the operation instructions at least comprise a first instruction;

the microcontroller reads and executes the first instruction from the first memory.

13. The method according to claim 11, wherein the controlling the dma controller to perform data transfer comprises:

the microcontroller sends a data transmission request to the direct memory access controller, and the direct memory access controller sends a bus occupation request to the microcontroller according to the data transmission request;

the microcontroller controls the direct memory access controller to enter a host working state from a slave working state according to the bus occupation request;

and after the direct memory access controller enters a host working state, data transmission is carried out through the system bus.

14. The data transmission method of claim 12, wherein the operation instruction further comprises a second instruction; the method further comprises the following steps:

and the microcontroller executes the second instruction to replace the main controller to complete the operation corresponding to the second instruction, wherein the second instruction comprises one or more of a waiting instruction, a query instruction, a pointer jump instruction, an access instruction and a stop instruction.

15. The data transmission method according to any of claims 11-14, wherein the dma controller further comprises a format conversion module; the method further comprises the following steps:

and calling the format conversion module to perform format conversion on the operation instruction so as to obtain target data, wherein the data format of the target data is matched with the data format required by the first memory.

16. The data transmission method according to any one of claims 11 to 14, wherein the dma control device further comprises an arbiter; the method further comprises the following steps:

and when the arbiter receives the instructions sent by the main controller and the microcontroller at the same time, controlling the arbiter to process the instructions of the main controller preferentially.

17. A data transfer system comprising a main controller and a direct memory access control device according to any one of claims 1 to 10, wherein the main controller is integrated with the direct memory access control device or wherein the main controller is disposed outside the direct memory access control device.

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