JP2000132503A - Data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device which can transfer data via a bus at a high speed and in a high efficiency. SOLUTION: This device transfers data via a bus and consists of an initiator, e.g. a processor I/F controller 310 which serves as a bus master, a target, e.g. an SDRAM controller 328 which receives the commands from the initiator and plural buffers, e.g. receiving buffers 320, 322 and 324 which belong to the target and hold the commands.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer device for performing high-speed and efficient data transfer in a computer system including a processor, a storage device, a screen display device, an I / O device and the like.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a typical computer system. As shown in FIG. 1, the processor 10 is connected via a system controller 12
SRAM 22, flash memory 24, ROM 26, V
It is connected to a storage device such as the RAM 30 and the SDRAM 40 and a screen display device such as the display 32. Further, the system includes a peripheral controller 14, a PCMCIA
52, a serial ROM 54, a local I / O bus 56,
It comprises serial interfaces 58 and 64, a network interface card 60, an I / O interface 62, a keyboard 66, a floppy disk 68, a hard disk 70, a parallel interface 72 and the like.

FIG. 6 is a block diagram showing an example of the configuration of the system controller shown in FIG. As shown in the figure,
The system controller 12 includes a processor I / F (interface) port 210, an SDRAM I / F port 220, a ROM I / F port 230, a graphics I / F port 240, and an I / O port 250. , An interrupt controller 270, a timer counter 280, and a serial controller 290.

Conventionally, in a VME (Versa Module Europe) bus, a PCI (Peripheral Components Interconnect) bus, an ISA (Industry Standard Architecture) bus and other local buses, one device occupies the bus (that is, a bus master). Transfer data. A processor, a memory (storage device), a screen display device, an I / O device, and the like are connected to the initiator (that issues commands to other devices) and the target (the one that is controlled by the initiator) on these buses. Thus, a computer system is configured. On these buses, two or more devices may request occupation of the bus at the same time. In this case, the right to use the bus is determined by an arbitration circuit or the like. Then, the device having the right to use occupies the bus at that moment (that is, becomes a bus master) and performs data transfer.

[0005] In particular, the PCI bus has a bus bridge architecture, and concurrent data transfer can be executed on separate buses separated by a bridge. However, in the above-mentioned bus, usually, in data transfer, only one device occupies the bus at a certain moment, and the other devices wait.

FIG. 7 is a block diagram showing an example of a data flow in a conventional system controller. The processor I / F controller 212 and the DMA controller 260 have only an initiator function. Also,
SDRAM controller 224, ROM controller 2
34 and the graphics port 244 have only a target function. The I / O controller 254 has both an initiator function and a target function.

As shown in FIG. 1, the SDRAM controller 224, the ROM controller 234, the graphics port 244, and the I / O controller 254 have reception buffers 222, 232, 242, and 252, respectively. Then, each buffer 222, 232 or 252
Holds commands, data, and the like transmitted to each controller 224, 234, or 254. Buffer 242
Holds commands, data, and the like transmitted to the graphics port 244.

[0008]

However, the above prior arts have the following disadvantages.

(1) When data is transferred to a target on the bus in response to a request from two or more initiators, a bus master device is determined by handshaking the right to use the bus on the initiator side. At this time, the initiator that has failed to acquire the usage right waits until the initiator (that is, the bus master) that has obtained the usage right completes the data transfer. That is, the initiator that cannot acquire the right to use the bus cannot perform the next process (data transfer), and the execution time (bus transaction) increases.

(2) While direct memory access transfer (DMA transfer) is being performed on the system, the processor cannot own the bus, and waits for access at that moment. In this case, recent RISC (Reduced I
nstruction Set Computer) The function of the processor cannot work efficiently.

(3) Multitask, multithread,
In systems that share parallel execution programs and data typified by multi-processes, shortening of bus transactions and concurrent data transfer are required to improve the performance of such systems.
It is not suitable for buses, VME buses and the like. Although the PCI bus satisfies these requirements to some extent, efficient transfer is not possible in constructing a system for sharing data. In addition, when high-speed data transfer such as burst transfer from two or more devices is performed, the dispersion ratio cannot be optimized in a timely manner.

The present invention has been made in view of the above points, and has as its object the performance of a system using a plurality of devices such as a processor, a screen display device, a memory (storage device), and an I / O device. As a means for improving the performance, it is an object to provide a data transfer device capable of executing bus data transfer at high speed.

In addition to the high-speed data transfer, all data transmitted by the first initiator are transferred to the first initiator.
Before the first target finishes processing, the first initiator releases the bus, the first initiator starts a new data transfer to the second target, or the second initiator becomes the new bus master. To provide a data transfer device capable of starting new data transfer.

[0014]

According to one aspect of the present invention, there is provided a data transfer apparatus for performing data transfer via a bus, comprising: an initiator serving as a bus master; and a command transmitted from the initiator. It comprises a target to receive, and a plurality of reception buffers belonging to the target and holding the command.

The reception buffer includes: (1) a buffer of a memory interface port capable of decoding a write command and retaining received data when data is transferred from the processor interface port to the memory interface port; When data is transferred from the port to the screen display device interface port, a buffer of the screen display device interface port capable of decoding a write command and holding received data; (3) data transfer from the processor interface port to the I / O device interface port A buffer of an I / O device interface port capable of decoding a write command and holding received data;
(4) When data is transferred from one memory interface port to another memory interface port, a buffer of the memory interface port that can decode a write command and hold received data, and (5) from the memory interface port to the screen display device interface port. A buffer of a screen display device interface port capable of decoding a write command when data is transferred and holding received data, and (6) transferring a write command when data is transferred from a memory interface port to an I / O device interface port. A buffer of an I / O device interface port that can decode and hold received data, and (7) decodes a write command when data is transferred from the screen display device interface port to the memory interface port. A buffer of a memory interface port capable of holding received data, and (8) an I / O capable of decoding a write command and holding received data when data is transferred from the screen display device interface port to the I / O device interface port. (9) I / O buffer of a memory interface port capable of decoding a write command and retaining received data when data is transferred from the I / O device interface port to the memory interface port; When data is transferred from the device interface port to the screen display device interface port, a buffer of the screen display device interface port capable of decoding a write command and holding received data;
Etc. are exemplified.

The receiving buffer is preferably provided for each port of the initiator. However, one receiving buffer is preferably provided for each port of the initiator, and another buffer is provided for each port of a plurality of initiators other than the processor. You don't have to.

According to a second aspect of the present invention, there is provided a data transfer apparatus for transferring data via a bus, comprising: an initiator serving as a bus master; a target transmitting data to the initiator; and a target belonging to the target and holding the data. And a plurality of transmission buffers.

The transmission buffer includes: (1) a transmission buffer of a processor interface port capable of holding transmission data corresponding to a decoded read command when data is transferred from the processor interface port to the memory interface port; A transmission buffer of a processor interface port capable of holding transmission data corresponding to a decoded read command when data is transferred from the interface port to the screen display device interface port; (3) data from the processor interface port to the I / O device interface port A transmission buffer of a processor interface port capable of holding transmission data corresponding to a decoded read command when transferred; (4) a first memory interface port; When data is transferred from the first memory interface port to the second memory interface port, a transmission buffer of the first memory interface port capable of holding transmission data corresponding to the decoded read command, (5) from the memory interface port to the screen display device interface port A transmission buffer of a memory interface port capable of holding transmission data corresponding to a decoded read command when data is transferred, and (6) a decoding buffer read when data is transferred from the memory interface port to the I / O device interface port. A transmission buffer of a memory interface port capable of holding transmission data corresponding to a command; (7) a read command decoded when data is transferred from the screen display device interface port to the memory interface port; (8) A transmission buffer of a screen display device interface port capable of holding transmission data corresponding to (8), when data is transferred from the screen display device interface port to the I / O device interface port, transmission data corresponding to a decoded read command is transmitted. (9) I / O device interface port capable of holding transmission data corresponding to a decoded read command when data is transferred from the I / O device interface port to the memory interface port (10) Transmission of an I / O device interface port capable of holding transmission data corresponding to a decoded read command when data is transferred from the I / O device interface port to the screen display device interface port. Communication buffer, and the like.

The transmission buffer is preferably provided for each port of the initiator. However, one transmission buffer is always provided for each port of the initiator, and another transmission buffer is provided for each port of a plurality of initiators other than the processor. You don't have to.

According to a third aspect of the present invention, in the first aspect of the present invention, when a plurality of the receiving buffers transfer data to the same target, a priority of data processing between the receiving buffers is determined. An arbitration circuit is provided.

A plurality of commands issued by a plurality of initiators are respectively held in a plurality of buffers belonging to the same target and decoded. Then, the commands are sequentially processed from the command held in the buffer with the highest priority determined by the arbitration circuit. The change of the priority of the arbitration circuit is for realizing that it is desired to temporarily process a large amount of data transfer with respect to a certain device or to preferentially process a certain device with respect to another device. The priority is changed in real time.

According to a fourth aspect of the present invention, in the second aspect of the present invention, when a plurality of transmission buffers belonging to the same target transfer data to respective initiators, priority of data processing among the transmission buffers is determined. Arbitration circuit for determining

A plurality of commands issued by a plurality of initiators are held in a buffer belonging to the same target, decoded, and data is held in a transmission buffer of a target port. A plurality of transmission buffers are provided for the first initiator and for the second initiator. Then, the data is sequentially processed from the data held in the transmission buffer having the higher priority determined by the arbitration circuit. The priority is changed in real time.

According to a fifth aspect of the present invention, there is provided a data transfer device for transferring data via a bus, comprising: an initiator serving as a bus master; and a target receiving a command from the initiator, wherein the target transmits the command. The initiator is provided with a transmission buffer for holding a command issued by the initiator when the reception buffer is not empty.

If it is assumed that a command cannot be transmitted from the initiator when the target reception buffer is not empty,
The initiator waits for processing until the target reception buffer becomes empty. Therefore, if a transmission buffer is provided in the initiator and a command or the like can be put in the transmission buffer, the initiator can start the next process even if a command or the like cannot be put in the target reception buffer.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

The present invention is an apparatus for improving the throughput of each initiator by efficiently processing data transfer in all transactions in a computer system as shown in FIG.

FIG. 1 is a diagram showing a data flow when data is transferred from an initiator to a target by a write command issued by a device (initiator) having a bus master function according to the first embodiment.

For convenience, the ROM controller 334, SD
Assume that the RAM controller 328 and the graphics port 348 do not have a bus master function. Further, the processor I / F controller 310 and the I / O controller 3
56, it is assumed that the DMA controller 260 has a bus master function.

In FIG. 1, a system configuration is adopted in which data is transferred to the ROM controller 334 only from the processor I / F controller 310. For this reason, the reception buffer is the processor I / F controller 3
Only the reception buffer (BUF) 330 connected to 10 is required.

However, the SDRAM controller 328 includes reception buffers 320, 322, and 324 for each initiator because commands are transferred from each of the processor I / F controller 310, the I / O controller 356, and the DMA controller 260. The graphics port 348 also includes reception buffers 340, 342, and 344, respectively. Since data is transferred from the processor I / F controller 310 and the DMA controller 260 to the I / O controller 356, two reception buffers (350 and 352) are provided.
Is provided.

An initiator inputs a write command and data to a target reception buffer. For example, when the processor I / F controller 310 is the initiator and the SDRAM controller 328 is the target, a write command and data are input from the processor I / F controller 310 to the reception buffer 320. The posted write method is used as the write command. It is also possible to support burst transfer.

The data flow is as shown by the arrow in FIG. That is, the data transmitted from the I / O controller 356 is transmitted to the SD buffer via the reception buffer 322.
The data is transferred to either the graphics port 348 via the RAM controller 328 or the reception buffer 342.

Similarly, data sent from the DMA controller 260 is transmitted to the SD buffer via the reception buffer 324.
Graphics port 348 via RAM controller 328, receive buffer 344, or receive buffer 3
The data is transferred to any one of the I / O controllers 356 via the communication device 52.

Similarly, the processor I / F controller 3
The data sent out from the SDRAM controller 328 and the reception buffer 3
30, the ROM controller 334, the reception buffer 340, the graphics port 348, or the reception buffer 350, the I / O controller 35.
6 is transferred.

Since the target is provided with the reception buffer for each initiator, the initiator can immediately enter the next operation cycle after transferring commands, data, etc. to the reception buffer of the target.
The initiator can process data efficiently.

Specifically, for example, the SDRAM 328
By providing the reception buffer 320 for the processor I / F controller 310, the reception buffer 322 for the I / O controller 356, and the reception buffer 324 for the DMA controller 260, the processor I / F controller 310 Since the next operation cycle can be started immediately after the transfer of the command, the data, and the like, the processor I / F controller 310 can process the data efficiently.

By providing a reception buffer for each initiator in this way, each initiator can quickly process a command transfer and release the bus. However, the bus usage frequency of each initiator is not always the same. For this reason, an initiator frequently used may be provided with one reception buffer for one initiator, and an initiator less frequently used may be provided with one reception buffer for a plurality of initiators.

The controls 332, 326, 34
6 and 354 are reception buffers (B
UF) group, and has a function of decoding commands and data.

FIG. 2 is a diagram showing a data flow when data is transferred from a target to an initiator by a read command issued by a device having a bus master function (initiator) according to the second embodiment.

The reception buffer 432 connected to the ROM controller 435 is used as the processor I / F controller 4
When a read command is received from the CPU 10, the requested data is transferred from the ROM controller 435 to the processor I / F controller 410 via the transmission buffer 436. Similarly, when receiving buffer 433 receives a read command from I / O controller 450, RO
The requested data is transferred from the M controller 435 to the I / O controller 450 via the transmission buffer 437. Similarly, when receiving buffer 434 receives a read command from DMA controller 460, RO
The requested data is transferred from the M controller 435 to the DMA controller 460 via the transmission buffer 438.

When the reception buffer 422 receives a read command from the processor I / F controller 410, the reception buffer 422 sends the read command from the SDRAM controller 425 via the transmission buffer 426 to the processor I / F controller 41.
The requested data is transferred to 0. Similarly, when the reception buffer 423 receives a read command from the I / O controller 450, it passes through the transmission buffer 427,
The data is transferred to the I / O controller 450. Similarly, the reception buffer 424 controls the DMA controller 460
When a read command is received from the
, Data is transferred to the DMA controller 460.

When the reception buffer 442 receives the read command, data is transferred to the processor I / F controller 410 via the transmission buffer 446. Similarly, when the reception buffer 443 receives the read command, the data is transferred to the I / O controller 450 via the transmission buffer 447. Similarly, when the reception buffer 444 receives the read command, data is transferred to the DMA controller 460 via the transmission buffer 448.

Regarding the I / O controller 450, when the reception buffer 452 receives the read command, data is transferred to the processor I / F controller 410 via the transmission buffer 454. When the reception buffer 453 receives the read command, data is transmitted to the DMA controller 460 via the transmission buffer 455. Since the I / O bridge 458 has a bus bridge function, when data is transferred between one I / O device 456 and another I / O device 457, the data must pass through the I / O controller 450. There is no.

Since the target has the transmission buffer for each initiator, the target can immediately start the next operation cycle after transferring data or the like to the transmission buffer, so that the target can process the data efficiently.

More specifically, for example, the SDRAM controller 425 includes a transmission buffer 426 for the processor I / F controller, a transmission buffer 427 for the I / O controller, and a transmission buffer 428 for the DMA controller.
And the SDRAM controller 425
Can transfer to the next operation cycle immediately after transferring data and the like to the transmission buffer 426.
The SDRAM controller 425 can process data efficiently.

When the frequency of data transfer from a certain target to a certain initiator is low, it is not always necessary to provide a transmission buffer dedicated to such an initiator. For example, data transfer from the target A to the initiator B is performed frequently, but when the data transfer from the target A to the initiators C and D is infrequent, the target A includes one transmission buffer dedicated to the initiator B, One transmission buffer for the initiators C and D may be provided.

Next, an outline of the interface port will be described. FIG. 3 is a block diagram showing an outline of an interface port of a device having only a slave function according to the third embodiment. Interface port 500
Has only a slave function (ie, is a target but not an initiator).
Connect to For example, the ROM 26 shown in FIG.
M30, SDRAM40, etc. The interface port 500 has a data transfer flow for a read command or a write command issued by the initiator. The reception buffers 521, 522, and 523 include a write command sent from an initiator (not shown),
Holds addresses, data, etc., and performs write control 5.
Transfer to 25. Receive buffers 531, 532, 533
Holds a read command, an address, and the like sent from the initiator, and transfers the read command, the address, and the like to the read control 535. The transmission buffers 541, 542, 543 transfer the data requested by the initiator to the initiator.

The write control 525 controls the reception buffers 521 to 521. Read control 53
5 controls the transmission buffers 541 to 3. The priority of each control (525 and 535) is determined by the arbiter for the bus in the interface port, that is, the arbitration circuit 550.

As shown in FIG. 7, in a device in which SDRAM controller 224 has only one reception buffer 222, data is first transferred from processor I / F controller 212 to reception buffer 222, and then I / O
When data is transferred from the controller 254 to the receiving buffer 222 and finally data is transferred from the DMA controller 260 to the receiving buffer 222, if the receiving buffer is a FIFO (first-in first-out) type buffer, the SDRAM 224 follows the order in which the data was transferred. Processes the data. If the reception buffer is a LIFO (last in, first out) buffer, the SDRAM 224 processes the data in the reverse order of the order in which the data was transferred.

However, in this embodiment, data is processed according to the priority determined by the arbitration circuit. That is, even when data is received in the order of the reception buffers 521, 522, and 523, the data is not always processed in the order in which the data was received or in the reverse order.

Here, two commands, a write command and a read command, may be generated from the same initiator. In this case, first, the write command is input to the write command reception buffer (BUF) 521,
While the write command is stopped in the reception buffer 521 due to the posted write method, the read command may be input to the read command reception buffer 531. At this time, a circuit for recognizing whether the write command is input to the write command receiving buffer first or the read command is input to the read command receiving buffer first is required. In such a case, it is necessary to process a write command and then process a read command. Conversely, when a read command is input before a write command is input, the read command must be processed before the write command is processed. By providing such a circuit, from one initiator to one target,
Even if two commands, a read command and a write command, are issued, no overtaking of the command (the previously issued command is processed later) does not occur, and data transfer without contradiction can be established.

When two commands, a write command and a read command, are issued from the same initiator, it is necessary to prohibit the overtaking of the command as described above. However, for a command issued from a different initiator, It is not necessary to prohibit such overtaking.

A processor (not shown) includes an arbitration circuit 550
Set the arbitration method of Of course, the arbitration circuit 550 is required for each interface port 500 of each target. The arbitration circuit 550 includes buffers (531-533) for holding read commands from the initiator and buffers (521) for holding write commands from the initiator.
523), arbitration must be performed on the buffers (541 to 543) that hold data to be transmitted to the initiator.

As described above, the arbitration circuit exists for each port. As an arbitration method in each arbitration circuit, a fixed priority method, a round robin method, a single level method, or the like can be adopted. Then, how to combine them is made variable. In other words, the circuit configuration is such that the setting of combining the fixed priority method and the round robin method or the combination of the fixed priority method and the single level method can be changed. Further, priorities are assigned to the arbitration methods, and the priorities are made variable. That is, when performing a certain process, the fixed-priority system has the first priority, and the round-robin system has the second priority. When performing another process, the round-robin system has the first priority, and the fixed-priority system has the highest priority. Has a circuit configuration that can change the priority order such that By making the priority assignment method (arbitration method) changeable, the throughput can be improved.

FIG. 4 is a block diagram showing an outline of an interface port connected to an initiator device having a bus master function according to a fourth embodiment of the present invention. The interface port 600 connects to a device 610 having a bus master function. Interface port 60
0 differs from the interface port 500 shown in FIG. 5 in that it has a function of issuing an address and a read / write command to a target (not shown).

Bus master read control 620
Controls the read command transmission buffers 622 to 624. Also, bus master write control 6
30 controls the transmission buffers 632-634.
That is, a read / write command or an address is received from the device 610 as an initiator, and buffers 626 to 628 and 636 to 63 of the target I / F port are received.
8, a command, data, and the like are transmitted.

For example, when a write command is issued from the device 610, the write command is issued to the buffer 636 of the target I / F port as the command transfer destination via the external control 612, the bus master write control 630, and the buffer 632. Command is transferred. At this time, the buffer 636 may already hold another command or data. In such a case, since the posted write method is employed, the already issued write command is held in the buffer 632. On the other hand, buffer 6
When 36 is empty, the write command is transferred to the buffer 636 without being held in the buffer 632.

When a command is held in the buffer 632, the external control 612 suspends the transfer cycle of the device 610 until the buffer 632 becomes empty. Buffer 632 transfers commands, addresses, and data to buffer 636 when buffer 636 is empty.

The above-mentioned two types of interface ports of the system controller 12 (the port 500 having only the slave function and the port 600 having the master function) can be basically realized by the same circuit. That is, an interface port can be added only by adding a buffer line or expanding the control range of the controller.

Note that the present invention is not limited to the above-described embodiment, and it goes without saying that the system configuration can be variously modified or realized by a semiconductor or an electric circuit without departing from the gist of the present invention.

[0062]

As described above, according to the present invention, the following effects can be obtained.

By providing a plurality of reception buffers in the interface port to which the target belongs, the initiator transfers commands and the like to the reception buffers,
Since the next operation cycle can be entered immediately, the initiator can process data efficiently.

By providing a plurality of transmission buffers at the interface port to which the target belongs, the target transfers data and the like to the transmission buffer,
Since the next operation cycle can be started immediately, the target can process data efficiently.

Further, an arbitration circuit is provided. The arbitration circuit determines the priority order among the buffers, and processes the data in order from the buffer having the highest priority order, so that the arbitration circuit only changes the priority order in real time. Efficient processing of data transfer of the entire system can be realized.

When the system is expanded by adding an interface port to which a target belongs in the system controller, a buffer for a new port is added to an existing port in the system controller, and the buffer is subjected to arbitration by an existing arbitration circuit. The system can be expanded simply by adding In addition, the circuit scale related to this does not significantly increase.

The write command transmission buffer in the interface port having the bus master function and its controller enable the initiator to perform the following internal processing without interrupting the transfer of the write command. Thereby, data processing on the initiator side can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a diagram showing a data flow when data is transferred from an initiator to a target by a write command issued by a device (initiator) having a bus master function according to the first embodiment.

FIG. 2 is a diagram showing a data flow when data is transferred from a target to an initiator by a read command issued by a device (initiator) having a bus master function according to a second embodiment.

FIG. 3 is a block diagram showing an outline of an interface port of a device having only a slave function according to a third embodiment;

FIG. 4 is a block diagram showing an outline of an interface port connected to an initiator device having a bus master function according to a fourth embodiment.

FIG. 5 is a block diagram showing a configuration of a typical computer system.

FIG. 6 is a block diagram showing an example of the configuration of the system controller shown in FIG. 5;

FIG. 7 is a block diagram showing an example of a data flow in the system controller of FIG. 5;

[Explanation of symbols]

260 DMA controller 310 Processor I / F controller 328 SDRAM controller 334 ROM controller 348 Graphics port 356 I / O controller 320, 322, 324, 330, 340, 342, 3
44, 350, 352 Target-side receive buffers 426, 427, 428, 436, 437, 438, 4
46, 447, 448, 454, 455 Target side transmission buffer 550, 650 Arbitration circuit 622, 623, 624, 632, 633, 634 Initiator side transmission buffer

Claims (5)

[Claims] 1. A data transfer apparatus for transferring data via a bus, comprising: an initiator serving as a bus master; a target receiving a command from the initiator; and a plurality of reception buffers belonging to the target and holding the command. A data transfer device, comprising: 2. A data transfer apparatus for performing data transfer via a bus, comprising: an initiator serving as a bus master; a target transmitting data to the initiator; and a plurality of transmission buffers belonging to the target and holding the data. A data transfer device, comprising: 3. An arbitration circuit for determining a priority of data processing among said plurality of receiving buffers when a plurality of said receiving buffers transfer data to the same target. 2. The data transfer device according to 1. 4. An arbitration circuit for determining a priority of data processing among the transmission buffers when a plurality of transmission buffers belonging to the same target transfer data to respective initiators. The data transfer device according to claim 2, wherein 5. A data transfer device for performing data transfer via a bus, comprising: an initiator serving as a bus master; and a target receiving a command from the initiator, wherein the target includes a reception buffer holding the command. The data transfer device, wherein the initiator includes a transmission buffer for holding a command issued by the initiator when the reception buffer is not empty.