CN115411105A - GaN device with P-GaN field plate and manufacturing method - Google Patents
GaN device with P-GaN field plate and manufacturing method Download PDFInfo
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- 239000002184 metal Substances 0.000 claims abstract description 87
- 229910052751 metal Inorganic materials 0.000 claims abstract description 87
- 230000004888 barrier function Effects 0.000 claims abstract description 51
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
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- 229910002704 AlGaN Inorganic materials 0.000 description 3
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- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
The present invention relates to the field of GaN devices. The invention provides a GaN device with a P-GaN field plate and a manufacturing method thereof, wherein the P-GaN field plate is directly formed on the surface of a barrier layer, a channel below the P-GaN field plate does not have a two-dimensional electron gas layer, the P-GaN field plate is discontinuously distributed in a direction vertical to the channel, and the two-dimensional electron gas layer is arranged at the discontinuous position, so that the current between a source electrode and a drain electrode is normally conducted, and the GaN device can normally work. When the GaN device experiences high drain voltage, the P-GaN field plate is rapidly clamped off, and the voltage difference between the grid electrode and the drain electrode is almost completely reduced between the P-GaN field plate and the drain electrode, so that the pressure bearing of a P-i-n junction at the grid electrode is small, holes are prevented from being emitted into a grid electrode metal electrode from a grid electrode P-GaN layer, and the problem of dynamic threshold voltage drift of the GaN device is solved.
Description
Technical Field
The invention relates to the field of GaN devices, in particular to a GaN device with a P-GaN field plate and a manufacturing method thereof.
Background
Referring to fig. 1, the conventional GaN device has a serious problem of dynamic threshold voltage. When the GaN device is subjected to high drain voltage, holes are emitted from the grid electrode P-GaN layer into the grid electrode metal electrode, so that positive charges in the grid electrode P-GaN layer are reduced; after the device is opened again, the positive charge reduced in the grid P-GaN layer cannot be recovered immediately, the GaN device can be started only by needing larger grid voltage, and the threshold voltage has forward drift. The common solution is to add a metal field plate on the surface of the dielectric layer, balance the electric field distribution by using the metal field plate, and reduce the withstand voltage of the p-i-n junction at the gate, thereby inhibiting the threshold voltage drift phenomenon.
The metal field plate of the traditional GaN device is formed on the surface of a dielectric layer of the GaN device, and the metal field plate cannot directly contact with a barrier layer, so that the defect is that the pinch-off voltage of the metal field plate is large, namely the threshold voltage of an MIS-HEMT formed by the metal field plate, the dielectric layer below the metal field plate and an AlGaN/GaN heterojunction is large and generally ranges from tens of volts to hundreds of volts. Before the metal field plate is pinched off, the voltage V between the grid and the drain DG The P-i-n junction at the gate is still required to bear, the gate P-GaN layer is still depleted to some extent, resulting in holes being emitted from the gate P-GaN layer into the gate metal electrode, and the problem of dynamic threshold voltage still exists.
Disclosure of Invention
In order to overcome the technical problem that a GaN device faces dynamic threshold voltage, the invention provides a GaN device with a P-GaN field plate and a manufacturing method thereof.
To achieve the above object, the present invention provides a GaN device having a P-GaN field plate, comprising:
the GaN-based electronic device comprises a substrate, a GaN layer positioned on the surface of the substrate, and a barrier layer positioned on the surface of the GaN layer, wherein a two-dimensional electronic gas layer is arranged between the GaN layer and the barrier layer;
the grid electrode P-GaN layer, the P-GaN field plate, the source electrode and the drain electrode are positioned on the surface of the potential barrier layer, the grid electrode metal electrode is positioned on the surface of the grid electrode P-GaN layer, the P-GaN field plate metal electrode is positioned on the surface of the P-GaN field plate, and the grid electrode P-GaN layer and the grid electrode metal electrode on the surface of the grid electrode P-GaN layer form a grid electrode;
the P-GaN field plate is positioned between the grid electrode and the drain electrode, the grid electrode is positioned between the source electrode and the P-GaN field plate, a two-dimensional electron gas layer does not exist in a channel below the grid electrode and the P-GaN field plate, and the P-GaN field plates are discontinuously distributed in a direction perpendicular to the channel direction.
Optionally, when the P-GaN field plates are discontinuously distributed in a direction perpendicular to the channel direction, the interval between two adjacent P-GaN field plates is 1nm to 10um.
Optionally, the thickness of the barrier layer or the doping concentrations of the gate P-GaN layer and the P-GaN field plate are adjusted so that the channel below the P-GaN field plate has no two-dimensional electron gas layer.
Optionally, the method further includes: the metal field plate is positioned between the grid electrode and the drain electrode and positioned on the surface of the dielectric layer.
The invention provides a manufacturing method of a GaN device with a P-GaN field plate, which comprises the following steps:
providing a substrate, forming a GaN layer on the surface of the substrate, forming a barrier layer on the surface of the GaN layer, and arranging a two-dimensional electron gas layer between the GaN layer and the barrier layer;
forming a grid electrode P-GaN layer, a P-GaN field plate, a source electrode and the drain electrode on the surface of the barrier layer, forming a grid electrode metal electrode on the surface of the grid electrode P-GaN layer, forming a P-GaN field plate metal electrode on the surface of the P-GaN field plate, and forming a grid electrode by the grid electrode P-GaN layer and the grid electrode metal electrode on the surface of the grid electrode P-GaN layer;
the P-GaN field plate is formed between the grid electrode and the drain electrode, the grid electrode is formed between the source electrode and the P-GaN field plate, a two-dimensional electron gas layer does not exist in a channel below the grid electrode and the P-GaN field plate, and the P-GaN field plates are discontinuously distributed in a direction perpendicular to the channel direction.
Optionally, the P-GaN field plate and the gate P-GaN layer are formed simultaneously by the same process.
Optionally, the specific process for forming the P-GaN field plate and the gate P-GaN layer includes: forming a P-GaN material layer on the surface of the barrier layer, forming a photoresist layer on the surface of the P-GaN material layer, exposing and developing the photoresist layer, etching the P-GaN material layer by using the exposed photoresist layer as a mask to form a P-GaN field plate and a grid P-GaN layer, wherein the P-GaN field plate is discontinuously distributed in a direction perpendicular to the channel direction, and the grid P-GaN layer is continuously distributed in a direction perpendicular to the channel direction.
Optionally, the gate metal electrode and the P-GaN field plate metal electrode are formed simultaneously by the same process or are prepared by different metals respectively.
Optionally, the source and the drain are formed simultaneously by the same process.
Optionally, the method further includes: and forming dielectric layers on the surfaces of the grid metal electrode, the P-GaN field plate metal electrode, the source electrode, the drain electrode and the barrier layer, and forming a metal field plate between the grid and the drain electrode and on the surface of the dielectric layer.
In summary, the invention has the advantages and beneficial effects that:
according to the invention, the P-GaN field plate is directly formed on the surface of the barrier layer, the P-GaN field plate is in direct contact with the barrier layer, the pinch-off voltage of the P-GaN field plate is smaller than that of a metal field plate in the prior art, when a GaN device experiences high drain voltage, the P-GaN field plate is rapidly pinched off, the voltage difference between the grid electrode and the drain electrode almost completely falls between the P-GaN field plate and the drain electrode, due to the shielding of the P-GaN field plate, the pressure bearing of a P-i-n junction at the grid electrode is very small, a depletion region in the grid electrode P-GaN layer is almost not widened, holes are prevented from being emitted into the grid electrode metal electrode from the grid electrode P-GaN layer, and compared with the traditional metal field plate, the P-GaN field plate can effectively inhibit the concentration of a P-i-n junction electric field at the grid electrode, so that the problem of dynamic threshold voltage drift is overcome.
In the invention, because the channel below the P-GaN field plate does not have the two-dimensional electron gas layer, in order to ensure that the GaN device can work normally, the P-GaN field plate is distributed discontinuously in the direction vertical to the channel, and the two-dimensional electron gas layer is arranged at the discontinuous position, so that the current between the source electrode and the drain electrode is conducted normally, thereby ensuring that the GaN device can work normally.
Further, C between the P-GaN field plate and the drain electrode DS Is a variable capacitor, when the voltage between the source and the drain is V DS P at the gate > 0-the i-n junction is reversely biased, the two-dimensional electron gas in the channel below the drain electrode is depleted, and meanwhile, a depletion region in the P-GaN field plate expands towards the upper surface of the P-GaN field plate; when the voltage V between the source and the drain is higher DS When larger, the depletion region in the P-GaN field plate is almost completely depleted, and the capacitance C between the source electrode and the drain electrode DS The upper polar plate extends upwards from the contact surface of the P-GaN field plate and the barrier layer to the upper surface of the P-GaN field plate, and the capacitance C between the source electrode and the drain electrode DS The distance between the electrode plates is increased, the distance is the sum of the thickness of the P-GaN field plate and the width of the depletion region, and the P-GaN field plate enables the capacitance C between the source electrode and the drain electrode when the GaN device experiences high drain electrode voltage DS The size of the converter is smaller, so that the working frequency of a GaN device is improved, the system size is reduced, the system power density is improved, and the converter efficiency is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional GaN device;
FIG. 2 is a top view of a cell of a GaN device with a P-GaN field plate according to an embodiment of the invention;
fig. 3 is a schematic flow chart illustrating a method of fabricating a GaN device with a P-GaN field plate according to an embodiment of the present invention;
fig. 4 to 8 are schematic cross-sectional structural views illustrating a process of manufacturing line1 of a GaN device having a P-GaN field plate according to an embodiment of the present invention;
fig. 9 is a schematic cross-sectional view of line2 of a GaN device with a P-GaN field plate according to an embodiment of the present invention;
FIG. 10 is a top view of a cell of a GaN device with a P-GaN field plate according to another embodiment of the invention;
fig. 11 is a schematic cross-sectional view of line3 of a GaN device with P-GaN field plates according to another embodiment of the present invention;
fig. 12 is a schematic cross-sectional view of line4 of a GaN device with P-GaN field plates according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to specific examples for facilitating understanding by those skilled in the art.
An embodiment of the present invention provides a GaN device having a P-GaN field plate, referring to fig. 2, including:
the substrate comprises a substrate 10, a GaN layer 20 positioned on the surface of the substrate 10, and a barrier layer 40 positioned on the surface of the GaN layer 20, wherein a two-dimensional electron gas layer 30 is arranged between the GaN layer 20 and the barrier layer 40;
the gate P-GaN layer 51, the P-GaN field plate 52, the source electrode 61 and the drain electrode 62 are positioned on the surface of the barrier layer 40, the gate metal electrode 63 is positioned on the surface of the gate P-GaN layer 51, the P-GaN field plate metal electrode 64 is positioned on the surface of the P-GaN field plate 52, and the gate P-GaN layer 51 and the gate metal electrode 63 on the surface of the gate P-GaN layer 51 form a gate 74;
the P-GaN field plate 52 is positioned between the gate 74 and the drain electrode 62, the gate 74 is positioned between the source electrode 61 and the P-GaN field plate 52, the channel below the gate 74 and the P-GaN field plate 52 is free of the two-dimensional electron gas layer 30, and the P-GaN field plate 52 is discontinuously distributed perpendicular to the channel direction;
and metal interconnection layers positioned on the gate metal electrode 63, the P-GaN field plate metal electrode 64, the surface of the source electrode 61 and the surface of the drain electrode 62, wherein the source electrode 61 and the P-GaN field plate metal electrode 64 are electrically connected through the metal interconnection layers.
Specifically, in the embodiment of the present invention, the substrate 10 is a silicon substrate, and in other embodiments, the substrate is a silicon carbide substrate, a sapphire substrate, or another suitable substrate.
In the embodiment of the present invention, the barrier layer 40 is an AlGaN barrier layer, and in other embodiments, the barrier layer is an InAlN barrier layer, an AlN barrier layer, or other barrier layers suitable for GaN devices.
In the embodiment of the invention, when the P-GaN field plates 52 are discontinuously distributed in a direction perpendicular to the channel direction, the interval between two adjacent P-GaN field plates 52 is 1nm to 10um, so that the current between the source and the drain normally flows when the GaN device is turned on.
The thickness of the barrier layer 40 or the doping concentration of the gate P-GaN layer 51 and the P-GaN field plate 52 are adjusted to ensure that the two-dimensional electron gas layer 30 is not arranged in the channel below the P-GaN field plate 52. The barrier layer 40 is thin, so that when the source electrode 61 of the GaN device has no external bias voltage, the channel below the grid 74 and the channel below the P-GaN field plate 52 are not provided with the two-dimensional electron gas layer 30, and the device has normally-off characteristics.
In the embodiment of the present invention, the P-GaN field plate 52 and the gate P-GaN layer 51 are formed simultaneously by the same process.
In the embodiment of the present invention, the specific process for forming the P-GaN field plate 52 and the gate P-GaN layer 51 includes: forming a P-GaN material layer on the surface of the barrier layer 40, forming a photoresist layer on the surface of the P-GaN material layer, exposing and developing the photoresist layer, etching the P-GaN material layer by using the exposed photoresist layer as a mask, and forming a P-GaN field plate 52 and a grid P-GaN layer 51, wherein the P-GaN field plate 52 is discontinuously distributed in a direction perpendicular to the channel direction, and the grid P-GaN layer 51 is continuously distributed in a direction perpendicular to the channel direction.
The P-GaN field plate 52 is formed on the surface of the barrier layer 40, and is in direct contact with the barrier layer 40, when the GaN device experiences a high drain voltage, the pinch-off voltage of the P-GaN field plate 52 is much smaller than that of a metal field plate in a conventional device, the P-GaN field plate 52 is rapidly pinched off, the voltage difference between the gate 74 and the drain 62 is almost completely between the P-GaN field plate 52 and the drain 62, the P-i-n junction at the gate 74 has a small pressure, and almost no depletion region in the gate P-GaN layer 51 is widened, so that holes are prevented from being emitted from the gate P-GaN layer 51 into the gate metal electrode 63.
In the embodiment of the present invention, the gate metal electrode 63 and the P-GaN field plate metal electrode 64 are formed simultaneously by the same process, and in other embodiments, the gate metal electrode and the P-GaN field plate metal electrode are made of different metals.
In the embodiment of the present invention, the source electrode 61 and the drain electrode 62 are simultaneously formed by the same process.
Capacitance C between the P-GaN field plate 52 and the drain 62 DS Is variable capacitance between the source 61 and the drain 62Voltage V DS When the voltage is more than 0, the P-i-n junction at the grid electrode 74 is reversely biased, the two-dimensional electron gas in the channel below the drain electrode 62 is depleted, the depletion region in the P-GaN field plate 52 expands to the upper surface of the P-GaN field plate 52, and the capacitance C between the P-GaN field plate 52 and the drain electrode 62 is increased DS The distance between the plates becomes larger, the distance is the sum of the thickness of the P-GaN field plate 52 and the width of the depletion region, and the P-GaN field plate 52 capable of being depleted enables the GaN device to experience C when the GaN device experiences high drain voltage DS And is smaller.
In the embodiment of the present invention, the method further includes: a dielectric layer 70 positioned on the surfaces of the gate metal electrode 63, the P-GaN field plate metal electrode 64, the source electrode 61, the drain electrode 62 and the barrier layer 40, a metal field plate 71 positioned between the gate 74 and the drain electrode 61 and on the surface of the dielectric layer 70, wherein the metal field plate 71 is electrically connected with the gate 74, the source electrode 61 or the drain electrode 62 through a metal interconnection layer, so that the potential of the metal field plate 71 is equal to that of the gate 74, the source electrode 61 or the drain electrode 62.
The metal field plate can further improve the withstand voltage and inhibit the current collapse by adjusting the electric field distribution of a channel region between the grid electrode and the drain electrode.
In other embodiments, further comprising: and forming a plurality of metal field plates between the grid and the drain and on the surface of the dielectric layer to further adjust the distribution of an electric field.
An embodiment of the present invention further provides a method for manufacturing a GaN device having a P-GaN field plate, and please refer to fig. 3, which is a flowchart of a method for manufacturing a GaN device having a P-GaN field plate according to an embodiment of the present invention, including:
step S01, providing a substrate 10, forming a GaN layer 20 on the surface of the substrate 10, and forming a barrier layer 40 on the surface of the GaN layer 20;
step S02, forming a grid electrode P-GaN layer 51 and a P-GaN field plate 52 on the surface of the barrier layer 40; forming a gate metal electrode 63 on the surface of the gate P-GaN layer 51 and a P-GaN field plate metal electrode 64 on the surface of the P-GaN field plate 52; forming a source electrode 61 and a drain electrode 62 on the surface of the barrier layer 40; the gate P-GaN layer 51 and the gate metal electrode 63 constitute a gate 74, the gate 74 being located between the source electrode 61 and the P-GaN field plate 52; the P-GaN field plate 52 is located between the gate 74 and the drain 62;
step S03, forming metal interconnection layers on the surfaces of the gate metal electrode 63, the P-GaN field plate metal electrode 64, the source electrode 61 and the drain electrode 62, and electrically connecting the source electrode 61 and the P-GaN field plate metal electrode 64 through the metal interconnection layers.
Specifically, step S01 is executed, please refer to fig. 4, a substrate 10 is provided, and a GaN layer 20 and a barrier layer 40 are sequentially formed on a surface of the substrate 10.
In an embodiment of the present invention, the substrate 10 is a silicon substrate, and in other embodiments, the substrate is a silicon carbide substrate, a sapphire substrate, or other suitable substrate.
In the embodiment of the present invention, the barrier layer 40 is an AlGaN barrier layer, and in other embodiments, the barrier layer is an InAlN barrier layer, an AlN barrier layer, or other barrier layers suitable for GaN devices.
Step S02 is executed, please refer to fig. 5, wherein P-GaN field plates 52 and a gate P-GaN layer 51 are formed on the surface of the barrier layer 40, and the specific process for forming the P-GaN field plates 52 and the gate P-GaN layer 51 includes: forming a P-GaN material layer on the surface of the barrier layer 40, forming a photoresist layer on the surface of the P-GaN material layer, exposing and developing the photoresist layer, etching the P-GaN material layer by using the exposed photoresist layer as a mask, and forming a P-GaN field plate 52 and a grid P-GaN layer 51, wherein the P-GaN field plate 52 is discontinuously distributed in a direction perpendicular to the channel direction, and the grid P-GaN layer 51 is continuously distributed in a direction perpendicular to the channel direction.
When the P-GaN field plates 52 are discontinuously distributed, the interval between two adjacent P-GaN field plates 52 is 1 nm-10 um, so that the current between the source and the drain normally flows when the GaN device is started.
The P-GaN field plate 52 is located between the gate 74 and the drain 62, and the gate 74 is located between the source 61 and the P-GaN field plate 52.
Referring to fig. 6, a gate metal electrode 63 is formed on the surface of the gate P-GaN layer 51, a P-GaN field plate metal electrode 64 is formed on the surface of the P-GaN field plate 52, and the gate metal electrode 63 and the P-GaN field plate metal electrode 64 are made of the same material and formed simultaneously by the same process.
In other embodiments, the gate metal electrode and the P-GaN field plate metal electrode are separately fabricated using different metal materials.
Referring to fig. 7, the source electrode 61 and the drain electrode 62 are formed on the surface of the barrier layer 40, and the source electrode 61 and the drain electrode 62 are made of the same material and formed simultaneously by the same process.
Step S03 is executed, please refer to fig. 8 to 9, fig. 8 is a schematic cross-sectional structure diagram of line1 of a GaN device with a P-GaN field plate according to an embodiment of the present invention, fig. 9 is a schematic cross-sectional structure diagram of line2 of a GaN device with a P-GaN field plate according to an embodiment of the present invention, a metal interconnection layer is formed on the surface of the gate metal electrode 63, the P-GaN field plate metal electrode 64, the source electrode 61 and the drain electrode 62, and the source electrode 61 and the P-GaN field plate metal electrode 64 are electrically connected through the metal interconnection layer.
In another embodiment of the present invention, please refer to fig. 10 to 12, which further includes: and forming a dielectric layer 70 on the surfaces of the gate metal electrode 63, the source electrode 61, the drain electrode 62, the P-GaN field plate metal electrode 64 and the barrier layer 40, and forming a metal field plate 71 between the gate 74 and the drain electrode 61 and on the surface of the dielectric layer 70.
The metal field plate can further improve the withstand voltage and inhibit the current collapse by adjusting the electric field distribution of a channel region between the grid electrode and the drain electrode.
In other embodiments, further comprising: and forming a plurality of metal field plates between the grid electrode and the drain electrode and on the surface of the dielectric layer to further adjust the electric field distribution.
Finally, it is to be noted that any modifications or equivalent substitutions of some or all of the technical features depending on the device structure of the present invention and the technical solutions of the examples may be made, and the obtained essence does not depart from the corresponding technical solutions of the present invention, and all of the technical features belong to the device structure of the present invention and the patent scope of the embodiments.
Claims (10)
1. A GaN device with a P-GaN field plate, comprising:
the GaN-based solar cell comprises a substrate, a GaN layer and a barrier layer, wherein the GaN layer is positioned on the surface of the substrate, the barrier layer is positioned on the surface of the GaN layer, and a two-dimensional electronic gas layer is arranged between the GaN layer and the barrier layer;
the grid electrode P-GaN layer, the P-GaN field plate, the source electrode and the drain electrode are positioned on the surface of the potential barrier layer, the grid electrode metal electrode is positioned on the surface of the grid electrode P-GaN layer, the P-GaN field plate metal electrode is positioned on the surface of the P-GaN field plate, and the grid electrode P-GaN layer and the grid electrode metal electrode on the surface of the grid electrode P-GaN layer form a grid electrode;
the P-GaN field plate is positioned between the grid electrode and the drain electrode, the grid electrode is positioned between the source electrode and the P-GaN field plate, a two-dimensional electron gas layer does not exist in a channel below the grid electrode and the P-GaN field plate, and the P-GaN field plates are discontinuously distributed in a direction perpendicular to the channel direction.
2. The GaN device of claim 1, wherein when the P-GaN field plates are intermittently distributed perpendicular to the channel direction, the spacing between two adjacent P-GaN field plates is 1nm to 10um.
3. The GaN device with the P-GaN field plate as claimed in claim 1, wherein the thickness of the barrier layer or the doping concentration of the gate P-GaN layer and the P-GaN field plate is adjusted so that the channel below the P-GaN field plate has no two-dimensional electron gas layer.
4. The GaN device with P-GaN field plate of claim 1, further comprising: the metal field plate is positioned between the grid and the drain electrode and positioned on the surface of the dielectric layer.
5. A manufacturing method of a GaN device with a P-GaN field plate is characterized by comprising the following steps:
providing a substrate, forming a GaN layer on the surface of the substrate, forming a barrier layer on the surface of the GaN layer, and arranging a two-dimensional electron gas layer between the GaN layer and the barrier layer;
forming a grid electrode P-GaN layer, a P-GaN field plate, a source electrode and the drain electrode on the surface of the barrier layer, forming a grid electrode metal electrode on the surface of the grid electrode P-GaN layer, forming a P-GaN field plate metal electrode on the surface of the P-GaN field plate, and forming a grid electrode by the grid electrode P-GaN layer and the grid electrode metal electrode on the surface of the grid electrode P-GaN layer;
the P-GaN field plate is formed between the grid electrode and the drain electrode, the grid electrode is formed between the source electrode and the P-GaN field plate, a two-dimensional electron gas layer does not exist in a channel below the grid electrode and the P-GaN field plate, and the P-GaN field plates are discontinuously distributed in a direction perpendicular to the channel direction.
6. The method of claim 5, wherein the P-GaN field plate and the gate P-GaN layer are formed simultaneously by the same process.
7. The method of claim 6, wherein the specific process for forming the P-GaN field plate and the gate P-GaN layer comprises: forming a P-GaN material layer on the surface of the barrier layer, forming a photoresist layer on the surface of the P-GaN material layer, exposing and developing the photoresist layer, etching the P-GaN material layer by using the exposed photoresist layer as a mask to form a P-GaN field plate and a grid P-GaN layer, wherein the P-GaN field plate is discontinuously distributed in a direction perpendicular to the channel direction, and the grid P-GaN layer is continuously distributed in a direction perpendicular to the channel direction.
8. The method of claim 5, wherein the gate metal electrode and the P-GaN field plate metal electrode are formed simultaneously by the same process or are fabricated separately from different metals.
9. The method of claim 5, wherein the source electrode and the drain electrode are formed simultaneously using the same process.
10. The method of claim 5, further comprising: and forming dielectric layers on the surfaces of the grid metal electrode, the P-GaN field plate metal electrode, the source electrode, the drain electrode and the barrier layer, and forming a metal field plate between the grid and the drain electrode and on the surface of the dielectric layer.
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