CN115411105B - GaN device with P-GaN field plate and manufacturing method - Google Patents
GaN device with P-GaN field plate and manufacturing method Download PDFInfo
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- 239000002184 metal Substances 0.000 claims abstract description 85
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- 230000004888 barrier function Effects 0.000 claims abstract description 50
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims description 24
- 239000008186 active pharmaceutical agent Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 description 18
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- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000005684 electric field Effects 0.000 description 5
- 229910002704 AlGaN Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- 239000007769 metal material Substances 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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Abstract
The present invention relates to the field of GaN devices. The invention provides a GaN device with a P-GaN field plate and a manufacturing method thereof, wherein the P-GaN field plate is directly formed on the surface of a barrier layer, a channel below the P-GaN field plate has no two-dimensional electron gas layer, the P-GaN field plate is discontinuously distributed in the direction perpendicular to the channel, and the discontinuous position is provided with the two-dimensional electron gas layer, so that the current between a source electrode and a drain electrode is normally conducted, and the GaN device can be ensured to work normally. When the GaN device experiences high drain voltage, the P-GaN field plate is rapidly pinched off, and the voltage difference between the grid electrode and the drain electrode is almost completely reduced between the P-GaN field plate and the drain electrode, so that the P-i-n junction at the grid electrode has small bearing pressure, and holes are prevented from being emitted from the P-GaN layer of the grid electrode to the metal electrode of the grid electrode, thereby overcoming the problem of dynamic threshold voltage drift of the GaN device.
Description
Technical Field
The invention relates to the field of GaN devices, in particular to a GaN device with a P-GaN field plate and a manufacturing method thereof.
Background
Referring to fig. 1, the conventional GaN device has a serious problem of dynamic threshold voltage. When a GaN device experiences a high drain voltage, holes are emitted from the gate P-GaN layer into the gate metal electrode, resulting in a reduction of positive charge in the gate P-GaN layer; after the device is turned on again, the positive charges reduced in the grid electrode P-GaN layer cannot be recovered immediately, and a larger grid electrode voltage is needed to turn on the GaN device, so that the threshold voltage shifts forward. The common solution is to add a metal field plate on the surface of the dielectric layer, balance electric field distribution by using the metal field plate, and reduce the p-i-n junction withstand voltage at the gate electrode, thereby inhibiting the threshold voltage drift phenomenon.
The metal field plate of the traditional GaN device is formed on the surface of the dielectric layer of the GaN device, and the metal field plate cannot be in direct contact with the barrier layer, so that the defect is that the pinch-off voltage of the metal field plate is large, namely the threshold voltage of MIS-HEMT formed by the dielectric layer below the metal field plate-AlGaN/GaN heterojunction is large, and is generally different from tens to hundreds of volts. Before the metal field plate is clamped off, the voltage V between the grid electrode and the drain electrode DG The P-i-n junction at the gate is still required to bear, the gate P-The GaN layer will still be depleted to some extent, resulting in holes being emitted from the gate P-GaN layer into the gate metal electrode, and the problem of dynamic threshold voltage still remains.
Disclosure of Invention
The invention provides a GaN device with a P-GaN field plate and a manufacturing method thereof, aiming at solving the technical problem that a GaN device faces a dynamic threshold voltage.
To achieve the above object, the present invention provides a GaN device having a P-GaN field plate, comprising:
the substrate, the GaN layer located on the surface of the substrate, the barrier layer located on the surface of the GaN layer, the two-dimensional electron gas layer between the GaN layer and the barrier layer;
the grid electrode P-GaN layer, the P-GaN field plate, the source electrode and the drain electrode are positioned on the surface of the barrier layer, the grid electrode metal electrode is positioned on the surface of the grid electrode P-GaN layer, the P-GaN field plate metal electrode is positioned on the surface of the P-GaN field plate, and the grid electrode metal electrode on the surface of the grid electrode P-GaN layer form a grid electrode;
the P-GaN field plate is located between the grid electrode and the drain electrode, the grid electrode is located between the source electrode and the P-GaN field plate, a channel below the grid electrode and the P-GaN field plate has no two-dimensional electron gas layer, and the P-GaN field plate is discontinuously distributed in the direction perpendicular to the channel direction.
Optionally, when the P-GaN field plates are intermittently distributed perpendicular to the channel direction, the interval between two adjacent P-GaN field plates is 1 nm-10 um.
Optionally, the thickness of the barrier layer or the doping concentration of the grid electrode P-GaN layer and the P-GaN field plate are adjusted so that a channel below the P-GaN field plate has no two-dimensional electron gas layer.
Optionally, the method further comprises: the dielectric layer is positioned on the surfaces of the gate metal electrode, the P-GaN field plate metal electrode, the source electrode, the drain electrode and the barrier layer, and the metal field plate is positioned between the gate and the drain electrode and on the surface of the dielectric layer.
The invention provides a manufacturing method of a GaN device with a P-GaN field plate, which comprises the following steps:
providing a substrate, forming a GaN layer on the surface of the substrate, forming a barrier layer on the surface of the GaN layer, and forming a two-dimensional electron gas layer between the GaN layer and the barrier layer;
forming a grid P-GaN layer, a P-GaN field plate, a source electrode and a drain electrode on the surface of the barrier layer, forming a grid metal electrode on the surface of the grid P-GaN layer, forming a P-GaN field plate metal electrode on the surface of the P-GaN field plate, and forming a grid by the grid P-GaN layer and the grid metal electrode on the surface of the grid P-GaN layer;
the P-GaN field plate is formed between the grid electrode and the drain electrode, the grid electrode is formed between the source electrode and the P-GaN field plate, a channel below the grid electrode and the P-GaN field plate has no two-dimensional electron gas layer, and the P-GaN field plate is discontinuously distributed in the direction perpendicular to the channel direction.
Optionally, the P-GaN field plate and the gate P-GaN layer are formed simultaneously by the same process.
Optionally, the specific process for forming the P-GaN field plate and the gate P-GaN layer includes: and forming a P-GaN material layer on the surface of the barrier layer, forming a photoresist layer on the surface of the P-GaN material layer, exposing and developing the photoresist layer, and etching the P-GaN material layer by using the exposed photoresist layer as a mask to form a P-GaN field plate and a grid P-GaN layer, wherein the P-GaN field plate is discontinuously distributed in the direction perpendicular to the channel direction, and the grid P-GaN layer is continuously distributed in the direction perpendicular to the channel direction.
Optionally, the gate metal electrode and the P-GaN field plate metal electrode are formed simultaneously by the same process or are prepared by different metals respectively.
Optionally, the source electrode and the drain electrode are formed simultaneously by the same process.
Optionally, the method further comprises: and forming a dielectric layer on the surfaces of the gate metal electrode, the P-GaN field plate metal electrode, the source electrode and the drain electrode and the barrier layer, and forming a metal field plate between the gate and the drain electrode and on the surface of the dielectric layer.
In summary, the invention has the advantages that:
according to the invention, the P-GaN field plate is directly formed on the surface of the barrier layer, and because the P-GaN field plate is directly contacted with the barrier layer, the pinch-off voltage is smaller than that of a metal field plate in the traditional technology, when a GaN device experiences high drain voltage, the P-GaN field plate is rapidly pinched off, the voltage difference between the grid electrode and the drain electrode almost drops between the P-GaN field plate and the drain electrode, the P-i-n junction at the grid electrode has small bearing pressure due to the shielding of the P-GaN field plate, the grid electrode has little depletion region broadening, holes are prevented from being emitted from the grid electrode P-GaN layer into the grid electrode metal electrode, and compared with the traditional metal field plate, the P-GaN field plate can effectively inhibit the concentration of a P-i-n junction at the grid electrode, so that the problem of dynamic threshold voltage drift is solved.
In the invention, as the channel below the P-GaN field plate has no two-dimensional electron gas layer, in order to ensure that the GaN device can work normally, the P-GaN field plate is discontinuously distributed in the direction perpendicular to the channel, and the discontinuous position is provided with the two-dimensional electron gas layer, so that the current between the source electrode and the drain electrode is conducted normally, thereby ensuring that the GaN device can work normally.
Further, C between the P-GaN field plate and the drain electrode DS As a variable capacitance, when the voltage V between the source and the drain DS When the current is more than 0, the P-i-n junction at the grid electrode is reversely biased, two-dimensional electron gas in a channel below the drain electrode is exhausted, and meanwhile, a depletion region in the P-GaN field plate expands towards the upper surface of the P-GaN field plate; when the voltage V between the source and the drain DS When larger, the depletion region in the P-GaN field plate is almost completely depleted, and the capacitance C between the source and the drain DS Upper polar plate of the barrier layer extends upwards from the contact surface of the P-GaN field plate to the upper surface of the P-GaN field plate, and the capacitance C between the source electrode and the drain electrode DS The distance between the polar plates becomes larger, the distance is the sum of the thickness of the P-GaN field plate and the width of the depletion region, and the P-GaN field plate enables the capacitance C between the source electrode and the drain electrode when the GaN device experiences high drain electrode voltage DS And the working frequency of the GaN device is improved, the system volume is reduced, the system power density is improved, and the efficiency of the converter is improved.
Drawings
Fig. 1 is a schematic cross-sectional structure of a conventional GaN device;
FIG. 2 is a schematic top view of a GaN device with a P-GaN field plate according to an embodiment of the invention;
FIG. 3 is a schematic flow chart of a method for fabricating a GaN device with a P-GaN field plate according to an embodiment of the invention;
FIGS. 4 to 8 are schematic cross-sectional views showing a process of fabricating line1 of a GaN device having a P-GaN field plate according to an embodiment of the invention;
FIG. 9 is a schematic diagram showing a cross-sectional structure of line2 of a GaN device with a P-GaN field plate according to an embodiment of the invention;
FIG. 10 is a top view of a GaN device with a P-GaN field plate according to another embodiment of the invention;
FIG. 11 is a schematic cross-sectional view of line3 of a GaN device with a P-GaN field plate according to another embodiment of the invention;
fig. 12 is a schematic cross-sectional view of line4 of a GaN device with a P-GaN field plate according to another embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples for the purpose of facilitating understanding to those skilled in the art.
An embodiment of the present invention provides a GaN device having a P-GaN field plate, please refer to fig. 2, including:
a substrate 10, a GaN layer 20 positioned on the surface of the substrate 10, a barrier layer 40 positioned on the surface of the GaN layer 20, and a two-dimensional electron gas layer 30 between the GaN layer 20 and the barrier layer 40;
the gate electrode P-GaN layer 51, the P-GaN field plate 52, the source electrode 61 and the drain electrode 62 which are positioned on the surface of the barrier layer 40, the gate metal electrode 63 which is positioned on the surface of the gate electrode P-GaN layer 51, the P-GaN field plate metal electrode 64 which is positioned on the surface of the P-GaN field plate 52, and the gate electrode metal electrode 63 which is positioned on the surface of the gate electrode P-GaN layer 51 and the gate electrode P-GaN layer 51 form a gate 74;
the P-GaN field plate 52 is located between the gate 74 and the drain 62, the gate 74 is located between the source 61 and the P-GaN field plate 52, the channel non-two-dimensional electron gas layer 30 is located below the gate 74 and the P-GaN field plate 52, and the P-GaN field plate 52 is intermittently distributed perpendicular to the channel direction;
and the metal interconnection layers are positioned on the surfaces of the gate metal electrode 63, the P-GaN field plate metal electrode 64, the source electrode 61 and the drain electrode 62, and the source electrode 61 and the P-GaN field plate metal electrode 64 are electrically connected through the metal interconnection layers.
Specifically, in the embodiment of the present invention, the substrate 10 is a silicon substrate, and in other embodiments, the substrate is a silicon carbide substrate, a sapphire substrate, or other suitable substrate.
In the embodiment of the present invention, the barrier layer 40 is an AlGaN barrier layer, and in other embodiments, the barrier layer is a barrier layer suitable for a GaN device, such as an InAlN barrier layer, an AlN barrier layer, or the like.
In the embodiment of the present invention, when the P-GaN field plates 52 are intermittently distributed in the direction perpendicular to the channel, the interval between two adjacent P-GaN field plates 52 is 1 nm-10 um, so that the current between the source and the drain normally flows when the GaN device is turned on.
The thickness of the barrier layer 40 or the doping concentration of the grid P-GaN layer 51 and the P-GaN field plate 52 are adjusted so that a channel below the P-GaN field plate 52 is free of the two-dimensional electron gas layer 30. The barrier layer 40 is relatively thin so that when no bias voltage is applied to the GaN device source 61, the channel under the gate 74 and the channel under the P-GaN field plate 52 do not have the two-dimensional electron gas layer 30, resulting in a normally-off feature of the device.
In the embodiment of the present invention, the P-GaN field plate 52 and the gate P-GaN layer 51 are formed simultaneously by the same process.
In the embodiment of the present invention, the specific process for forming the P-GaN field plate 52 and the gate P-GaN layer 51 includes: a P-GaN material layer is formed on the surface of the barrier layer 40, a photoresist layer is formed on the surface of the P-GaN material layer, the photoresist layer is exposed and developed, the P-GaN material layer is etched by using the exposed photoresist layer as a mask, and the P-GaN field plate 52 and the gate P-GaN layer 51 are formed, wherein the P-GaN field plate 52 is discontinuously distributed in a direction perpendicular to the channel direction, and the gate P-GaN layer 51 is continuously distributed in a direction perpendicular to the channel direction.
The P-GaN field plate 52 is formed on the surface of the barrier layer 40 and is in direct contact with the barrier layer 40, when the GaN device experiences a high drain voltage, the pinch-off voltage of the P-GaN field plate 52 is far smaller than that of a metal field plate in a conventional device, the P-GaN field plate 52 is rapidly pinched off, the voltage difference between the gate 74 and the drain 62 is almost completely located between the P-GaN field plate 52 and the drain 62, the P-i-n junction pressure at the gate 74 is small, and there is almost no depletion region broadening in the gate P-GaN layer 51, avoiding holes from being emitted from the gate P-GaN layer 51 into the gate metal electrode 63.
In the embodiment of the present invention, the gate metal electrode 63 and the P-GaN field plate metal electrode 64 are formed simultaneously by the same process, and in other embodiments, the gate metal electrode and the P-GaN field plate metal electrode are respectively made of different metals.
In the embodiment of the present invention, the source electrode 61 and the drain electrode 62 are formed simultaneously by the same process.
Capacitance C between the P-GaN field plate 52 and the drain 62 DS As a variable capacitance, when the voltage V between the source 61 and the drain 62 DS At > 0, the P-i-n junction at the gate 74 is reverse biased, the two-dimensional electron gas in the channel under the drain 62 is depleted, the depletion region in the P-GaN field plate 52 expands towards the upper surface of the P-GaN field plate 52, and the capacitance C between the P-GaN field plate 52 and the drain 62 DS The distance between the polar plates becomes larger, the distance is the sum of the thickness of the P-GaN field plate 52 and the width of the depletion region, and the depletable P-GaN field plate 52 enables C to be achieved when the GaN device experiences high drain voltage DS Smaller.
In an embodiment of the present invention, the method further includes: dielectric layer 70 on the gate metal electrode 63, P-GaN field plate metal electrode 64, source electrode 61, drain electrode 62 and barrier layer 40, metal field plate 71 between gate 74 and drain electrode 61 and on the surface of dielectric layer 70, and metal interconnection layer electrically connects metal field plate 71 with gate 74, source electrode 61 or drain electrode 62, so that the potential of metal field plate 71 is equal to that of gate 74, source electrode 61 or drain electrode 62.
The metal field plate can further improve withstand voltage and inhibit current collapse by adjusting the electric field distribution of a channel region between the gate and the drain.
In other embodiments, further comprising: and forming a plurality of metal field plates between the grid electrode and the drain electrode and on the surface of the dielectric layer, and further adjusting electric field distribution.
The embodiment of the invention also provides a method for manufacturing a GaN device with a P-GaN field plate, please refer to FIG. 3, which is a flowchart of a method for manufacturing a GaN device with a P-GaN field plate, comprising:
step S01, providing a substrate 10, forming a GaN layer 20 on the surface of the substrate 10, and forming a barrier layer 40 on the surface of the GaN layer 20;
step S02, forming a grid P-GaN layer 51 and a P-GaN field plate 52 on the surface of the barrier layer 40; forming a gate metal electrode 63 on the surface of the gate P-GaN layer 51 and forming a P-GaN field plate metal electrode 64 on the surface of the P-GaN field plate 52; forming a source electrode 61 and a drain electrode 62 on the surface of the barrier layer 40; the gate P-GaN layer 51 and the gate metal electrode 63 constitute a gate 74, the gate 74 being located between the source 61 and the P-GaN field plate 52; the P-GaN field plate 52 is located between the gate 74 and the drain 62;
in step S03, a metal interconnection layer is formed on the gate metal electrode 63, the P-GaN field plate metal electrode 64, the surface of the source electrode 61 and the surface of the drain electrode 62, and the source electrode 61 and the P-GaN field plate metal electrode 64 are electrically connected through the metal interconnection layer.
Specifically, in step S01, referring to fig. 4, a substrate 10 is provided, and a GaN layer 20 and a barrier layer 40 are sequentially formed on the surface of the substrate 10.
In the present embodiment, the substrate 10 is a silicon substrate, and in other embodiments the substrate is a silicon carbide substrate, a sapphire substrate, or other suitable substrate.
In the embodiment of the present invention, the barrier layer 40 is an AlGaN barrier layer, and in other embodiments, the barrier layer is a barrier layer suitable for a GaN device, such as an InAlN barrier layer, an AlN barrier layer, or the like.
Referring to fig. 5, referring to step S02, a P-GaN field plate 52 and a gate P-GaN layer 51 are formed on the surface of the barrier layer 40, and the specific process for forming the P-GaN field plate 52 and the gate P-GaN layer 51 includes: a P-GaN material layer is formed on the surface of the barrier layer 40, a photoresist layer is formed on the surface of the P-GaN material layer, the photoresist layer is exposed and developed, the P-GaN material layer is etched by using the exposed photoresist layer as a mask, and the P-GaN field plate 52 and the gate P-GaN layer 51 are formed, wherein the P-GaN field plate 52 is discontinuously distributed in a direction perpendicular to the channel direction, and the gate P-GaN layer 51 is continuously distributed in a direction perpendicular to the channel direction.
When the P-GaN field plates 52 are intermittently distributed, the interval between two adjacent P-GaN field plates 52 is 1 nm-10 um, so that the current between the source and the drain normally flows when the GaN device is turned on.
The P-GaN field plate 52 is located between the gate 74 and the drain 62, and the gate 74 is located between the source 61 and the P-GaN field plate 52.
Referring to fig. 6, a gate metal electrode 63 is formed on the surface of the gate P-GaN layer 51, a P-GaN field plate metal electrode 64 is formed on the surface of the P-GaN field plate 52, the gate metal electrode 63 and the P-GaN field plate metal electrode 64 are made of the same material and are formed simultaneously by the same process.
In other embodiments, the gate metal electrode and the P-GaN field plate metal electrode are separately prepared using different metal materials.
Referring to fig. 7, the source electrode 61 and the drain electrode 62 are formed on the surface of the barrier layer 40, and the source electrode 61 and the drain electrode 62 are formed simultaneously by the same process.
Referring to fig. 8 to 9, fig. 8 is a schematic cross-sectional structure of line1 of a GaN device with a P-GaN field plate according to an embodiment of the invention, and fig. 9 is a schematic cross-sectional structure of line2 of a GaN device with a P-GaN field plate according to an embodiment of the invention, wherein metal interconnection layers are formed on the gate metal electrode 63, the P-GaN field plate metal electrode 64, the source electrode 61 and the drain electrode 62, and the source electrode 61 and the P-GaN field plate metal electrode 64 are electrically connected through the metal interconnection layers.
In another embodiment of the present invention, please refer to fig. 10-12, further comprising: dielectric layers 70 are formed on the surfaces of the gate metal electrode 63, the source electrode 61, the drain electrode 62, the P-GaN field plate metal electrode 64, and the barrier layer 40, and a metal field plate 71 is formed between the gate 74 and the drain electrode 61 and on the surface of the dielectric layers 70.
The metal field plate can further improve withstand voltage and inhibit current collapse by adjusting the electric field distribution of a channel region between the gate and the drain.
In other embodiments, further comprising: and forming a plurality of metal field plates between the grid electrode and the drain electrode and on the surface of the dielectric layer, and further adjusting electric field distribution.
Finally, any modification or equivalent replacement of some or all technical features by means of the device structure of the present invention and the technical solutions of the examples described, without departing from the corresponding technical solutions of the present invention, shall fall within the scope of the device structure of the present invention and the patent claims of the embodiments described.
Claims (4)
1. A GaN device having a P-GaN field plate, comprising:
the substrate, the GaN layer located on the surface of the substrate, the barrier layer located on the surface of the GaN layer, the two-dimensional electron gas layer between the GaN layer and the barrier layer;
the grid electrode P-GaN layer, the P-GaN field plate, the source electrode and the drain electrode are positioned on the surface of the barrier layer, the grid electrode metal electrode is positioned on the surface of the grid electrode P-GaN layer, the P-GaN field plate metal electrode is positioned on the surface of the P-GaN field plate, and the grid electrode metal electrode on the surface of the grid electrode P-GaN layer form a grid electrode;
the P-GaN field plate is positioned between the grid electrode and the drain electrode, the grid electrode is positioned between the source electrode and the P-GaN field plate, a channel below the grid electrode and the P-GaN field plate has no two-dimensional electron gas layer, and the P-GaN field plate is discontinuously distributed in a direction perpendicular to the channel direction;
a P-GaN field plate metal electrode positioned on the grid metal electrodeThe source electrode and the P-GaN field plate metal electrode are electrically connected through the metal interconnection layer; wherein, the capacitance C between the P-GaN field plate and the drain electrode DS For variable capacitance, when the voltage V between the source and the drain DS When the current is more than 0, the P-i-n junction at the grid electrode is reversely biased, two-dimensional electron gas in a channel below the drain electrode is exhausted, and meanwhile, a depletion region in the P-GaN field plate expands towards the upper surface of the P-GaN field plate; when the voltage V between the source and the drain DS When larger, the depletion region in the P-GaN field plate is almost completely depleted, and the capacitance C between the source and the drain DS Upper polar plate of the barrier layer extends upwards from the contact surface of the P-GaN field plate to the upper surface of the P-GaN field plate, and the capacitance C between the source electrode and the drain electrode DS The distance between the polar plates becomes larger, the distance is the sum of the thickness of the P-GaN field plate and the width of the depletion region, and the P-GaN field plate enables the capacitance C between the source electrode and the drain electrode when the GaN device experiences high drain electrode voltage DS And the working frequency of the GaN device is improved, the system volume is reduced, the system power density is improved, and the efficiency of the converter is improved.
2. The GaN device of claim 1 wherein when said P-GaN field plates are intermittently distributed perpendicular to the channel direction, the spacing between adjacent P-GaN field plates is 1nm to 10um.
3. The GaN device of claim 1 wherein the thickness of the barrier layer or the doping concentration of the gate P-GaN layer, P-GaN field plate is adjusted such that the channel under the P-GaN field plate is free of two-dimensional electron gas layers.
4. The GaN device with P-GaN field plate of claim 1, further comprising: the dielectric layer is positioned on the surfaces of the gate metal electrode, the P-GaN field plate metal electrode, the source electrode, the drain electrode and the barrier layer, and the metal field plate is positioned between the gate and the drain electrode and on the surface of the dielectric layer.
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| CN109728079A (en) * | 2018-12-04 | 2019-05-07 | 北京大学深圳研究生院 | A kind of transistor and preparation method thereof |
| CN110649096A (en) * | 2019-10-08 | 2020-01-03 | 电子科技大学 | High-voltage n-channel HEMT device |
| CN110660851A (en) * | 2019-10-08 | 2020-01-07 | 电子科技大学 | High-voltage n-channel HEMT device |
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| CN109728079A (en) * | 2018-12-04 | 2019-05-07 | 北京大学深圳研究生院 | A kind of transistor and preparation method thereof |
| CN110649096A (en) * | 2019-10-08 | 2020-01-03 | 电子科技大学 | High-voltage n-channel HEMT device |
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