CN115410631A

CN115410631A - Sealed chip, using method, equipment and medium

Info

Publication number: CN115410631A
Application number: CN202211090904.9A
Authority: CN
Inventors: 胡民; 韩西领; 张明明; 许龙飞; 康天奇; 肖自铧
Original assignee: Lianyun Technology Hangzhou Co ltd
Current assignee: Lianyun Technology Hangzhou Co ltd
Priority date: 2022-09-07
Filing date: 2022-09-07
Publication date: 2022-11-29

Abstract

Disclosed are a sealed chip, a method of use, an apparatus and a medium, the sealed chip comprising: the memory controller comprises a first pin, a second pin and a third pin, wherein the first pin is used for receiving a read/write operation request of an external device; the memory controller is connected with the at least one memory, the memory controller performs read/write operation on the at least one memory according to the read/write operation request, the at least one memory shares a second pin, and the second pin is used for reading data from the at least one memory and/or writing the data into the at least one memory; and the sealing pin is connected with external equipment, the function of sealing the chip is realized when the first pin is connected with the sealing pin, and the function of at least one memory is realized when the second pin is connected with the sealing pin. The embodiment of the disclosure expands the application scene of the sealed chip, reduces the resource waste of the sealed chip, and improves the resource utilization rate of the sealed chip.

Description

Sealed chip, using method, equipment and medium

Technical Field

The present disclosure relates to the field of semiconductor integrated circuit technology, and more particularly, to a packaged chip, a method of use, an apparatus, and a medium.

Background

With the development of science and technology, more and more products are developed towards the direction of intellectualization, and the development of the chip market is promoted. While the early days were limited by technology, finished chips were usually packaged from one chip, multi-chip package technology is now available that can package multiple chips together. A chip manufactured by the multi-chip sealing technology is referred to as a sealing chip, and pins led out of the sealing chip are referred to as sealing pins. The sealing chip seals a plurality of chips together to be used as a special chip, and usually leads out related pins to the outside of the sealing chip according to a communication interface protocol to be used as sealing pins. Therefore, the sealed chip can only be used as a special chip after being packaged, and when part of functions in the sealed chip are damaged or the original application scene is not needed any more because of supply and demand relations, the sealed chip can only be discarded for use, so that certain resource waste is caused, and the resource utilization rate of the sealed chip is reduced.

Disclosure of Invention

In order to overcome the problems in the related art, the embodiments of the present disclosure provide a sealed chip, a method, a device, and a medium, which expand the application scenarios of the sealed chip, reduce the waste of resources of the sealed chip, and improve the resource utilization rate of the sealed chip.

According to a first aspect of the embodiments of the present disclosure, there is provided a sealed chip, including:

the memory controller comprises a first pin, a second pin and a third pin, wherein the first pin is used for receiving a read/write operation request of an external device;

the memory controller is connected with the at least one memory, the memory controller performs read/write operation on the at least one memory according to the read/write operation request, the at least one memory shares a second pin, and the second pin is used for reading data from the at least one memory and/or writing data into the at least one memory;

and the sealing pin is connected with the external equipment, the function of the sealing chip is realized when the first pin is connected with the sealing pin, and the function of the at least one memory is realized when the second pin is connected with the sealing pin.

Optionally, the sealed chip further comprises a multiplexer,

the multiplexer comprises an input end, an output end and a control end, the input end is connected with the first pin and the second pin, the output end is connected with the sealing pin, the control end is used for receiving a control signal, the output end is connected with the first pin or the second pin through the input end according to the control signal,

when the output end is connected with the first pin, the function of the sealed chip is realized;

when the output is connected to the second pin, the function of the at least one memory is implemented.

Optionally, each memory of the at least one memory includes a third pin for reading data from the memory and/or writing data to the memory, the seal chip further includes a multiplexer,

the multiplexer comprises an input end, an output end and a control end, the input end is connected with the first pin and the third pin of each memory in the at least one memory, the output end is connected with the sealing pin, the control end is used for receiving a control signal, the output end is connected with the first pin or the third pin through the input end according to the control signal,

and when the output end is connected with the third pin, the corresponding function of the memory is realized.

Optionally, the sealing pins include a first sealing pin and a second sealing pin, the first pin is connected to the first sealing pin, the second pin is connected to the second sealing pin,

when the first sealing pin is connected with the external equipment and the second sealing pin is suspended, the function of the sealing chip is realized,

and when the second seal pin is connected with the external equipment and the first seal pin is suspended, the function of the at least one memory is realized.

Optionally, each memory in the at least one memory includes a third pin, the third pin is used for reading data from the memory and/or writing data into the memory, the seal pin includes a first seal pin and at least one third seal pin, the first pin is connected to the first seal pin, the third pin of each memory in the at least one memory is respectively connected to the third seal pin,

when the first sealing pin is connected with the external equipment and other sealing pins are suspended, the function of the sealing chip is realized,

and when the third sealing pin is connected with the external equipment and other sealing pins are suspended, the corresponding function of the memory is realized.

According to a second aspect of the embodiments of the present disclosure, there is provided a method for using a sealed chip, where the sealed chip includes a memory controller, at least one memory, and a sealed pin, the memory controller includes a first pin, the first pin is configured to receive a read/write operation request from an external device, the memory controller is connected to the at least one memory, the memory controller performs a read/write operation on the at least one memory according to the read/write operation request, the at least one memory shares a second pin, the second pin is configured to read data from the at least one memory and/or write data into the at least one memory, and the sealed pin is connected to the external device, the method includes:

connecting the first pin with the sealing pin to realize the function of the sealing chip;

and connecting the second pin with the seal pin to realize the function of the at least one memory.

Optionally, the package chip further includes a multiplexer, the multiplexer includes an input end, an output end, and a control end, the input end is connected to the first pin and the second pin, the output end is connected to the package pin, the control end is configured to receive a control signal, and according to the control signal, the output end is connected to the first pin or the second pin through the input end, and the using method includes:

connecting the output end with the first pin to realize the function of the sealed chip;

connecting the output terminal to the second pin to implement the function of the at least one memory.

Optionally, each memory in the at least one memory includes a third pin, the third pin is configured to read data from the memory and/or write data into the memory, the seal chip further includes a multiplexer, the multiplexer includes an input terminal, an output terminal, and a control terminal, the input terminal is connected to the first pin and the third pin of each memory in the at least one memory, the output terminal is connected to the seal pin, the control terminal is configured to receive a control signal, and according to the control signal, the output terminal is connected to the first pin or the third pin through the input terminal, and the using method includes:

and connecting the output end with the third pin to realize the function of the corresponding memory.

Optionally, the sealing pins include a first sealing pin and a second sealing pin, the first pin is connected to the first sealing pin, and the second pin is connected to the second sealing pin, and the using method includes:

connecting the first sealing pin with the external device, suspending the second sealing pin to realize the function of the sealing chip,

and connecting the second sealing pin with the external equipment, and suspending the first sealing pin to realize the function of the at least one memory.

Optionally, each memory in the at least one memory includes a third pin, the third pin is used for reading data from the memory and/or writing data into the memory, the seal pin includes a first seal pin and at least one third seal pin, the first pin is connected to the first seal pin, and the third pin of each memory in the at least one memory is respectively connected to the third seal pin, where the use method includes:

connecting the first sealing pin with the external device, suspending other sealing pins to realize the function of the sealing chip,

and connecting the third sealing pin with the external equipment, and suspending other sealing pins to realize the function of the corresponding memory.

According to a third aspect of an embodiment of the present disclosure, there is provided an electronic apparatus including:

the encapsulated chip of any of the preceding claims.

According to a fourth aspect of embodiments of the present disclosure, there is provided a computer apparatus comprising:

a memory for storing computer executable code;

a processor for executing the computer executable code to implement the method described above.

According to a fifth aspect of embodiments of the present disclosure, there is provided a computer-readable medium comprising computer-executable code that, when executed by a processor, implements the method described above.

The sealed chip comprises a memory controller, at least one memory and sealed pins, wherein the memory controller comprises a first pin used for receiving a read/write operation request of an external device, the memory controller is connected with the at least one memory, the memory controller performs read/write operation on the at least one memory according to the read/write operation request, the at least one memory shares a second pin, the second pin is used for reading data from the at least one memory and/or writing the data into the at least one memory, the sealed pins are connected with the external device, when the first pin is connected with the sealed pins, the function of the sealed chip is realized, and when the second pin is connected with the sealed pins, the function of the at least one memory is realized as a whole.

Drawings

The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following description of embodiments of the disclosure, which refers to the accompanying drawings in which:

FIG. 1 shows a schematic structural diagram of a sealed chip according to one embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of an internal structure of a sealed chip according to an embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of the internal structure of a sealed chip according to one embodiment of the present disclosure;

FIG. 4 shows a schematic diagram of the internal structure of a sealed chip according to an embodiment of the present disclosure;

FIG. 5 shows a schematic diagram of an internal structure of a sealed chip according to one embodiment of the present disclosure;

FIG. 6 shows a flow diagram of a method of using a sealed chip according to one embodiment of the present disclosure;

FIG. 7 shows a schematic structural diagram of an electronic device according to one embodiment of the present disclosure;

FIG. 8 shows a schematic structural diagram of a computer device according to one embodiment of the present disclosure.

Detailed Description

The present disclosure is described below based on examples, but the present disclosure is not limited to only these examples. In the following detailed description of the present disclosure, some specific details are set forth in detail. It will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the essence of the present disclosure. Further, the figures are not necessarily to scale, with like numerals referring to the same or similar elements throughout the figures.

Fig. 1 shows a schematic structural diagram of a sealed chip according to an embodiment of the present disclosure. As shown in fig. 1, the sealed chip 100 includes: the memory controller 110, the at least one memory 120, the seal pin 130, the substrate 140, and the housing 150, n is a positive integer and greater than 1. Note that, for convenience of description, only one memory 120 is shown in fig. 1. The sealed chip 100 is a dedicated chip formed by system-in-package the memory controller 110 and the at least one memory 120 by using a multi-chip sealing technology. In some embodiments, the memory controller 110 is, for example, a microprocessor, an FPGA (field-programmable gate array), or the like. The memory 120 is, for example, a flash memory or the like. The sealing chip 100 may be implemented as a dedicated embedded multimedia Card (eMMC) sealing chip, a Universal Flash Storage (UFS) sealing chip, or the like.

In some embodiments, as shown in fig. 1, the memory controller 110, the at least one memory 120, and the housing 150 are disposed on a first surface of the substrate 140. The memory controller 110 and the at least one chip 120 are located within a cavity of the housing 150, and the housing 150 isolates the memory controller 110 and the at least one memory 120 from the outside. The memory controller 110 includes a first pin 111, the first pin 111 receives a read/write operation request of an external device, and an internal function circuit of the memory controller 110 is connected to the first pin 111. The memory controller 110 and the at least one memory 120 are connected by a data transmission line 141. The memory controller 110 performs a read/write operation on the at least one memory 120 according to the read/write operation request. The at least one memory 120 shares a second pin (not shown) for reading data from the at least one memory 120 and/or writing data to the at least one memory 120 with the at least one memory 120 as a whole. In some embodiments, each memory 120 includes a third pin 121, and the internal functional circuitry of each memory 120 is coupled to the third pin 121.

In some embodiments, as shown in fig. 1, the sealing pin 130 is disposed on the second surface of the substrate 140, and the sealing pin 130 is connected to an external device. In some embodiments, when the first pin 111 of the memory controller 110 is connected to the encapsulation pin 130, the first pin 111 of the memory controller 110 is connected to an external device, so as to implement the function of the encapsulated chip 100. In some embodiments, when the second pin (not shown) of the at least one memory 120 is connected to the seal pin 130, the second pin of the at least one memory 120 is connected to an external device, and the at least one memory 120 as a whole implements the function of the at least one memory 120. In some embodiments, when the third pin 121 of the memory 120 is connected to the seal pin 130, the third pin 121 of the memory 120 is connected to an external device, so as to implement the corresponding function of the memory 120. That is to say, the sealed chip 100 of the embodiment of the present disclosure is a multifunctional chip that can be applied to a plurality of application scenarios, and when part of functions of the sealed chip 100 are damaged or the original application scenario is no longer needed because of the supply and demand relationship, the sealed chip 100 may also be applied to an application scenario in which at least one memory 120 is used as a whole and other application scenarios in which a single memory 120 is used.

UFS memory chip particles are chips widely used in mobile phone products; the NAND Flash controller chip and the NAND Flash memory chip are packaged together. Only the relevant pins of the UFS protocol are reserved on the encapsulated particles of the UFS memory chip. Communication pins between the NAND Flash controller chip and the NAND Flash memory chip are not left on the package. When the NAND Flash controller chip in the UFS storage chip particles is damaged but the NAND Flash storage chip is normal, the cost of the NAND Flash storage particles is high, the whole chip particles are discarded, resources are wasted, and the resource utilization rate of the UFS storage chip is also reduced.

In some embodiments, the encapsulated chip 100 is a UFS or eMMC memory chip, and the memory controller 110 is a UFS or eMMC controller chip, respectively. The memory 120 may be a NAND Flash memory chip. When a UFS controller chip in a UFS storage chip or an eMMC controller chip in an eMMC storage chip is damaged and a NAND Flash storage chip in the UFS or the eMMC storage chip is normal, the UFS or the eMMC storage chip is directly used as NAND Flash storage particles to develop other storage products with low-level requirements, such as a U disk. The utilization rate of a batch of UFS or eMMC memory chips can be greatly improved, and the cost for developing a U disk and additionally purchasing NAND Flash memory particles can be reduced.

Fig. 2 shows an internal structural schematic diagram of a sealed chip according to an embodiment of the present disclosure. As shown in fig. 2, the sealed chip 200 includes: the memory controller 210, the 1 st to nth memories 220, the seal pin 230 and the multiplexer 260 n are positive integers and are greater than 1.

In some embodiments, as shown in fig. 2, the memory controller 210 and the 1 st to nth memories 220 are connected via a data connection 241, and the memory controller 210 receives a read/write operation request from an external device and performs a read/write operation on the 1 st to nth memories 220 according to the read/write operation request. The memory controller 210 includes first pins 211, and each memory 220 includes third pins 221, the third pins 221 being used to read data from the memory 220 and/or write data to the memory 220. The closeout pin 230 is connected to an external device.

In some embodiments, multiplexer 260 includes an input 261, an output 262, and a control 263. The input terminal 261 is connected to the first pin 211 of the memory controller 210 and the third pin 221 of each of the 1 st to nth memories 220, and the output terminal 262 is connected to the seal pin 230. The control terminal 263 is used for receiving a control signal, and the output terminal 262 is connected to the first pin 211 of the memory controller 210 or the third pin 221 of the memory 220 via the input terminal 261 according to the control signal. When the output 262 is connected to the first pin 211, the function of the sealed chip 200 is realized, and when the output 262 is connected to the third pin 221, the function of the corresponding memory 220 is realized.

In some embodiments, when the control signal is at the first level, the multiplexer 260 connects the output end 262 to the first pin 211 of the memory controller 210 through the input end 261, so that the first pin 211 of the memory controller 210 is connected to the sealing pin 230, and the sealing chip 200 is used as a dedicated sealing chip to implement the function of the sealing chip 200. When the control signal is at the second level, the multiplexer 260 connects the output 262 to the third pin 221 of the 1 st memory 220 through the input 261, so that the third pin 221 of the 1 st memory 220 is connected to the seal pin 230, and the seal chip 200 is used as the 1 st memory 220 to implement the function of the 1 st memory 220. When the control signal is at the third level, the multiplexer 260 connects the output 262 to the third pin 221 of the 2 nd memory 220 through the input 261, so that the third pin 221 of the 2 nd memory 220 is connected to the seal pin 230, and the seal chip 200 is used as the 2 nd memory 220 to implement the function of the 2 nd memory 220. In analogy, when the control signal is at the n +1 th level, the multiplexer 260 connects the output 262 to the third pin 221 of the nth memory 220 through the input 261, so that the third pin 221 of the nth memory 220 is connected to the seal pin 230, and the seal chip 200 is used as the nth memory 220 to realize the function of the nth memory 220.

The sealing chip 200 of the embodiment of the disclosure may be applied to various application scenarios, and the functions of the sealing chip 200 and the functions of each of the 1 st to nth memories 220 are implemented. It should be noted that the first pins 211, the third pins 221, and the encapsulating pins 230 in the drawings are only exemplary, and the number of the first pins 211, the third pins 221, and the encapsulating pins 230 and the positions of the respective chips may be set differently according to actual engineering requirements.

Fig. 3 shows an internal structure diagram of a sealed chip according to an embodiment of the present disclosure. As shown in fig. 3, the sealed chip 300 includes: the memory controller 310, the 1 st memory 320 to the nth memory 320 and the seal pin 330, n is a positive integer and is greater than 1.

In some embodiments, as shown in fig. 3, the memory controller 310 and the 1 st to nth memories 320 to 320 are connected via a data connection 341, and the memory controller 310 receives a read/write operation request from an external device and performs a read/write operation on the 1 st to nth memories 320 to 320 according to the read/write operation request. The memory controller 310 includes first pins 311, and each memory 320 includes third pins 321, the third pins 321 being used to read data from the memory 320 and/or write data to the memory 320. The closeout pin 330 is connected to an external device.

In some embodiments, the sealing pins 330 include a first sealing pin 331 and at least one third sealing pin 332 (third sealing pin 332-1 through third sealing pin 332-n are shown). The first pin 311 of the memory controller 310 is connected to a first seal pin 331, and the third pin 321 of each of the 1 st to nth memories 320 is connected to a third seal pin 332-1 to a third seal pin 332-n, respectively. In some embodiments, when the first encapsulating pin 331 is connected to an external device and the third encapsulating pin 332 is suspended, the function of the encapsulating chip 300 is realized.

In some embodiments, when the third seal pin 332 connected to the third pin 321 of one of the 1 st to

nth memories

320 and 320 is connected to an external device and the other seal pins are suspended, the corresponding function of the memory 320 is implemented. For example, when the third seal pin 332-i connected to the third pin 321 of the ith memory 320 is connected to an external device and other seal pins are suspended, the function of the ith memory 320 is implemented, where i is an integer, and i is greater than or equal to 1 and less than or equal to n.

The sealed chip 300 of the embodiment of the present disclosure may be applied to various application scenarios, and the functions of the sealed chip 300 and the functions of each of the 1 st to nth memories 320 to 320 are implemented. It should be noted that the first pin 311, the third pin 321, the first seal pin 331, and the third seal pin 332 in the drawings are only exemplary, and the number of the first pin 311, the third pin 321, the first seal pin 331, and the third seal pin 332 and the positions of the respective chips may be set differently according to actual engineering requirements.

Fig. 4 shows an internal structural diagram of a sealed chip according to an embodiment of the present disclosure. As shown in fig. 4, the sealed chip 400 includes: the memory controller 410, the 1 st to nth memories 420, the seal pin 430 and the multiplexer 460, n is a positive integer and is greater than 1.

In some embodiments, as shown in fig. 4, the memory controller 410 is connected to the 1 st memory 420 to the nth memory 420 through the data connection line 441, and the memory controller 410 receives a read/write operation request from an external device and performs a read/write operation on the 1 st memory 420 to the nth memory 420 according to the read/write operation request. The memory controller 410 includes a first pin 411, and the 1 st to nth memories 420 share a second pin 422. In one example, a second pin 422 is disposed on the data connection line 441 between the 1 st to nth memories 420 and the memory controller 410, and the second pin 422 is used to read data from the 1 st to nth memories 420 and/or write data to the 1 st to nth memories 420 with the 1 st to nth memories 420 as a whole. The closeout pin 430 is connected to an external device.

In some embodiments, multiplexer 460 includes an input 461, an output 462, and a control 463. The input terminal 461 is connected to the first pin 411 of the memory controller 410 and the second pin 422 shared by the 1 st memory 420 through the nth memory 420, and the output terminal 462 is connected to the seal pin 430. The control terminal 463 is configured to receive a control signal, and connect the output terminal 462 to the first pin 411 or the second pin 422 via the input terminal 461 according to the control signal. When the output 462 is connected to the first pin 411 through the input 461, the function of the combined chip 400 is realized, and when the output 462 is connected to the second pin 422 through the input 461, the functions of the 1 st memory 420 through the nth memory 420 as a whole are realized. In some embodiments, when the control signal is at the first level, the multiplexer 460 connects the output terminal 462 to the first pin 411 through the input terminal 461, so that the first pin 411 is connected to the sealing pin 430, thereby implementing the function of the sealing chip 400. When the control signal is at the second level, the multiplexer 460 connects the output 262 to the second pin 422 through the input 461, so that the second pin 422 is connected to the seal pin 430, thereby implementing the overall functions of the 1 st memory 420 to the nth memory 420. The sealing chip 400 of the embodiment of the disclosure may be applied to various application scenarios, and the functions of the sealing chip 400 and the overall functions of the 1 st memory 420 to the nth memory 420 are realized. It should be noted that the first pins 411, the second pins 422, and the encapsulating pins 430 in the drawings are only exemplary, and the number of the first pins 411, the second pins 422, and the encapsulating pins 430 and the positions of the respective chips may be set differently according to actual engineering requirements.

In some embodiments, the encapsulated chip 400 is a UFS or eMMC memory chip, and accordingly, the memory controller 410 is a UFS or eMMC controller chip. The memory 420 may be a NAND Flash memory chip. When the encapsulating pin 430 is connected to the first pin 411 through the multiplexer 460, the memory chip function of the UFS or eMMC interface may be implemented. When the seal pin 430 is connected to the second pin 422 through the multiplexer 460, a NAND Flash memory chip function can be implemented.

Fig. 5 shows an internal structural schematic diagram of a sealed chip according to an embodiment of the present disclosure. As shown in fig. 5, the sealing chip 500 includes: the memory controller 510, the 1 st memory 520 to the nth memory 520 and the seal pin 530, n are positive integers and are greater than 1.

In some embodiments, as shown in fig. 5, the memory controller 510 and the 1 st to nth memories 520 to 520 are connected via a data connection 541, and the memory controller 510 receives a read/write operation request from an external device and performs a read/write operation on the 1 st to nth memories 520 according to the read/write operation request. The memory controller 510 includes a first pin 511, and the 1 st to nth memories 520 share a second pin 522. In one example, a second pin 522 is disposed on the data connection line 541 between the 1 st to nth memories 520 to 520 and the memory controller 510, and the second pin 522 is used to read data from the 1 st to nth memories 520 and/or write data to the 1 st to nth memories 520 from the 1 st to nth memories 520 as a whole. The seal pin 530 is connected to an external device.

In some embodiments, the seal pin 530 includes a first seal pin 531 and a second seal pin 533. The first pin 511 is connected to a first close-seal pin 531, and the second pin 522 is connected to a second close-seal pin 533. In some embodiments, when the first encapsulating pin 531 is connected to an external device and the second encapsulating pin 533 is suspended, the function of the encapsulating chip 500 is realized. In some embodiments, when the second seal pin 533 is connected to an external device and other seal pins are suspended, the 1 st memory 520 to the nth memory 520 as a whole are realized. The sealing chip 500 of the embodiment of the present disclosure may be applied to various application scenarios, and the functions of the sealing chip 500 and the 1 st memory 520 to the nth memory 520 as a whole are implemented. It should be noted that the first pin 511, the second pin 522, the first close-sealing pin 531, and the second close-sealing pin 533 in the figure are only exemplary, and the number of the first pin 511, the second pin 522, the first close-sealing pin 531, and the second close-sealing pin 533 and the position of each chip may be set differently according to actual engineering requirements.

In some embodiments, the encapsulated chip 500 is a UFS or eMMC memory chip, and accordingly, the memory controller 510 is a UFS or eMMC controller chip. The memory 520 may be a NAND Flash memory chip. Only the UFS/eMMC protocol related pin 531 and no other pin are left on the originally packaged UFS or eMMC memory chip particles, and when a UFS or eMMC controller chip is damaged, the whole chip is discarded, which results in higher cost for developing and producing a batch of UFS or eMMC controller chips. The NAND Flash memory chip has high cost, and the second seal pin 533 is additionally designed, in this embodiment, the second seal pin 533 is a NAND interface control pin, an external device is connected to the newly added NAND interface control pin 533, and the UFS/eMMC protocol related pin 531 is suspended, so that the UFS or eMMC memory chip is implemented as a NAND Flash memory chip, the overall development and production cost of a batch of seal chips can be reduced, and the utilization rate of the UFS or eMMC memory chip is improved. Meanwhile, when the UFS or eMMC controller chip is normal, the external device is connected to the UFS/eMMC protocol related pin 531, and the newly added NAND interface control pin 533 is suspended, so that the original function of the UFS or eMMC memory chip is not affected.

Fig. 6 shows a flow diagram of a method of using a sealed chip according to one embodiment of the present disclosure. The use method of the sealing chip of the embodiment of the present disclosure is applied to the sealing chip in the above embodiments. As shown in fig. 6, a method for using a sealed chip according to an embodiment of the present disclosure includes:

in step S610, the first pin is connected to the sealing pin to implement the function of the sealing chip.

In step S620, the second pin is connected to the seal pin to implement a function of the at least one memory.

In some embodiments, the sealing chip further includes a multiplexer, the multiplexer includes an input terminal, an output terminal, and a control terminal, the input terminal is connected to the first pin and the second pin, the output terminal is connected to the sealing pin, the control terminal is configured to receive a control signal, and the output terminal is connected to the first pin or the second pin through the input terminal according to the control signal, and the using method includes:

connecting the output to the second pin to implement the function of the at least one memory.

In some embodiments, each of the at least one memory devices includes a third pin, the third pin is used for reading data from the memory device and/or writing data into the memory device, the seal chip further includes a multiplexer, the multiplexer includes an input terminal, an output terminal, and a control terminal, the input terminal is connected to the first pin and the third pin of each of the at least one memory devices, the output terminal is connected to the seal pin, the control terminal is used for receiving a control signal, and the output terminal is connected to the first pin or the third pin according to the control signal, the using method includes:

and connecting the output end with the third pin to realize the corresponding function of the memory.

In some embodiments, the sealing pins include a first sealing pin and a second sealing pin, the first pin is connected to the first sealing pin, and the second pin is connected to the second sealing pin, and the using method includes:

In some embodiments, each of the at least one memory devices includes a third pin, the third pin is used for reading data from the memory device and/or writing data into the memory device, the seal pin includes a first seal pin and at least one third seal pin, the first pin is connected to the first seal pin, the third pin of each of the at least one memory devices is respectively connected to the third seal pin, and the using method includes:

The implementation details of the above-mentioned using method have been described in the above detailed description of the embodiment of the sealing chip, and are not repeated for brevity.

Fig. 7 shows a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. As shown in fig. 7, the electronic device 700 includes a host 710 and a sealing chip 720, and the host 710 and the sealing chip 720 are connected. As described above for the sealed chip embodiments, the sealed chip 720 may include a memory controller and at least one memory. In some embodiments, the functions of the sealed chip 720 are used in the electronic device 700, and the host 710 is configured to receive a read/write command from the outside, read data from the sealed chip 720, or write data to the sealed chip 720. In some embodiments, when part of the functions of the sealed chip 720 are damaged (for example, the memory controller in the sealed chip 720 is damaged) or the original application scenario is no longer needed because of the supply and demand relationship, the sealed chip 720 may be used as at least one memory therein, and the functions of the at least one memory in the sealed chip 720 are used in the electronic device 700. The host 710 is used to receive read/write commands from the outside, read data from at least one memory in the sealed chip 720 or write data to at least one memory in the sealed chip 720.

FIG. 8 shows a schematic structural diagram of a computer device according to one embodiment of the present disclosure. The device shown in fig. 8 is only an example and should not constitute any limitation on the function and scope of use of the embodiments of the present disclosure.

Referring to fig. 8, the computer device includes a processor 810, a memory 820, and an input-output device 830 connected by a bus. The memory 820 includes a Read Only Memory (ROM) and a Random Access Memory (RAM), and various computer instructions and data required to perform system functions are stored in the memory 820, and the processor 810 reads the various computer instructions from the memory 820 to perform various appropriate actions and processes. The input and output device 830 includes an input portion of a keyboard, a mouse, and the like; an output section including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage section including a hard disk and the like; and a communication section including a network interface card such as a LAN card, a modem, or the like. The memory 820 also stores computer instructions to perform the operations specified by the methods of the embodiments of the present disclosure.

Accordingly, embodiments of the present disclosure provide a computer-readable medium comprising computer-executable code that, when executed by a processor, implements the method described above.

According to the sealed chip, the using method, the device and the medium provided by the embodiment of the disclosure, the sealed chip comprises a memory controller, at least one memory and sealed pins, the memory controller comprises a first pin used for receiving a read/write operation request of an external device, the memory controller is connected with the at least one memory, the memory controller performs read/write operation on the at least one memory according to the read/write operation request, the at least one memory shares a second pin, the second pin is used for reading data from the at least one memory and/or writing the data into the at least one memory, the sealed pins are connected with the external device, when the first pin is connected with the sealed pins, the function of the sealed chip is realized, and when the second pin is connected with the sealed pins, the at least one memory is realized as an integral function.

The flowcharts and block diagrams in the figures illustrate the possible architectures, functions, and operations of the systems, methods and apparatuses according to the embodiments of the present disclosure, and the blocks in the flowcharts and block diagrams may represent modules, program segments, or code segments only, which are executable instructions for implementing specified logical functions. It should also be noted that the executable instructions that implement the specified logical functions may be recombined to create new modules and program segments. The blocks of the drawings, and the order of the blocks, are thus provided to better illustrate the processes and steps of the embodiments and should not be taken as limiting the invention itself.

The above description is only a few embodiments of the present disclosure and is not intended to limit the present disclosure, which may be subject to various modifications and changes by those skilled in the art. Any modification, equivalent replacement, improvement or the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A package chip, comprising:

2. The encapsulated chip of claim 1, wherein the encapsulated chip further comprises a multiplexer,

3. The closure chip of claim 1, wherein each of the at least one memory includes a third pin for reading data from and/or writing data to the memory, the closure chip further comprising a multiplexer,

4. The encapsulated chip of claim 1, wherein the encapsulated pins comprise a first encapsulated pin and a second encapsulated pin, the first pin being connected to the first encapsulated pin, the second pin being connected to the second encapsulated pin,

5. The sealing chip of claim 1, wherein each of the at least one memory comprises a third pin for reading data from and/or writing data to the memory, the sealing pins comprise a first sealing pin and at least one third sealing pin, the first pin is connected to the first sealing pin, the third pin of each of the at least one memory is connected to the third sealing pin,

6. A method for using a sealed chip, wherein the sealed chip includes a memory controller, at least one memory and a sealed pin, the memory controller includes a first pin, the first pin is used to receive a read/write operation request from an external device, the memory controller is connected to the at least one memory, the memory controller performs a read/write operation on the at least one memory according to the read/write operation request, the at least one memory shares a second pin, the second pin is used to read data from the at least one memory and/or write data into the at least one memory, and the sealed pin is connected to the external device, the method comprising:

7. The use method of claim 6, wherein the encapsulated chip further comprises a multiplexer, the multiplexer comprises an input terminal, an output terminal, and a control terminal, the input terminal is connected to the first pin and the second pin, the output terminal is connected to the encapsulated pin, the control terminal is configured to receive a control signal, and the output terminal is connected to the first pin or the second pin through the input terminal according to the control signal, and the use method comprises:

8. The use method of claim 6, wherein each memory of the at least one memory includes a third pin, the third pin is used for reading data from the memory and/or writing data into the memory, the seal chip further includes a multiplexer, the multiplexer includes an input terminal, an output terminal and a control terminal, the input terminal is connected to the first pin and the third pin of each memory of the at least one memory, the output terminal is connected to the seal pin, the control terminal is used for receiving a control signal, and the output terminal is connected to the first pin or the third pin through the input terminal according to the control signal, the use method includes:

9. The use method of claim 6, wherein the seal pin comprises a first seal pin and a second seal pin, the first pin is connected with the first seal pin, and the second pin is connected with the second seal pin, the use method comprising:

and connecting the second seal pin with the external equipment, and suspending the first seal pin to realize the function of the at least one memory.

10. The use method of claim 6, wherein each memory of the at least one memory comprises a third pin, the third pin is used for reading data from the memory and/or writing data into the memory, the seal pin comprises a first seal pin and at least one third seal pin, the first pin is connected with the first seal pin, the third pin of each memory of the at least one memory is respectively connected with the third seal pin, and the use method comprises:

and connecting the third sealing pin with the external equipment, and suspending other sealing pins to realize the corresponding functions of the memory.

11. An electronic device, comprising:

the flip chip of any of claims 1-5.

12. A computer device, comprising:

a memory for storing computer executable code;

a processor for executing the computer executable code to implement the method of any one of claims 6 to 10.

13. A computer-readable medium comprising computer-executable code that, when executed by a processor, performs the method of any one of claims 6-10.