CN115398607A - Jin Beifu bonding wire, method for manufacturing the same, semiconductor wire bonding structure, and semiconductor device - Google Patents

Jin Beifu bonding wire, method for manufacturing the same, semiconductor wire bonding structure, and semiconductor device Download PDF

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Publication number
CN115398607A
CN115398607A CN202080099629.XA CN202080099629A CN115398607A CN 115398607 A CN115398607 A CN 115398607A CN 202080099629 A CN202080099629 A CN 202080099629A CN 115398607 A CN115398607 A CN 115398607A
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China
Prior art keywords
bonding
wire
beifu
jin
electrode
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CN202080099629.XA
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Chinese (zh)
Inventor
安德优希
川野将太
崎田雄祐
平井祐佳
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Tanaka Denshi Kogyo KK
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Tanaka Denshi Kogyo KK
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Publication of CN115398607A publication Critical patent/CN115398607A/en
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The present invention provides Jin Beifu bonding wires which have characteristics equivalent to gold and do not require a high material cost, and which are applicable to a method (CWB) for direct wedge bonding between electrodes of a multi-stage stacked chip, in place of bonding wires mainly composed of gold, in consideration of the demands for chip thinning and multi-stage stacking of semiconductor devices such as memories. A gold-coated bonding wire (1) of the present invention has a core material (2) containing silver or copper as a main component, and a coating layer (3) provided on the surface of the core material (2) and containing gold as a main component. The thickness of the gold-coated layer is controlled to be 5nm to 200nm, and the compressive stress at a strain of 60% with respect to the wire diameter is controlled to be 290MPa to 590MPa, thereby achieving the technical object.

Description

Jin Beifu bonding wire, method for manufacturing the same, semiconductor wire bonding structure, and semiconductor device
Technical Field
The invention relates to a gold-coated bonding wire and a method for manufacturing the same, a semiconductor wire bonding structure, and a semiconductor device.
Background
An integrated circuit such as an IC or an LSI in which semiconductor elements such as a capacitor and a diode are collectively combined with a semiconductor device occupies a large part of the market scale. An integrated circuit incorporates a "semiconductor chip" formed of a silicon single crystal or the like. A semiconductor chip includes a plurality of elements of an electronic circuit that performs a complicated function, and is a precision electronic component that is very weak against vibration or shock. Further, a plurality of electrodes (referred to as chip electrodes or pads) are provided on the surface of the semiconductor chip, and electrode portions of a circuit base material such as a lead frame or a circuit board, which mainly supports and fixes the semiconductor chip and is connected to external wiring, and the electrodes of the chip electrodes are bonded and wired by bonding wires.
The bonding wire is generally bonded at one end thereof to a chip electrode by a method called ball bonding (1 st bonding), and at the other end thereof to an external electrode of a circuit substrate such as a lead frame by a method called wedge bonding (or stitch bonding) (2 nd bonding). In the ball bonding, one end of a bonding wire is melted by electric discharge or the like, and solidified into a spherical shape by surface tension or the like to form a ball. The solidified Ball is called a Free Air Ball (FAB), and is connected to the chip electrode by thermocompression bonding or the like by ultrasonic waves. In wedge bonding, ultrasonic waves and a load are applied to a wire, bonded to an electrode, using a bonding tool (a welding pin).
As the bonding wire, a metal wire such as a gold wire, a silver wire, or a copper wire having a wire diameter of about 15 to 35 μm is used, and a coated wire obtained by coating these metal wires with another metal is also used. The semiconductor device is configured by resin-sealing a semiconductor chip and a circuit substrate connected by wire bonding.
However, although a memory device (memory) is incorporated in a computer, a smart phone, a digital camera, a portable music player, and the like, the memory is classified into a mechanically readable memory represented by a hard disk, a semiconductor memory such as a flash memory, and the like. A semiconductor memory is a type of semiconductor device, and electronic components called cells for storing data are incorporated in a semiconductor chip. Semiconductor memories have high cost per unit capacity and have been used for external storage in a few years, but in recent years, demand for semiconductor memories has increased due to low cost and the weakness of mechanical hard disks that are destroyed by vibration.
In addition, since there is a strong demand for storage of large-capacity data of music or moving images and for miniaturization and thinning of portable devices such as portable music players, demands for a semiconductor memory having a large capacity and a small size have been increased. For example, NAND flash memories are used for image storage of digital cameras, and USB memories (Universal Serial Bus) are used for smart phones, portable music players, and the like. In the year around 2000 of the Gregorian calendar, the memory capacity is 1 Gbyte or less, but in the year around 2010, a demand for a larger capacity is continuously increasing in recent years in response to a demand for 100 Gbytes or more.
On the other hand, as portable devices are miniaturized, there is an increasing demand for miniaturization of semiconductor memories, and semiconductor memory chips are also required to be thin. In the year of about 2000 in the gregorian calendar, a chip having a thickness of about 150 μm was sufficient, but the thinning of the chip has been rapidly progressed thereafter, and a chip having a thickness of about 30 μm was used in the year of about 2010. In recent years, development of chips having a thickness of only 20 μm (0.020 mm) has been advanced. Needless to say, the thinning of the chip makes it easier to break and more careful handling of electronic components that would otherwise be broken by a very precise and careless handling.
In order to meet the demands for higher capacity and smaller size, semiconductor memory manufacturers have made efforts to reduce the thickness and multi-level stack packages of memory chips. The memory capacity of 1 memory chip is limited, and is about 4 to 8 gigabytes per 1 memory chip, and thus at least 16 chips are required for the memory capacity of 128 gigabytes, for example. Since a memory product itself is enlarged when a plurality of semiconductor devices are assembled, stacking thin chips in 1 semiconductor device is a means to meet both requirements of a large capacity and a small size. In the deposition method, there is a method of depositing chips in a unidirectional step shape as shown in fig. 11 or fig. 12 described later; and stacking the layers with the V-shape being laid in the horizontal direction as shown in fig. 13.
In the field of the semiconductor memory, it is necessary to bond and wire the electrodes on the surface of the stacked, delicate and fragile chip to the electrodes on the lead frame or the circuit board by bonding wires. Here, a bonding method performed before this is explained. For example, in a semiconductor device in which a circuit board and 3 chips thereon as shown in fig. 9 are stacked in 4 stages, first, a bump electrode called a bump is formed on an electrode of each chip, and then, a bonding wire is ball-bonded to the electrode of the circuit board, and thereafter, the bonding wire is wedge-bonded to a surface of the bump formed on the electrode of the chip which does not perform a loop back operation. This bonding method is called BSOB (BALL stuck ON BALL) mode or reverse bonding. The purpose is to obtain the effect of a buffer material and the like for preventing chip destruction by forming bumps on precise and fragile chip electrodes. This BSOB was repeated 3 times to connect the chip electrode and the circuit board. In a general procedure, the chip electrode is directly ball-bonded without forming a bump on the chip electrode, and after performing a loop-back operation, the bonding wire is wedge-bonded to the electrode of the circuit board. This joining method is called a positive joining method. Generally, the chip electrodes are connected to the circuit board by a positive bonding method, but with the recent thinning of semiconductor packages, it is necessary to control the loop height to be low, and therefore a reverse bonding method is adopted as a bonding method on the stacked chips. Since the wire is always upward in the wire characteristics and is difficult to bend at a sharp angle in the vicinity of the neck portion between the ball portion and the wire portion after the FAB is formed, in the ball bonding in the positive bonding method, a space is required to reach a higher position, and thinning of the semiconductor memory is significantly insufficient. Therefore, it is a big reason to bond the electrode of the upper chip from the electrode of the circuit board at the low position. Further, as conditions suitable for the bonding wire of the reverse bonding method, there can be mentioned those having flexibility not to deteriorate the precision of the chip electrode; the wedge bonding to the bump, the bump surface and the wire surface has high corrosion resistance and oxidation resistance. Therefore, a gold (Au) bonding wire and a gold (Au) bump, which are soft and do not oxidize, are used as the main component.
However, in the above joining method, the distance between the chip electrode and the circuit board is increased and the chip electrode and the circuit board are connected by 1 wire, so that man-hours for moving the chip electrode and the circuit board to and from each other are required, and productivity is lowered. Further, since the loop length is long, there is a problem that straightness of the looped wire is controlled. Therefore, a method (cascade bonding method) of connecting the chip electrodes to the electrodes of the circuit board after connecting the chip electrodes shown in fig. 10 with wires is adopted. The cascade connection method will be explained. In a semiconductor device in which 4 chips are stacked on a circuit board, the connection is made from the upper chip (the circuit board at the lowest stage is the 1 st stage, and the chip at the highest stage is the 4 th stage). First, a bump is formed on the chip electrode at the 3 rd stage, the chip electrode at the 4 th stage is ball-bonded, and after a loop-back operation, a bonding wire is wedge-bonded to the bump formed on the chip electrode at the 3 rd stage. Thereby, the chip electrodes of the 3 rd and 4 th stages are connected. Next, bumps are formed on the chip electrodes of the 2 nd stage, and the bumps subjected to wedge bonding located on the chip electrodes of the 3 rd stage are ball-bonded. After the loop-back operation, wedge bonding is performed on the bumps formed on the chip electrodes of the 2 nd segment. Thereby, the chip electrodes of the 2 nd, 3 rd and 4 th stages are connected. Finally, ball bonding is performed on the bump accompanying the wedge bond formed on the chip electrode of the 2 nd stage, and the bonding wire is wedge bonded to the circuit board of the 1 st stage through a loop-back operation. As a result, the chip electrodes at the uppermost stage are wired in series to the electrodes of the circuit board at the lowermost stage. In this case, since the bonding wire requires flexibility and oxidation resistance as well as the reverse bonding method, a gold (Au) bonding wire and a gold (Au) bump are used.
Among these methods, although the demand for a large capacity and a small size of a semiconductor device is satisfied, in these methods, since it is necessary to cycle the 4 steps of (1) bump formation, (2) ball bonding, (3) wedge bonding, and (4) wire peeling by the number of chips, the number of steps becomes too large for the 16-stage and 32-stage multistage of chips accompanied by further large capacity in recent years, and the 64 steps and 128 steps, the number of steps becomes too large, and there are problems that productivity is lowered and manufacturing cost is extremely high. Therefore, as an improved Bonding method centered on the Bonding apparatus manufacturer, a multi-stage continuous Bonding method called a Capillary Wedge Bonding (CWB) has been proposed. CWB is a method of bonding a wire to a chip electrode at the uppermost stage by wedge bonding, then performing loop-back wedge bonding to a chip electrode at the next stage, continuously connecting 1 same wire to a chip electrode at the next stage without tearing, and finally connecting the wire to an electrode of a circuit board, instead of conventional ball bonding. In this method, since the formation of the bump, the wire removal after wedge bonding, and the ball bonding after FAB formation can be omitted, the number of steps can be significantly reduced. Specifically, since only 1 step of wedge bonding is performed for 1 chip, the conventional man-hours become 1/4, and bonding can be performed continuously without forming bumps or FAB, and thus the bonding time can be significantly shortened. Further, since no bump or FAB is formed, the amount of the bonding wire used can be significantly reduced. This can significantly improve productivity and reduce manufacturing cost (fig. 6 described later is an example of a conventional ball joint, and fig. 11 and 12 are examples of a CWB).
As described above, by using the CWB method in the bonding apparatus, the productivity of continuous bonding of the multi-stage laminated chip can be significantly improved. This is an improvement of the hard surface, provided that the bonding wire as a soft surface still uses a gold wire which does not cause damage to the chip electrode. As described above, although the bumps or the FAB may not be formed, when the multi-stage laminated chip becomes necessary, the amount of the bonding wire used is greatly increased, and thus, although the productivity is improved, the use of expensive gold causes a new technical problem of increasing the material cost and increasing the total cost.
The present inventors have made a problem to develop a bonding wire that has characteristics equivalent to those of gold and is applicable to a CWB method without a material cost, instead of a bonding wire mainly composed of gold. When the conditions for the wire necessary for the continuous bonding of the multi-stage laminated chip electrodes by the CWB method are newly summarized, there are (1) good wedge bondability (having continuous bondability and bonding strength), (2) no damage to the chip electrodes, (3) a thin wire having a wire diameter of 35 μm or less, (4) inexpensive material cost, (5) not limited to CWB and low specific resistance, and the like.
For example, jp 2007-012776 a (patent document 1) describes a bonding wire having a core material mainly composed of copper and a sheath layer on the core material, the sheath layer containing copper and a conductive metal different from one or both of the components or the composition of the core material, and the sheath layer having a thickness of 0.001 to 0.02 μm (1 to 20 nm), as a bonding wire capable of improving the ball formability and the bonding property and improving the bonding strength of wedge bonding. Jp 2007-123597 a (patent document 2) describes a bonding wire having a core material containing 1 or more of silver, gold, palladium, platinum, and aluminum as a main component element, and an outer sheath layer containing a conductive metal different from the main component element as a main component, the outer sheath layer having a thickness of 0.001 to 0.09 μm (1 to 90 nm), as a bonding wire capable of improving ball formability and bondability and improving bonding strength of wedge bonding. These bonding wires are improved in wedge bondability by controlling the thickness of the outer skin layer, the thickness and concentration distribution of the concentration gradient region of the core material and the outer skin layer, and the like, and are not controlled in consideration of the characteristics of the bonding wire itself having the outer skin layer. The opponent of the wedge bonding is an electrode of a lead frame or a circuit board or a bump on a chip electrode, and is basically different from the case of direct wedge bonding to a thin, delicate chip electrode.
International publication No. 2013/129253 (patent document 3) discloses a power semiconductor device in which a metal wire is used to wedge-connect a metal electrode (element electrode) of a power semiconductor element and a metal electrode (connection electrode) of a substrate or the like, wherein the metal wire is an Ag or Ag alloy wire having a diameter of more than 50 μm and 2mm or less, or a wire having a coating layer containing 1 or more of Pd, au, zn, pt, ni, and Sn or an alloy thereof or an oxide or nitride of these metals on the surface of the Ag or Ag alloy wire by a thickness of 3nm or more. In this power semiconductor device, the metal wires are wedge-bonded to both the element electrodes and the connection electrodes, but the metal wires are thick wires having a diameter of more than 50 μm and 2mm or less, and thin wires having a wire diameter of about 15 to 35 μm are not considered. In this power semiconductor device, the wedge bondability is merely improved by selecting the constituent metal, thickness, and the like of the electrode coating layer that covers the element electrode surface. In addition, the electrodes of power semiconductors that handle large amounts of power are fundamentally different from the electrodes of precision, fragile thin chips such as memories.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open No. 2007-012776
Patent document 2: japanese patent laid-open No. 2007-123597
Patent document 3: international publication No. 2013/129253
Disclosure of Invention
Technical problems to be solved by the invention
As described above, the present inventors have made an object to develop a bonding wire that can be applied to a method (CWB) of directly wedge bonding electrodes of a multi-stage stacked chip, which has characteristics equivalent to gold and does not require a material cost, instead of a bonding wire mainly composed of gold, in consideration of the needs for thinning and stacking a chip of a semiconductor device such as a memory. Repeatedly, as conditional problems necessary for the wire, there are (1) good wedge bondability (having continuous bondability and bonding strength), (2) no damage to the chip electrode, (3) a thin wire having a wire diameter of 35 μm or less, (4) inexpensive material cost, (5) not limited to CWB, low specific resistance, and the like.
In addition, when chips are stacked in multiple stages in order to thin a semiconductor device, the orientation of the V-shaped line is changed as shown in fig. 13, and the lower side of the chip electrode portion is left blank and there is no base (support) of the chip. It was determined that when no base was present, ultrasonic application by a bonding pin became ineffective, bonding energy applied to the chip decreased, and bonding strength became weak. Is multi-stage, and therefore, it is necessary to individually set the engagement energy suitable for each position. The bonding energy is a range of conditions for obtaining stable bonding, and the wedge bonding conditions mainly include load, ultrasonic wave application, and heating temperature. When the conditions around the bonding position are different from each other, a wide range of conditions for bonding energy is required.
The present inventors have repeatedly tried and tried with a conventional bonding wire not mainly composed of gold, and have determined that since the range of bonding energy that can be handled by the conventional bonding wire is narrow, in the continuous wedge bonding, when the bonding energy is low, that is, when the amount of broken wire is mainly small, the bonding strength is weak, and the wire is peeled (raised) at the bonding interface in the course of the subsequent loop back, and conversely, when the bonding energy is high (the amount of broken wire is large, and the load is high), the chip is damaged, and the wire is deformed to be extremely thin, and therefore, the wire is cut at a position where the bonding portion is thin in the course of the subsequent loop back.
The invention provides a bonding wire which can bond chip electrodes stacked in multiple thin sections of a semiconductor memory or the like in a good wedge shape, does not damage the chip electrodes, has a wide bonding energy condition range, has low specific resistance, and does not cost materials. Further, the present invention solves the technical problems by providing a method for manufacturing the same, and a semiconductor wire bonding structure and a semiconductor device using the bonding wire.
The present inventors have conducted extensive studies on a bonding wire in order to solve the above-mentioned problems of wedge bonding, and as a result of a conclusion made based on trial and error, found that it is effective to control the compressive stress of the wire. The compressive stress is a value of strength (force) per unit area when the yarn is deformed by a force in a compressive direction, and it has been found in the present invention that the technical problem can be solved when the compressive stress at 60% compression (deformation) with respect to the yarn diameter of the yarn is in the range of 290MPa to 590MPa.
The details of the compressive stress measuring method of the present invention are described in detail on page 14, line 15 to page 15, line 16, and are calculated by the following equations.
Compressive stress (MPa) = force applied when deforming 60% with respect to the diameter of the wire (N)/(circumference ratio. Times. Wire diameter (mm)/2). Times. Indenter diameter (mm)
Further, the compressive stress may also use a value automatically calculated in a compression tester. The indenter diameter refers to the diameter of the indenter of the compression tester. The circumference ratio used was 3.14.
As a basic method of the present invention, attention is paid to a so-called wire structure in which the surface of a wire is covered with soft Au, based on an Ag wire or a Cu wire, under the conditions of low specific resistance and low cost while being controlled within the above-described range of compressive stress.
The gold-coated bonding wire of the present invention is a bonding wire having a core material containing silver or copper as a main component and Jin Beifu provided on the surface of the core material and containing a coating layer containing gold as a main component, and is characterized in that the compressive stress when the bonding wire is deformed by 60% with respect to the wire diameter of Jin Beifu is 290MPa to 590MPa.
The method for producing a gold-coated bonding wire of the present invention is a method for producing a Jin Beifu bonding wire having a core material containing silver or copper as a main component and a coating layer containing gold as a main component provided on a surface of the core material, wherein a compressive stress when the bonding wire is deformed by 60% with respect to a wire diameter of the Jin Beifu bonding wire is 290 to 590MPa.
The semiconductor wire bonding structure of the present invention is a Jin Beifu bonding wire having a core material containing silver or copper as a main component and a coating layer containing gold as a main component; an electrode of the semiconductor chip; and a wedge-shaped bonding portion for bonding the wire to the electrode, wherein the coating layer of the Jin Beifu bonding wire has a film thickness of 5nm to 200nm, and a compressive stress at a strain of 60% with respect to the wire diameter is 290MPa to 590MPa.
The semiconductor device of the present invention includes: 1 or more semiconductor chips having at least 1 first electrode; a circuit base material selected from a lead frame and a circuit substrate having at least 1 second electrode; and Jin Beifu bonding wires which are wedge-bonded to at least one of the first electrodes and the second electrodes or the plurality of first electrodes while electrically connecting at least 1 selected from the group consisting of the first electrodes of the semiconductor chips and the second electrodes of the circuit base material and the first electrodes of the plurality of semiconductor chips, wherein the Jin Beifu bonding wire has a core material containing silver or copper as a main component and a coating layer provided on a surface of the core material and containing gold as a main component, and a compressive stress of the Jin Beifu bonding wire is 290 to 590MPa.
Effects of the invention
According to the gold-coated bonding wire and the method for manufacturing the same of the present invention, by setting the compressive stress to 290MP to 590MPa, even in continuous wedge bonding in which bonding energy conditions are different depending on each connection position as in the case of a multi-stage laminated chip electrode, the semiconductor chip electrode and the like are not damaged, and stable wedge bonding strength can be obtained. Further, according to the semiconductor device of the present invention, by using such a gold-coated bonding wire, it is possible to provide a semiconductor memory or the like which is inexpensive, thin, and has a large memory capacity, and which has a suppressed total cost.
In addition to the above-described effects, the present invention is also effective in bonding stability, bonding reliability, and the like in general ball bonding to semiconductor chip electrodes, wedge bonding to substrate circuits, lead frames, and the like.
Drawings
Fig. 1 is a longitudinal sectional view showing a Jin Beifu bonding wire of the embodiment.
FIG. 2 is a cross-sectional view of an embodiment Jin Beifu bonding wire.
Fig. 3 is a longitudinal sectional view showing a modification of the Jin Beifu bonding wire of the embodiment.
Fig. 4 is a cross-sectional view showing a modification of the Jin Beifu bonding wire of the embodiment.
Fig. 5 is a diagram showing the shape of an indentation in a compressive stress test of the bonding wire according to the embodiment.
Fig. 6 is a sectional view showing a stage before resin sealing of the semiconductor device of the embodiment.
Fig. 7 is a sectional view showing a stage after the semiconductor device of the embodiment is resin-sealed.
Fig. 8 is a cross-sectional view showing a wedge-shaped bonding portion of Jin Beifu bonding wires bonded to electrodes of a semiconductor chip in a semiconductor device according to an embodiment.
Fig. 9 is a diagram showing an example of a conventional wire connection structure of a semiconductor chip stacked in a plurality of stages.
Fig. 10 is a diagram showing another example of a conventional wire connection structure of a semiconductor chip stacked in a plurality of stages.
Fig. 11 is a sectional view showing a 1 st modification of the semiconductor device of the embodiment.
Fig. 12 is a sectional view showing a 2 nd modification of the semiconductor device of the embodiment.
Fig. 13 is a cross-sectional view showing an example of a semiconductor device having a multi-stage stacked structure of semiconductor chips.
Detailed Description
Hereinafter, a Jin Beifu bonding wire, a method for manufacturing the same, a semiconductor wire bonding structure, and a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. In each embodiment, substantially the same constituent parts are denoted by the same reference numerals, and a description thereof may be omitted. The drawings are schematic, and the relationship between the thickness and the plane size, the ratio of the thicknesses of the respective portions, the ratio of the vertical size to the horizontal size, and the like may be different from the actual ones. In addition, the use of compressive stress (MPa) in the present specification is based on1kgf/mm 2 Value of conversion equation of =9.8 MPa.
(Jin Beifu Joint wire and method for producing the same)
As shown in fig. 1 and 2, the Jin Beifu bonding wire 1 of the embodiment has a core material 2 mainly composed of silver (Ag) or copper (Cu), and a coating layer 3 provided on the surface of the core material 2 and mainly composed of gold (Au). As shown in fig. 3 and 4, the Jin Beifu bonding wire 1 of the embodiment may further include an intermediate metal layer 4 provided between the core material 2 and the coating layer 3. The intermediate metal layer 4 contains 1 metal selected from palladium (Pd), platinum (Pt) and nickel (Ni) as a main component.
The Jin Beifu bonding wire 1 of the embodiment has a compressive stress of 290 to 590MPa when deformed by 60% with respect to the wire diameter. Jin Beifu compressive stress in bonding wire 1 affects the amount of deformation of the wire and the bondability to the electrode when the wire is wedge-bonded to an electrode of a semiconductor chip or an electrode of a circuit base material such as a circuit board or a lead frame. In this respect, stable wedge bondability or wedge bonding strength can be obtained without damaging a semiconductor chip or the like at the time of wedge bonding by bonding the wire 1 using Jin Beifu having a compressive stress of 290 to 590MPa. In particular, when the electrodes of the semiconductor chips stacked in a plurality of stages are continuously connected by the CWB using 1 bonding wire under different conditions depending on the bonding position, sufficient wedge bonding strength can be obtained without causing chip damage.
The critical meaning of defining the compressive stress range is explained. When the compressive stress of Jin Beifu bonding wire 1 is less than 290MPa, the wire breakage width at the wire bonding portion with respect to the electrode becomes excessively large because it is excessively deformed by the energy at the time of wedge bonding, specifically, the applied ultrasonic wave and the load. When a part of the broken wire is oozed out of the electrode, it comes into contact with the adjacent wire bonding portion, and a short-circuit failure is likely to occur. Further, the wire bonding portion is excessively broken, the bonded wire becomes thin, and when a loop is formed by a bonding tool (bonding pin), breakage of the wire at the bonding portion and the like are likely to occur. In particular, when the electrodes of the semiconductor chip are continuously connected by 1 bonding wire in the CWB, the wire breakage width or the wire thickness at the wire bonding portion tends to be unstable. In order to avoid such a problem, if wedge bonding is performed at a low bonding energy, the wire at the bonding portion is insufficiently deformed to weaken the wedge bonding strength, and the wire is likely to be peeled at the bonding interface in the subsequent ring formation. As a means for evaluating such bonding strength, there is a tensile test, in which wire peeling is referred to as "lift-off", and this is a barometer (meter) for evaluating the possibility of peeling at the bonding interface between the wire and the electrode. 5363 the compressive stress of the Jin Beifu bonding wire 1 is preferably 340MPa or more.
On the other hand, when the compressive stress of Jin Beifu bonding wire 1 exceeds 590MPa, the wire is less likely to deform, the bonding area of the wire bonding portion decreases, the bonding strength becomes weak, and wire separation is likely to occur at the bonding interface in the subsequent loop formation, even if wedge bonding is performed with high bonding energy. This also rises in the tensile test described. Therefore, the compressive stress of Jin Beifu is preferably 540MPa or less, and more preferably 490MPa or less. That is, stable wedge bonding can be performed under a wide range of wedge bonding conditions by using the Jin Beifu bonding wire 1 having a compressive stress of 290MPa to 590MPa.
As described in detail later, the compressive stress of the gold-coated bonding wire 1 can be obtained at 290 to 590MPa by appropriately controlling the composition of the metal material (silver-based material or copper-based material) constituting the core member 2, the composition or heat treatment of the core member 2, the thickness of the coating layer 3 or the intermediate metal layer 4, the wire diameter of the bonding wire 1, the heat treatment conditions applied to the bonding wire 1, and the like. However, the compressive stress of Jin Beifu the bonding wire 1 is not limited by the material, production process, production conditions, and the like of the Jin Beifu bonding wire 1, and the characteristics thereof are exhibited within the above-described range.
The Jin Beifu bonding wire 1 preferably has a wire diameter (diameter D shown in fig. 1) of 13 to 35 μm. If the wire diameter of the wire 1 is less than 13 μm, there is a concern that the strength, conductivity, and the like will be reduced, and the reliability of wire bonding will be reduced, when wire bonding is performed using the bonding wire 1 during the manufacture of semiconductor devices. When the wire diameter of the wire 1 exceeds 35 μm, the bondability to the electrode bonding, particularly the bondability to wedge bonding, may be reduced. For example, the opening area of an electrode of a narrowly spaced semiconductor device is reduced. When the bonding wire 1 having a wedge bonding wire diameter exceeding 35 μm is used in the opening area of the narrowly spaced electrode, the passivation film may be broken or a short circuit may occur between adjacent bonding portions. The passivation film is an uppermost insulating film of the chip and functions to protect the inside from moisture or metal ions from the outside such as a sealing resin. Therefore, the passivation film is higher than the bonding surface of the chip when viewed in a vertical cross section of the chip. When the diameter of the wire exceeds 35 μm, the passive film may be broken by contact with the side surface of the wire near the joint portion or contact with the wire broken at the joint portion at the time of joining.
The core member 2 mainly constitutes the bonding wire 1 of the embodiment and plays a role of the bonding wire 1. As the main component of such a core material 2, silver or copper is used. Here, silver or copper as a main component means that the core material 2 contains silver or copper in an amount of at least 50 mass%. When a material containing silver as a main component is used as the core material 2, the core material 2 may be made of pure silver, and is preferably made of a silver alloy in which an additive element is added to silver. When a material containing copper as a main component is used as the core material 2, the core material 2 may be made of pure copper, and is preferably made of a copper alloy in which an additive element is added to copper. In the case of pure metal, self annealing (self annealing) occurs and the metal becomes too soft, and therefore, the metal has a disadvantage that it is difficult to handle in the manufacturing process. When alloyed, the alloy becomes harder than a pure metal, and has an advantage that the bonding wire can be easily handled in the manufacturing process. Not only these, the use of the core material 2 made of a silver alloy or a copper alloy has an advantage that the Jin Beifu bonding wire 1 having a compressive stress of 290MPa to 590MPa can be easily obtained.
In principle, controlling the compressive stress of the entire wire is the most important condition for achieving the technical problem, and the vickers hardness (Hv) of the core material 2 containing silver or copper as a main component is preferably 40 to 80. The Vickers hardness here is the Vickers hardness of the core material 2 in a cross section of Jin Beifu bonding wire 1. When the vickers hardness of the core material 2 is 40 to 80, the Jin Beifu bonding wire 1 having a compressive stress of 290 to 590MPa is easily obtained. That is, when the vickers hardness of the core material 2 is less than 40, the compressive stress of the Jin Beifu bonding wire 1 becomes too small to obtain a compressive stress of 290MPa or more. When the vickers hardness of the core material 2 exceeds 80, the compressive stress of the Jin Beifu bonding wire 1 becomes too high, and it becomes difficult to obtain a compressive stress of 590MPa or less. The vickers hardness of the core material 2 is more preferably 45 or more, and still more preferably 70 or less. Of course, not only the target compressive stress is easily obtained, but the vickers hardness in this range further improves the wedge bondability due to the synergistic effect of the compressive stress and the hardness. Furthermore, the compressive stress and vickers hardness are not purely proportional.
When the core material 2 is made of a silver alloy, the silver content in the silver alloy is preferably 97 mass% or more. The silver alloy constituting the core material 2 preferably contains at least 1 element selected from copper (Cu), calcium (Ca), phosphorus (P), gold (Au), palladium (Pd), platinum (Pt), nickel (Ni), rhodium (Rh), indium (In), and iron (Fe). The elements added to the silver alloy constituting the core material 2 have the effect of improving the reliability (corrosion resistance) of the gold-coated bonding wire 1 and preventing self-annealing (self-annealing) by improving the vickers hardness of the core material 2. When self-annealing occurs, the yarn becomes too soft, and the yarn becomes difficult to handle and is easily damaged in the production process. However, if the content of the additive element is too large, the specific resistance of the core material 2 increases, and the electrical conductivity of the Jin Beifu bonding wire 1 as the core material 2 decreases. The content of the additive element is preferably in the range of 1 mass ppm to 3 mass% with respect to the entire amount of the wire 1.
When the content of the additive element in the silver alloy constituting the core material 2 is less than 1 mass ppm with respect to the entire amount of the wire 1, there is a possibility that the reliability of the Jin Beifu bonding wire 1, the self-annealing suppression effect of the core material 2, and the like cannot be sufficiently obtained. When the content of the additive element exceeds 3 mass% with respect to the entire amount of the yarn 1, the specific resistance of the Jin Beifu spliced yarn 1 increases. The content of the additive element is preferably set so that the specific resistance of the Jin Beifu bonding wire 1 is 2.3 μ Ω · cm or less.
When the core material 2 is made of a copper alloy, the copper content in the copper alloy is preferably 98 mass% or more. The copper alloy constituting the core material 2 preferably contains at least 1 element selected from phosphorus (P), gold (Au), palladium (Pd), platinum (Pt), nickel (Ni), silver (Ag), rhodium (Rh), indium (In), gallium (Ga), and iron (Fe). The elements added to the copper alloy constituting the core member 2 in the same manner as described above have the effect of improving the reliability (corrosion resistance) of the gold-coated bonding wire 1 and preventing self-annealing (self-annealing) by increasing the vickers hardness of the core member 2. When self-annealing occurs, the wire becomes too soft, and in the manufacturing process, the wire becomes difficult to handle and is easily damaged even by a slight impact. However, if the content of the additive element is too large, the specific resistance of the core material 2 increases, and the function of the core material 2, and further the Jin Beifu bonding wire 1, is lowered. The content of the additive element is preferably in the range of 1 mass ppm to 3 mass% with respect to the entire amount of the wire 1.
When the content of the additive element in the copper alloy constituting the core material 2 is less than 1 mass ppm with respect to the entire amount of the wire 1, there is a possibility that the reliability of the Jin Beifu bonding wire 1, the self-annealing suppression effect of the core material 2, and the like cannot be sufficiently obtained. When the content of the additive element exceeds 2 mass% based on the entire amount of the yarn 1, the specific resistance of the Jin Beifu joined yarn 1 increases. The content of the additive element is preferably set so that the specific resistance of the Jin Beifu bonding wire 1 is 2.3 μ Ω · cm or less.
In the Jin Beifu bonding wire 1 using the core material 2 made of silver or silver alloy, the compressive stress is preferably 290 to 440MPa. By using such a gold-coated bonding wire 1, the wedge bondability can be improved while satisfying the wire characteristics of the Jin Beifu bonding wire 1 using the silver-based core material 2. In addition, in the Jin Beifu bonding wire 1 using the core material 2 made of copper or copper alloy, the compressive stress is preferably 440MPa to 590MPa. By using such a gold-coated bonding wire 1, the wedge bondability can be improved while satisfying the wire characteristics of the Jin Beifu bonding wire 1 using the copper-based core material 2.
The Jin Beifu bonding wire 1 of the embodiment has the coating layer 3 provided on the surface of the core material 2 mainly composed of silver or copper. The coating layer 3 contains gold as a main component. Here, the term "gold-containing" as a main component means that the coating layer 3 contains 50 mass% or more of gold. The coating layer 3 containing gold as a main component is excellent in corrosion resistance of the wire, compatibility with aluminum (Al) or an aluminum alloy (Al alloy) constituting an electrode of the semiconductor chip, gold (Au) or a gold alloy (Au alloy) constituting an electrode of the circuit board, silver (Ag) plating or silver alloy (Ag alloy) plating formed on the surface of the inner lead of the lead frame, and the like, and is easy to diffuse, and therefore, exhibits excellent bonding strength, particularly excellent wedge bonding strength. Therefore, when wedge bonding, particularly continuous bonding by CWB, is performed on the bonding wire 1 having the coating layer 3 containing gold as a main component on the surface thereof, the bonding wire 1 can be wedge bonded with good bonding strength and bonding reliability.
The coating layer 3 may be made of pure gold (the content of gold is 99.9% or more), or may be made of gold alloy in which an additive element is added to gold. The gold alloy constituting the coating layer 3 preferably contains at least 1 element selected from antimony (Sb), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), and bismuth (Bi). The element added to the gold alloy constituting the coating layer 3 exhibits an effect of improving the bonding reliability with aluminum (Al) of the semiconductor chip electrode constituting the gold coating layer 3. The gold coating layer 3 preferably has a film thickness of 5nm to 200nm. By setting the thickness of the gold coating layer 3 to 5nm or more, the wedge bondability to an aluminum electrode, a gold electrode, a silver-plated electrode, or the like formed of the gold coating layer 3 can be sufficiently improved. When the thickness of the gold coating layer 3 exceeds 200nm, the production cost of the Jin Beifu bonding wire 1 increases, which is not preferable. As described above, since the product of the present invention is used also for ball bonding, when the gold coating layer exceeds 200nm, ball formability such as FAB decentering may be reduced. The gold coating layer 3 has a film thickness of preferably more than 20nm, more preferably 50nm or more, and still more preferably 150nm or less.
As described above, the Jin Beifu bonding wire 1 of the embodiment may further include the intermediate metal layer 4 provided between the core material 2 and the coating layer 3, as shown in fig. 3 and 4. The intermediate metal layer 4 contains 1 metal selected from palladium (Pd), platinum (Pt), and nickel (Ni) as a main component. By providing such an intermediate metal layer 4 between the core material 2 and the coating layer 3, not only is reliability (corrosion resistance) improved, but also bleeding of the constituent material of the core material 2 beyond the coating layer 3 to the surface of the bonding wire 1 at high temperature can be suppressed. For example, when copper is exposed to the outermost surface of the core material 2, the possibility of oxidation increases, and when silver is exposed to the outermost surface of the core material 2, the possibility of sulfidation increases. These factors all contribute to lowering the bonding reliability of the gold-coated bonding wire 1 to the electrode. In contrast, by providing the intermediate metal layer 4 between the core material 2 and the coating layer 3, the copper or silver in the high-temperature atmosphere can be suppressed from bleeding to the wire surface, and the bonding reliability can be improved.
The intermediate metal layer 4 may be composed of pure palladium, pure platinum, or pure nickel, or may be composed of an alloy containing 2 or more of these substances. Further, the intermediate metal layer 4 may be formed of a palladium alloy, a platinum alloy, or a nickel alloy containing 1 metal selected from palladium, platinum, and nickel as a main component and an additive element added thereto.
The intermediate metal layer 4 preferably has a thickness of 60nm or less. If the thickness of the intermediate metal layer 4 exceeds 60nm, the original characteristics of the gold-coated bonding wire 1, such as the FAB ball formability, may be impaired. In order to sufficiently obtain the effect of suppressing the exposure of copper or silver to the surface of the wire, the thickness of the intermediate metal layer 4 is preferably 1nm or more. The Jin Beifu bonding wire 1 of the embodiment is not limited to one composed of only the core material 2 and the coating layer 3, or the core material 2, the coating layer 3, and the intermediate metal layer 4. The Jin Beifu binder wire 1 of the embodiment may have another structure as needed, and for example, may have a three-layer coating or four-layer coating structure.
5363 the compressive stress of the Jin Beifu bonding wire 1 was determined as follows. That is, the Jin Beifu bonding wire 1 was cut to several centimeters so as not to apply tension, and a wire sample was prepared. The wire sample was placed on a flat sample table of a compression tester (for example, a micro compression tester model MCT-W-500 manufactured by Shimadzu corporation) in a horizontal direction so that the wire sample was neither stretched nor sagged. Then, as the setting of the apparatus, a round shape was selected as the sample shape, the indenter size was set to 200 μm, the deformation amount in the cross-sectional direction of the wire was set to 60% of the wire diameter, and the maximum load corresponding to the wire diameter was set. For example, when the maximum load is set to a wire diameter of 20 μm, 3.5N is the standard.
Next, the stage was moved so that the filament reached the center of the indenter, and the surface of the filament was compressed using the indenter, thereby obtaining the compressive stress of the filament. According to the device, there is no problem even if the compression stress value is calculated by automatic calculation and used. The calculation formula used is a value obtained by dividing the force applied when the wire diameter is compressed by 60% by the cross-sectional area of the broken wire. Here, a method of calculating the cross-sectional area will be described. When the surface of the yarn is uniformly and infinitely thinly crushed in an ideal state by a ram, the shape (cross section) of the crushed yarn becomes a quadrangle and the thickness approaches 0 infinitely. The transverse length of the cross section is the diameter of the indenter, and the longitudinal length is a value infinitely close to half the circumferential length of the wire. Therefore, the cross-sectional area of the wire is determined by horizontal x vertical, and hence the diameter of the indenter is x (circumference ratio x diameter/2).
In reference to a specific embodiment, a 60% compression of the thread diameter of the thread by 20 μm means that the force (N) applied at the point of breaking the thread to a height of 8 μm is divided by the defined cross-sectional area (mm) 2 ). That is, the value of (indenter size 200 μm =0.2 mm) × (half of the circumferential length of the wire = (wire diameter 0.02mm × 3.14/2)) divided by force becomes compressive stress strictly speaking, at the point where the wire is deformed by 60%, the longitudinal length of the cross-sectional area is not half of the circumferential length because the wire is not completely broken into thin pieces, and there is a slight difference between the measured value calculated using the cross-sectional area and the measured value calculated strictly using the cross-sectional area at the time of 60% deformation, and since a difference exceeding the range having a critical meaning is not generated, the measurement method using this value is adopted in the present invention.
Compressive stress of the wire (MPa) = force applied when deformed by 60% in relation to the diameter of the wire (N)/((circumference ratio × diameter of wire (mm)/2) × diameter of indenter (mm))
Note that after the wire was compressed, the wire after the test was collected and the shape of the indentation was observed using a scanning electron microscope. In the state of indentation, as shown in fig. 5 (additional SEM image), it was confirmed that the length of indentation was ± 20% of the indenter diameter, and the crushing width was symmetrical with the longitudinal direction of the wire as the axis. If these conditions are not satisfied, the measurement value may not be an accurate measurement value, and therefore, re-measurement is performed. The measurement values are the average of 3 measurements in MPa. Further, the power unit of the compression test apparatus was kgf/mm 2 When it is used, the amount of the catalyst is 1kgf/mm 2 A conversion formula of =9.8 MPa. The reason why the compression deformation amount is 60% of the wire diameter is that the average breakage rate of the wire in wedge bonding is about 60%.
The vickers hardness of the cross section of the core material 2 was measured as follows. That is, jin Beifu joined yarn was cut into a length of several centimeters to prepare a plurality of yarn samples. The wire samples were attached straight and flat to a metal (Ag plated frame) plate while being considered neither stretched nor sagging. Then, the wire sample is placed in a cylindrical mold (mold) for each metal plate so that the metal plate becomes the bottom surface of the cylinder, the embedding resin is poured into the mold, and then the curing agent is added to cure the resin. Next, the cylindrical resin containing the cured yarn sample was roughly ground using a grinder so that the cross section of the yarn was exposed. Thereafter, the cut surface is finished by final polishing, and then the residual strain of the polished surface is removed by ion milling to obtain a smooth surface. Further, the ion milling apparatus was finely adjusted so that the cut surface of the wire became perpendicular to the longitudinal direction of the wire. The cross section of the wire sample (i.e., the polished surface of the sample) was fixed on a sample stage of a hardness tester (for example, HM-220 manufactured by Mitutoyo) so as to be parallel to the sample stage, and the Vickers hardness was measured in the vicinity of the center of the wire cross section under conditions of a test force of 0.001kgf, a load time of 4.0 seconds, a holding time of 10.0 seconds, an unload time of 4.0 seconds, and an approach speed of 60.0 um/second. The hardness measurement was performed for 5 pieces, and the average value was obtained.
In Jin Beifu the bonding wire 1, the content of the additive element to the entire wire 1 when the core material 2 is made of a silver alloy or a copper alloy, the content of the metal phase to the entire wire 1 when the coating layer 3 is made of a gold alloy, the content of the additive element to the entire wire 1 when the coating layer 3 is made of a gold alloy, the content of palladium, platinum, or nickel to the entire wire 1 when the intermediate metal layer 4 is made of an alloy, and the content of the additive element to the entire wire 1 when the intermediate metal layer 4 is made of an alloy were measured as follows. That is, first, in order to calculate the gold content, the bonding wire 1 was placed in dilute nitric acid, the core material 2 was dissolved, and then a solution was collected. Hydrochloric acid was added to the solution, and a constant volume solution was prepared using ultrapure water. The content of the additive element in the core material 2 was measured by ICP-Emission spectrography (ICP-AES: inductively Coupled Plasma Atomic Spectroscopy) or Inductively Coupled Plasma Mass Spectrometry (ICP-MS: inductively Coupled Plasma-Mass Spectrometry) using the constant volume solution.
The thicknesses of coating layer 3 and intermediate metal layer 4 were measured as follows. That is, the elemental composition was analyzed in the depth direction from the surface of Jin Beifu bonding wire 1 using a scanning Auger Electron Spectroscopy (AES) analyzer (e.g., JAMP-9500F, manufactured by Japan electronic division). The AES analyzer was set to 1 time set with an acceleration voltage of 10kV for the electron beam, a current of 50nA, a beam diameter of 5 μm, an acceleration voltage of 1kV for the argon ion sputtering, and a sputtering rate of 2.5 nm/min (SiO) 2 Scaling). The average concentration of the metal phase with respect to the total amount of gold, silver, or copper was determined by analyzing the surface of the Jin Beifu bonding wire 1 to the position where the detected concentration of the main component of the core material in the depth direction reached 50 atomic% or more. When the intermediate metal layer 4 is provided, the average concentrations of gold and the element M with respect to the total amount of the main constituent element M of the intermediate metal layer 4 and gold and silver or copper are determined.
The coating layer 3 is defined as a region from the surface of the wire 1 to a position where the ratio of gold to the total amount of silver or copper and gold is 50.0 atomic%, and the thickness of this region is determined as the thickness of the coating layer 3. The position where the ratio of gold is 50.0 atomic% becomes the boundary between the core material 2 and the coating layer 3. The intermediate metal layer 4 is defined as a region from a position where the ratio of gold is 50.0 atomic% to the total amount of silver or copper and gold and the element M to a position where the ratio of the element M is 50.0 atomic%, and the thickness of the region is determined as the thickness of the intermediate metal layer 4.
Next, a method for producing Jin Beifu as the bonding wire 1 of the embodiment will be described. The method for producing Jin Beifu as the embodiment is not particularly limited to the production method described below. The Jin Beifu bonding wire 1 of the embodiment is obtained, for example, as follows: the wire material is obtained by forming a layer containing gold as a main component on the surface of a wire rod containing silver or copper as a main component, which is to be the core material 2, to produce a wire material, drawing the wire rod to a wire diameter required for the gold-coated bonding wire 1, and performing heat treatment or the like as necessary. In the case of the gold-coated bonding wire 1 having the intermediate metal layer 4, for example, a layer to be the intermediate metal layer 4 and a layer containing gold as a main component are sequentially formed on the surface of a silver or copper wire material to be the core material 2 to prepare a wire material, and at the same time, wire drawing processing to obtain a wire diameter required for the gold-coated bonding wire 1, heat treatment, and the like are performed as necessary, thereby obtaining the gold-coated bonding wire 1.
When silver or copper is used as the core material 2, silver or copper of a predetermined purity is melted, and when a silver alloy or copper alloy is used, silver of a predetermined purity is melted together with an additive element or copper of a predetermined purity is melted together with an additive element, thereby obtaining a silver core material or a copper core material. The melting is carried out using a heating furnace such as an arc furnace, a high-frequency heating furnace, a resistance heating furnace, or a continuous casting furnace. In order to prevent the mixing of oxygen or hydrogen from the atmosphere, the silver molten metal or the copper molten metal in the heating furnace is preferably kept in a vacuum or an inert atmosphere such as argon or nitrogen. The melted core material is solidified by continuous casting from a heating furnace so as to have a predetermined wire diameter, or an ingot is produced by casting the melted core material in a mold, and the ingot is rolled. If necessary, a heat treatment is applied to the wire, and the wire is drawn to a predetermined wire diameter to obtain a silver wire or a copper wire (including a silver alloy wire and a copper alloy wire).
As a method for forming a gold layer or a layer to be the intermediate metal layer 4 on the surface of the silver wire or the copper wire, for example, a plating method (wet method) or an evaporation method (dry method) is used. The plating method may be any one of an electrolytic plating method and an electroless plating method. In electrolytic plating such as impact plating or flash plating, the plating speed is high, and when applied to gold plating, good adhesion of the gold layer to a silver wire or a copper wire is obtained. In the plating method, in order to contain an additive element in a gold layer or a palladium layer, a platinum layer, or a nickel layer which is the intermediate metal layer 4, for example, a plating solution containing a plating additive containing an additive element in a plating solution of a gold plating solution or a constituent element of the intermediate metal layer 4 is used in the above electrolytic plating. At this time, the amount of the additive element in the coating layer 3 or the intermediate metal layer 4 can be adjusted by adjusting the kind or amount of the plating additive.
As the vapor deposition method, physical Vapor Deposition (PVD) such as sputtering, ion plating, and vacuum vapor deposition, or Chemical Vapor Deposition (CVD) such as thermal CVD, plasma CVD, and Metal Organic Chemical Vapor Deposition (MOCVD) can be used. By these methods, there is no need to wash the gold coating layer or the intermediate metal layer after formation, and there is no concern about surface contamination or the like during washing. As a method of containing an additive element in a gold layer or a palladium layer, a platinum layer, or a nickel layer as the intermediate metal layer 4 by a vapor deposition method, there is a method of forming a gold layer or an intermediate metal layer by magnetron sputtering or the like using a gold target containing an additive element or a constituent material target of the intermediate metal layer 4. When other methods are applied, a raw material containing a desired additive element in the constituent material of the gold material or the intermediate metal layer 4 may be used.
As another method, there is a cladding method in which a tubular pipe is formed of a material to be coated in advance, and a core material is inserted into the pipe to manufacture the pipe.
The rate of drawing is determined by the final wire diameter or application of the produced Jin Beifu bonding wire 1. The reduction ratio of the wire drawing is generally preferably 90% or more as a reduction ratio of the coated silver wire or copper wire to a final wire diameter. The processing rate can be calculated as the reduction of area of the cross-sectional area of the yarn. The wire drawing is preferably performed by stepwise reducing the wire diameter using a plurality of diamond dies. In this case, the reduction of area (working ratio) per 1 diamond die is preferably 5% to 15%.
The silver wire or copper wire coated with the gold layer or the constituent material layer of the intermediate metal layer 4 is preferably drawn to a final wire diameter and then subjected to final heat treatment. The final heat treatment is performed in consideration of a strain relief heat treatment for removing a strain of a metal structure remaining in the wire 1 in the final wire diameter or necessary wire characteristics. The strain relief heat treatment is preferably performed at a temperature and for a time determined in consideration of necessary wire characteristics, particularly compressive stress of the wire 1. In addition, at any stage of the wire production, heat treatment corresponding to the target may be performed. As such heat treatment, there are strain relief heat treatment in the wire drawing process, diffusion heat treatment for improving adhesion after forming a constituent material layer of a gold layer or an intermediate metal layer 4, and the like. By performing diffusion heat treatment, adhesion between the core material 2 and the coating layer 3 can be improved. In order to facilitate adjustment of the heat treatment conditions, the heat treatment is preferably a running heat treatment in which the wire is heat-treated in a heating atmosphere heated to a predetermined temperature. For the inter-walk heat treatment, the heat treatment time can be calculated by using the passing speed of the wire and the passing distance of the wire in the heating device. As the heating device, an electric furnace or the like is used. While inhibiting surface oxidation of the yarn, N flows 2 Or an inert gas such as Ar is also effective when heating. Using N when necessary 2 And H 2 The reducing mixed gas of (2).
In the above-described process for producing the gold-coated bonding wire 1, the compressive stress of 290MPa to 590MPa can be obtained by appropriately controlling the production conditions such as the heat treatment conditions depending on the composition of the metal material (silver-based material or copper-based material) constituting the core member 2, the constituent material or thickness of the coating layer 3 or the intermediate metal layer 4 formed as needed, the wire diameter of the bonding wire 1, and the like. For example, the core material 2 is preferably made of a silver alloy or a copper alloy, and the compressive stress tends to be higher as the amount of the additive element in the silver alloy or the copper alloy is larger. Further, the thicker the coating layer 3 is, the lower the compressive stress tends to be. Further, the core material 2 using the copper alloy tends to have a higher compressive stress than the core material 2 using the silver alloy.
The heat treatment conditions are preferably selected according to the tendency of the constituent material of the gold-coated bonding wire 1 and the like to cause compressive stress. The heat treatment is preferably performed in both the intermediate stage and the final stage. The higher the temperature is, the lower the compressive stress tends to be in the final heat treatment. The intermediate heat treatment tends to lower the compressive stress as the temperature is higher. From these points, when a material exhibiting a tendency to have a high compressive stress on the constituent material is used, it is preferable to set the intermediate heat treatment temperature to 400 to 600 ℃ and set the heat treatment time to 0.2 to 20 seconds. When a material exhibiting a tendency to have a low compressive stress is used as the constituent material, it is preferable that the intermediate heat treatment temperature is set to 200 ℃ or more and less than 400 ℃ and the heat treatment time is set to 0.2 to 20 seconds. Further, when a material exhibiting a tendency to have a high compressive stress is used as the constituent material, the final heat treatment temperature is preferably set to 350 to 650 ℃ and the heat treatment time is preferably set to 0.01 to 5 seconds. When a material exhibiting a tendency to have a low compressive stress is used as the constituent material, the final heat treatment temperature is preferably set to 150 to 350 ℃ and the heat treatment time is preferably set to 0.01 to 5 seconds.
Further, even if the heat treatment conditions are the same, the compressive stress is affected by the structure of the heat treatment apparatus or the kind or amount of the additive element in the core material. In this regard, in the production process of Jin Beifu bonding wires according to this embodiment, the tensile rate in the heat treatment is adjusted by using the final heat treatment, whereby the compressive stress of the wires can be controlled. In the case of a wire having a core material containing copper as a main component as a constituent material, the elongation is preferably adjusted to 5.0% to 20.0%, more preferably 8.0% to 20.0%. In the case of a yarn having a core material containing silver as a main component as a constituent material, the elongation is preferably adjusted to 1.5% to 15.0%, more preferably 2.0% to 11.0%.
The elongation is a value obtained by a tensile test of the bonding wire. The elongation can be measured according to JIS-Z2241 or JIS-Z2201. For example, when a bonding wire having a length of 10cm is stretched at a speed of 20mm/min and a dynamometer specification of 2N using a tensile testing apparatus (for example, autocom manufactured by TSE, inc.), the ratio of the tensile length until the breaking point is reached is calculated. The elongation is preferably an average of 5 in consideration of variations in measurement results.
The above description is supplemented. Normally, it is desirable to adjust the final heat treatment conditions while measuring the compressive stress so that the final product is within the range of the target compressive stress, but here, from the viewpoint of expecting simplification in the manufacturing operation, the tensile rate of the wire which is easy to measure is substituted as a rough criterion of the compressive stress. Of course, the tensile ratio is not limited to the range of the target compressive stress.
(semiconductor device)
Next, a semiconductor device using the Jin Beifu bonding wire 1 according to the embodiment will be described with reference to fig. 6 to 8, 11, and 12. Fig. 6 is a sectional view showing a stage before the semiconductor device of the embodiment is resin-sealed, fig. 7 is a sectional view showing the semiconductor device of the embodiment after the resin-sealing, and fig. 8 is a sectional view showing a wedge-shaped bonding portion of Jin Beifu bonding wires 1 bonded to electrodes of a semiconductor chip in the semiconductor device of the embodiment. Fig. 11 and 12 are sectional views of modifications of the semiconductor device according to the embodiment.
As shown in fig. 6 and 7, the semiconductor device 10 according to the embodiment (semiconductor device 10X before resin sealing) includes a circuit board 12 having electrodes (board electrodes) 11, a plurality of semiconductor chips 14 (14A, 14B, 14C) each having at least 1 electrode (chip electrode) 13 and disposed on the circuit board 12, the electrodes 11 of the circuit board 12, the electrodes 13 of the semiconductor chips 14, and bonding wires 15 (Jin Beifu bonding wires 1) connecting the electrodes 13 of the plurality of semiconductor chips 14. The circuit board 12 is, for example, a printed wiring board or a ceramic circuit board in which a wiring network is provided on the surface or inside of an insulating base material such as a resin material or a ceramic material and electrodes connected to the wiring network are provided on the surface.
Fig. 6 and 7 show the semiconductor device 10 in which the plurality of semiconductor chips 14 are mounted on the circuit board 12, but the configuration of the semiconductor device 10 is not limited to this. For example, the semiconductor chip may be mounted on a lead frame, and in this case, the electrodes of the semiconductor chip are connected to inner leads functioning as internal terminals (electrodes) of the lead frame via bonding wires 15. The number of semiconductor chips 14 mounted on the circuit board 12 or the lead frame may be 1 or more. The bonding wire 15 is applied to at least 1 connection between the electrode 11 of the circuit board 12 and the electrode 13 of the semiconductor chip 14, the electrode of the lead frame and the semiconductor chip, and the electrodes 13 of the plurality of semiconductor chips 14, and is wedge-bonded to at least 1 of these connections (2 electrodes). As described later, when the plurality of semiconductor chips 14 are stacked and mounted on the circuit board 12 or the lead frame in stages, the plurality of semiconductor chips 14 and the semiconductor chip 14 and the circuit board 2 may be connected to each other continuously by wedge bonding using the CWB with 1 bonding wire 15.
In the plurality of semiconductor chips 14 of the semiconductor device 10 shown in fig. 6 and 7, the semiconductor chips 14A and 14C are mounted on the chip mounting region of the circuit board 12 via a die bonding material 16. The semiconductor chip 14B is mounted on the semiconductor chip 14A via the die bonding material 16. One electrode 13 of the semiconductor chip 14A is connected to the electrode 11 of the circuit board 12 via a bonding wire 15, the other electrode 13 is connected to the electrode 13 of the semiconductor chip 14B via a bonding wire 15, and the other electrode 13 is connected to the electrode 13 of the semiconductor chip 14C via a bonding wire 15. Further 1 electrode 13 of the semiconductor chip 14B is connected to the electrode 11 of the circuit board 12 via a bonding wire 15. Further 1 electrode 13 of the semiconductor chip 14C is connected to the electrode 11 of the circuit board 12 via a bonding wire 15.
The semiconductor chip 14 includes an Integrated Circuit (IC) formed of a silicon (Si) semiconductor, a compound semiconductor, or the like. The chip electrode 13 is formed of, for example, an aluminum electrode having an aluminum (Al) layer, an AlSiCu, alCu, or other aluminum alloy layer at least on the outermost surface. The aluminum electrode is formed by coating the surface of a silicon (Si) substrate with an electrode material such as Al or an Al alloy so as to be electrically connected to internal wiring, for example. The semiconductor chip 14 performs data communication with an external device via the substrate electrode 11 and the bonding wire 15, and is supplied with power from the external device.
The electrode 11 of the circuit board 12 is electrically connected to the bonding wire 15 via the electrode 13 of the semiconductor chip 14 mounted on the circuit board 12. In the semiconductor device 10 of the embodiment, the bonding wire 15 is formed of the Jin Beifu bonding wire 1 of the above-described embodiment. In some of the bonding wires 15, one end thereof is ball-bonded (1 st bonding) to the chip electrode 13, and the other end thereof is wedge-bonded (2 nd bonding) to the substrate electrode 11. The ball bonding and the wedge bonding may be reversed, and may be ball bonding (1 st bonding) on the substrate electrode 11 and wedge bonding (2 nd bonding) on the chip electrode 13. Similarly, when the electrodes 13 of the plurality of semiconductor chips 14 are connected by the bonding wire 15, one end thereof is ball-bonded (1 st bonding) to the chip electrode 13, and the other end thereof is wedge-bonded (2 nd bonding) to the other chip electrode 13. The electrode 13 of the semiconductor chip 14 electrically bonded by the bonding wire 15 also includes a bump (not shown) bonded to the electrode of the semiconductor chip 14 in advance.
The wire bonding with the bonding wire 15 is performed by, for example, melting one end of the bonding wire 15 by electric discharge or the like, solidifying the melted end into a ball by surface tension or the like to form an FAB, ball-bonding the FAB to the electrode 13 of the semiconductor chip 14, then lifting up the bonding tool (bonding pin) to form a ring, pressing the bonding wire 15 against the electrode 11 of the circuit board 12, and applying ultrasonic waves and a load to perform wedge bonding. As shown in fig. 8, after the wedge bond 17 is formed on the substrate electrode 11, the bonding wire 15 is torn off, and the connection at 1 is completed. The same applies to the case where the electrodes 13 of the semiconductor chip 14 are connected by the bonding wire 15 (between the electrodes 13 different from the built-in chip). Thereafter, the semiconductor device 10 is manufactured by forming the sealing resin layer 18 on the circuit substrate 12 so as to seal the plurality of semiconductor chips 14 and the bonding wires 15 with resin. The semiconductor device includes, specifically, a logic IC, an analog IC, a discrete semiconductor, a memory, an optical semiconductor, and the like.
In the semiconductor device 10 of the embodiment, when the Jin Beifu bonding wire 1 used as the bonding wire 15 has a compressive stress of 290MPa to 590MPa, the bonding wire 15 can be satisfactorily wedge-bonded under a wide range of ultrasonic conditions or load conditions even when placed in a position where the electrode 11 of the circuit board 12 or the electrode 13 of the semiconductor chip 14, particularly the chip electrode 13, is not suitable for bonding, for example, where there is no under-support, and therefore, stable wedge bonding strength can be obtained without damaging the semiconductor chip 14. Further, since the wedge width can be controlled within an appropriate range, short-circuiting between electrodes with a narrowed pitch or the like can be suppressed. This can provide a semiconductor device in which the reliability of connection between the electrodes of the bonding wire 15 is improved.
Next, another semiconductor device 10 will be described with reference to fig. 11 and 12. The semiconductor device 1 shown in fig. 11 includes 4 semiconductor chips 14A, 14B, 14C, and 14D stacked in multiple stages on a circuit board 12. The semiconductor chips 14A, 14B, 14C, and 14D are stacked in stages so that the electrodes 13 thereof are exposed. The electrodes 13 of the semiconductor chips 14A, 14B, 14C, and 14D and the electrodes 11 of the circuit board 12 are continuously connected by 1 bonding wire 15. That is, 4 electrodes 13 and the substrate electrode 11 are connected by 1 bonding wire 15 by the CWB. Further, the arrow indicates the joining direction.
Specifically, the bonding wire 15 held by the bonding tool (bonding pin) is first wedge-bonded to the electrode 13 of the semiconductor chip 14D on the uppermost stage. Then, without tearing the bonding wire 15, the bonding tool (bonding pin) is directly lifted up to form a loop, and the bonding wire 15 is moved to the electrode 13 of the semiconductor chip 14C to perform wedge bonding. Similarly, the bonding wire 15 is wedge-bonded to the electrode 13 of the semiconductor chip 14B and the electrode 13 of the semiconductor chip 14A in this order without peeling the bonding wire 15. After the bonding wires 15 are sequentially wedge-bonded to the electrodes 13 of the semiconductor chips 14D, 14C, 14B, and 14A, the bonding wires 15 are similarly wedge-bonded to the electrodes 11 of the circuit board 12, and then the bonding wires 15 are torn off. In this way, the electrodes 13 of the semiconductor chips 14A, 14B, 14C, and 14D are continuously connected to the electrodes 11 of the circuit board 12 by 1 bonding wire 15 without tearing the bonding wire 15 halfway.
Since the 4 chip electrodes 13 and the substrate electrode 11 are continuously wedge-bonded and electrically connected to each other by 1 bonding wire 15, the number of times of ball formation and the number of times of wire tearing can be reduced, and thus, the bonding speed can be increased and the productivity can be improved. When continuous wedge bonding is performed, wedge bonding of the bonding wire 15 becomes important. In this regard, since the bonding wire 1 is used as the bonding wire 15, which is Jin Beifu having a compressive stress of 290MPa to 590MPa, the bonding property to the electrodes 13 and 11 in the continuous wedge bonding can be improved. Therefore, the chip electrode 13 can be wedge-bonded favorably under a wide range of bonding conditions without damaging the semiconductor chip 14. Therefore, the productivity or reliability of the semiconductor device 10 to which the CWB is applied can be improved.
Wire bonding to which the CWB is applied is not limited to the structure shown in fig. 11. For example, as shown in fig. 12, the bonding wire 15 may be ball-bonded to the substrate electrode 11 of the circuit substrate 12 on the lowermost stage to form a ball-bonded portion 19, and the bonding wire 15 may be wedge-bonded to the electrodes 13 of the semiconductor chips 14A, 14B, 14C, and 14D in this order without peeling off the bonding wire 15, and then the bonding wire 15 may be peeled off. In the semiconductor device 10 to which the CWB is applied, the effect of improving the wedge bondability of the bonding wire 15 can improve the continuous wedge bondability, and the productivity and reliability of the semiconductor device 10 to which the CWB is applied can be improved. The arrows indicate the direction of engagement.
In the semiconductor device 10 of the embodiment, when 2 electrodes are connected by the bonding wire 15, the wedge bonding may be performed only for at least 1 electrode, and thus the effect of improving the wedge bonding property obtained by the bonding wire 1 of Jin Beifu of the embodiment, the effect of improving the bonding strength and the bonding reliability of the wedge bonding based on the wedge bonding, and the like can be exhibited. However, in order to more effectively exhibit the effect of improving wedge bondability obtained by the bonding wire Jin Beifu of the embodiment, at least 1 of the 2 electrodes connected by the bonding wire 15 is preferably the electrode 13 of the semiconductor chip 14, and the semiconductor device 10 in which such a chip electrode 13 is wedge bonded is preferable. In particular, as shown in fig. 11 and 12, the semiconductor device 10 according to the embodiment is preferably a semiconductor device to which a CWB is applied and which is wire-bonded, and in this case, excellent wedge bondability, and excellent bonding strength and bonding reliability based on the wedge bondability can be more effectively exhibited.
Examples
Next, an embodiment of the present invention will be described. The present invention is not limited to the following examples.
(manufacturing method and Properties of example)
The core materials shown in Table 1 were prepared, continuously drawn to an intermediate wire diameter of 0.2 to 0.5mm, and then immersed while continuously feeding the core materials in a gold electrolytic plating bath at a current density of 0.15 to 2.00A/dm 2 The current of (2) forms a gold coating layer.
In examples 16 to 19, 21, and 31 to 36, the intermediate layers shown in table 1 were formed by the same electrolytic plating method before the formation of the gold coating layer. Examples 1 to 19 were subjected to intermediate drawing to an intermediate wire diameter of 38 μm to 100 μm, examples 22 to 36 were subjected to intermediate drawing to a diameter of 50 μm to 200 μm, and heat treatment was carried out at an intermediate heat treatment temperature (set temperature of an electric furnace) shown in Table 1 at a feeding speed of 0.20 to 1.00 m/sec. The heat treatment is about 0.5 to 3 seconds in terms of time. Thereafter, wire drawing was performed until the final wire diameters shown in table 1 were reached, and final heat treatment was performed by adjusting the heat treatment temperature and the feed rate to the target draw ratios shown in table 1. Thus, jin Beifu bonding wires of examples 1 to 34 were produced.
The compressive stress and vickers hardness of the cross section of the core material of Jin Beifu binder threads having completed these were measured by the above-described methods, and the results thereof are shown in table 1. The gold-coated bonding wire thus obtained was subjected to characteristic evaluation described later.
(production method and Properties of comparative example)
Comparative examples will be described. Bonding wires having compressive stress outside the range of the present invention are shown in comparative examples 1 to 6 and 11 to 18, and bonding wires having a coating layer other than gold are shown in comparative examples 10, 19 and 20. In addition, comparative examples 7 to 9 show bonding wires without a coating layer formed thereon. The bonding wires of comparative examples 1 to 20 were produced by the same production method as in examples except that the above was changed. The compressive stress of these bonding wires and the vickers hardness of the cross section of the core material were measured by the above-described methods in the same manner as in examples, and the results are shown in table 1. The thus-obtained bonding wire was subjected to characteristic evaluation described later.
(evaluation of wedge bondability in examples and comparative examples)
The wedge bonding evaluation of the sample prepared above will be described. The opponent performing the wedge bonding had 2 kinds of electrodes on the circuit substrate and chip electrodes. As will be described in detail later, the following 3 evaluations were performed as evaluation items: whether a problem occurs in continuous bonding (continuous bonding), whether the bonding wire is perfectly bonded (bonding strength), and whether the chip is not damaged. The evaluation results are shown in tables 1 and 2. However, the chip damage evaluation is only a precision and fragile chip electrode.
(bonding energy for wedge bonding evaluation)
As described above, in particular, when bonding a bonding wire to an electrode of a chip stacked in a plurality of stages by wedge bonding, since it is necessary to bond the chips tightly without causing breakage of the chips depending on the bonding position, place, or the like, a plurality of different and wide bonding conditions are required. As an index for evaluating the suitability of the wire, the bonding energy is suitable as an evaluation method, and it can be confirmed without any problem whether or not the 3 evaluation items are acceptable even if the condition of the bonding energy is changed in a wide range.
The bonding energy is roughly dependent on the breakage rate of the wire. For example, in order to crush the yarn, it is necessary to comprehensively increase the conditions of the load pressure, the load time, the ultrasonic wave, and the like to the yarn. Here, the bonding energy was classified into 3 levels according to the breakage rate with respect to the wire diameter ((thickness of the wire to be broken/diameter of the wire before breaking) × 100) (%). That is, the breakage rate of the yarn was 47% to 53% and defined as low bonding energy, 57% to 63% and 67% to 73% as high bonding energy. These bonding energy conditions were adjusted by using a bonder apparatus (IConn PLUS manufactured by Kulick & Sofaa).
As described above, since 2 types of electrodes of the circuit board and the chip electrode were wedge-bonded, the under support was also strong in the wedge bonding of the circuit board to the electrode, and the bonding environment was not different from that of the chip electrode to such an extent, the wedge bondability was evaluated only under the condition of high bonding energy here. On the other hand, since the possibility that the chip electrode enhances various bonding environments is high, the wedge bondability is evaluated under the condition of 3 levels of bonding energy of low, medium, and high levels.
Further, in order to simulate a severe bonding environment close to the mounting level of the continuous wedge bonding of the more severe and precise multi-layer chip electrodes, the chips used in table 1 were ones in which the adhesion of the Al electrode was reduced as compared with the conventional chips. The chip has a cross-sectional structure comprising an insulating film (SiO) on a Si substrate 2 Film) on the SiO 2 An Al film is formed on the film. On the other hand, the cross-sectional structure of a conventional chip has an insulating film (TEOS: tetraethoxysilane) on a Si substrate, and a TiN layer is provided between the insulating film and an Al electrode, thereby improving the adhesion of the Al electrode. By using this chip, chip damage or chip electrode (pad) damage (a phenomenon in which an Al electrode is peeled off from the chip during a loop-back operation after wedge bonding) is liable to occur. Further, the electrode thickness was 0.8 μm, and the material of the electrode was Al-0.5% Cu or Al-1% Si-0.5% Cu.
(continuous bonding property of wedge bonding on substrate electrode)
The wedge bondability on the substrate electrode was evaluated by continuous wire bonding of the chip electrode and the substrate electrode (lead frame). The wedge bonding conditions were 36 cycles x 2 sets of wedge bonds for a total of 72 for the Ag plated lead frames under the high bonding conditions described. The 1 cycle here means that the cycle is continued 36 times for 2 groups from the ball bonding on the chip electrode to the wedge bonding on the frame and the tearing off of the wire. After 72 times of total bonding, when the device was not stopped due to failure of the wedge-shaped bonding portion or problems such as cutting of the wire, the continuous bondability was good, and thus the device was marked "excellent". When the number of times of stopping the apparatus due to the problem of the wedge-shaped joint is less than 2 times, the number of times of stopping the apparatus in the mass production process can be improved. When the number of times of stopping the apparatus was 2 or more, it was regarded as "poor", and it was marked as "x".
(tensile test on substrate electrode = evaluation of bonding strength)
The sample wedge-bonded by the wire bonding was hooked around the wedge bonding of the sample by using an adhesive force tester (for example, model 4000 of adhesive force tester manufactured by Daisy corporation), and 20 wires were randomly drawn out from the sample performed under the above conditions to perform a tensile test, and the presence or absence of an increase was confirmed (one of fracture modes). The adhesion tester was set to a dynamometer WP100, a measurement range 50% and a test speed 250 μm/min. In the breaking mode of the tensile test, the rise in which the wire at the joint portion was not peeled off from the substrate was referred to as "excellent" and was designated as "excellent". When the number of the rise occurrences is less than 3, the number of the rise occurrences can be improved by the mass production process, and is indicated as "o". When the number of the rise was 3 or more, the test piece was judged as "X". Further, the tensile strength (pull strength) of less than 2gf was not good even when 1 piece was generated, and indicated as "x".
(continuous bondability of wedge-bonding on chip electrode)
This evaluation was performed using a device having the chip mounted on an Ag plated lead frame. On the chip, 360 (10/cycle x 36 cycles) continuous wedge bonding was performed using a CWB approach. The wedge bonding conditions (3 levels of low bonding energy, medium bonding energy, high bonding energy) were set in 1 cycle with 3 wedges bonded per 1 cycle per wedge bonding condition x 3 levels (the first 1 st bond was made using ball bonding, so the wedge bonding position became 9 in 1 cycle). Therefore, the number of wires bonded at each level in 1 chip is 108 (the number of wedge bonds is 108 bonding wires =3 × 36 cycles). The shape of the welding pin for wedge bonding uses an H diameter: 1.2-1.3 times of the diameter of the silk thread, CD diameter: 1.5-1.8 times of the diameter of the silk thread, T: 3.5-3.8 times of the diameter of the silk thread, FA:0 °, OR diameter: matte pattern with surface finish of 4-12 μm. When the device was not stopped due to problems such as insufficient wedge bond, peeling of Al film, and wire cutting, the continuous bondability of wedge bonding at each bonding energy was good, and was designated "excellent". If the number of times of stopping the apparatus due to the problem of the wedge-shaped joint portion at each joining energy is less than 5 times, it can be improved in the mass production process, and is marked as "o". When the number of times of stopping the apparatus was 5 or more, the wedge-shaped bonding property at the bonding energy was poor and was designated as "x".
(tensile test on chip electrode = evaluation of bonding strength)
A sample prepared by wedge bonding on the chip was hooked on a bonding force tester (for example, model 4000 of the bonding force tester manufactured by Daisy corporation), 20 wires were randomly drawn out from 108 wires for each bonding energy, and a tensile tension test was performed to confirm the breaking mode. The adhesion tester was set to a dynamometer WP100, a measurement range 50% and a test speed 250 μm/min. In the fracture mode of the tensile test, when the rise of the separation of the wire at the joint portion from the chip electrode did not occur, the wedge bond strength at the bonding energy was good and was marked "excellent". When the number of the rise occurrences is less than 3, the number of the rise occurrences can be improved by the mass production process, and is indicated as "o". When the number of the rise occurred was 3 or more, the wedge bond strength at the bonding energy was poor and indicated as "x".
(evaluation of chip Damage)
This evaluation was carried out by using a device having the chip mounted on an Ag plated lead frame, and 64 (16 pieces/cycle × 4 group) continuous bonds were carried out on the chip by using a CWB method. The wedge bonding conditions (3 levels of low bonding energy, medium bonding energy, and high bonding energy) were set in 1 cycle, and the bonding energy was divided into 3 bonding energy levels in units of 5 pieces per 1 cycle (similarly to the above, since the first 1 st piece was performed by ball bonding, the total number of wedge bonding positions became 15). Each 1 chip becomes 20 wires bonded at each level (wedge bond number 20 bond wires =5 × 4 groups). The wedge bonding pins used were the same as those used in the 20 th to the 4 th rows on page 26.
After bonding, in order to melt the chip electrode and expose the chip base, the wedge-bonded sample was immersed in an aqueous sodium hydroxide solution for about 30 minutes to confirm that the wire was peeled off the chip, and after washing the sample with pure water, alcohol and drying, the exposed chip base (Si or SiO) was subjected to light microscopy 2 ) The joints at each joint energy level at 10 are observed randomly. When there was no pad (chip electrode) crack, the wedge bondability at this bonding energy was good, and was designated as "very good". If 1 pad crack was generated, the wedge bonding property at this bonding energy was poor and was indicated as "x".
With respect to the wedge bondability of tables 1 and 2, even if there are 1 defect "x" in the above evaluation items of the continuous bondability, the bonding strength, and the chip damage, it is estimated that the wedge bondability cannot be applied to the continuous wedge bonding in the multi-step laminated structure, and the wedge bondability is comprehensively evaluated as a defect. Further, the evaluation without "x" was qualified in the overall evaluation.
Figure BDA0003882012000000281
Figure BDA0003882012000000291
As can be seen from table 2, the Jin Beifu bonding wires having a compressive stress of less than 290MPa or more than 590MPa had poor wedge bondability to the substrate electrode or the chip electrode, both when silver core material was used (comparative examples 1 to 6) and when copper core material was used (comparative examples 11 to 18). Further, it is found that the bonding wire having no gold coating layer or the bonding wire coated with a coating layer other than gold has poor wedge bondability to both the substrate electrode and the chip electrode. In particular, it is considered that, in all the bonding wires of the comparative examples, since at least 1 or more of defects "x" are generated in any of the evaluations of the continuous bondability, the tensile test, and the chip damage, the technical problem of the bonding wire in the CWB including the continuous multi-stage wedge bonding has not been overcome yet.
As shown in Table 1, the Jin Beifu bonding wires of examples 1 to 36 having compressive stresses of 290MPa to 590MPa had excellent wedge bondability to both the substrate electrode and the chip electrode. In particular, in the evaluation of wedge bonding properties on chip electrodes, even under wedge bonding conditions in which 3 levels of low, medium, and high bonding energy were mixed, the evaluation of continuous bonding properties, tensile test, and chip damage was good, and the following conclusion was reached: adequate results for overcoming technical problems in soft surfaces (bonding wires) of CWBs are obtained.
According to the present invention, it is possible to provide a bonding wire in which material cost and production cost are suppressed, particularly in response to market demands for large capacity and miniaturization of a memory capacity represented by a semiconductor memory, and it is considered that this can contribute greatly to the development of the semiconductor industry, the electronics industry, and the like.
Description of the symbols
1 Jin Beifu bonding wire, 2 core material, 3 coating layer, 4 intermediate metal layer, 10 semiconductor device, 11 substrate electrode, 12 circuit substrate, 13 chip electrode, 14A, 14B, 14C, 14D semiconductor chip, 15 bonding wire, 16 chip bonding material, 17 wedge bonding part, 18 sealing resin layer, 19 ball bonding part

Claims (15)

1. A gold-coated bonding wire comprising a core material containing silver or copper as a main component and a coating layer provided on the surface of the core material and containing gold as a main component,
the coating layer of the Jin Beifu bonding wire has a film thickness of 5 to 200nm and a compressive stress of 290 to 590MPa when deformed by 60% relative to the wire diameter.
2. The Jin Beifu binder filament of claim 1, wherein the vickers hardness (Hv) of the core material in cross section is 40 to 80.
3. The Jin Beifu bonding wire according to claim 1 or 2, wherein the core material is formed of a silver alloy containing silver at 97 mass% or more, and contains at least 1 metal selected from copper, calcium, phosphorus, gold, palladium, platinum, nickel, rhodium, indium, and iron in a range of 1 mass ppm to 3 mass% relative to the entire amount of the wire.
4. The Jin Beifu bonding wire according to claim 1 or 2, wherein the core material is formed of a copper alloy containing 98 mass% or more of copper, and contains at least 1 metal selected from phosphorus, gold, palladium, platinum, nickel, silver, rhodium, indium, gallium, and iron in a range of 1 mass ppm to 2 mass% with respect to the entire amount of the wire.
5. The Jin Beifu bonding wire of any of claims 1-4, wherein the Jin Beifu bonding wire has a wire diameter of 13-35 μ ι η.
6. The Jin Beifu bonding wire according to any one of claims 1 to 5, further comprising an intermediate metal layer having 1 metal selected from palladium, platinum, and nickel as a main component, provided between the core material and the coating layer.
7. The Jin Beifu bonding wire of claim 6, wherein the intermediate metal layer has a thickness of 60nm or less.
8. The Jin Beifu bonding wire of any of claims 1-7, for a semiconductor memory.
9. A method for producing a gold-coated bonding wire, which comprises a core material containing silver or copper as a main component and a Jin Beifu bonding wire provided on the surface of the core material and containing a coating layer containing gold as a main component,
wherein the Jin Beifu bonding wire has a film thickness of 5nm to 200nm and a compressive stress of 290MPa to 590MPa.
10. A semiconductor wirebond structure comprising:
jin Beifu bonding wire comprising a core material containing silver or copper as a main component and a coating layer containing gold as a main component;
an electrode of the semiconductor chip; and
a wedge-shaped junction joining the wire and the electrode;
the coating layer of Jin Beifu a bonding wire has a film thickness of 5nm to 200nm and a compressive stress of 290MPa to 590MPa when deformed by 60% with respect to the wire diameter.
11. The semiconductor wirebond structure of claim 10, having 2 or more of the semiconductor chips and 2 or more of the wedge-shaped bonds connecting electrodes of the 2 semiconductor chips and the wire in sequence.
12. A semiconductor wire bond structure according to claim 9 or 10 for a semiconductor memory device.
13. A semiconductor device includes:
1 or more semiconductor chips having at least 1 first electrode;
a circuit base material selected from a lead frame and a circuit substrate having at least 1 second electrode;
bonding wires to Jin Beifu selected from at least 1 electrical connection between the first electrode of the semiconductor chip and the second electrode of the circuit substrate, and between the first electrodes of the plurality of semiconductor chips; and
a wedge-shaped bonding portion to which the first electrode or the second electrode and the Jin Beifu bonding wire are bonded;
the Jin Beifu bonding wire comprises a core material containing silver or copper as a main component and a coating layer provided on a surface of the core material and having a film thickness of 5nm to 200nm and containing gold as a main component,
the compressive stress at 60% deformation of the Jin Beifu bonding wire in the wire diameter is 290-590 MPa.
14. The semiconductor device according to claim 13, which is provided with a plurality of the semiconductor chips each having at least 1 of the first electrodes,
stacking the plurality of semiconductor chips so that the first electrode is exposed,
the semiconductor device includes 2 or more wedge-shaped bonding portions in which the first electrodes of the plurality of semiconductor chips are connected in sequence by the Jin Beifu bonding wires.
15. The semiconductor device according to claim 13 or 14, which is for a semiconductor memory.
CN202080099629.XA 2020-04-10 2020-05-19 Jin Beifu bonding wire, method for manufacturing the same, semiconductor wire bonding structure, and semiconductor device Pending CN115398607A (en)

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