CN115395793B - Switching power supply circuit - Google Patents

Switching power supply circuit Download PDF

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Publication number
CN115395793B
CN115395793B CN202211321991.4A CN202211321991A CN115395793B CN 115395793 B CN115395793 B CN 115395793B CN 202211321991 A CN202211321991 A CN 202211321991A CN 115395793 B CN115395793 B CN 115395793B
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current
voltage
power supply
switching
sampling
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CN115395793A (en
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李科举
麻胜恒
朱警怡
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Zhongke Shenzhen Wireless Semiconductor Co ltd
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Zhongke Shenzhen Wireless Semiconductor Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/348—Passive dissipative snubbers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a switching power supply circuit, and relates to the technical field of power supplies. The power supply control circuit comprises an input module, a switch control module, a transformer and an output module which are connected in sequence, wherein the switch control module comprises an absorption circuit, a control chip, a switch triode and a chip power supply energy storage capacitor; when the switching triode is conducted, the control chip can obtain current from the switching triode to realize self-power supply; the control chip can also obtain the voltage difference between two ends of the primary winding of the transformer through primary side sampling. The invention utilizes the characteristic that the switching triode has base storage effect to realize self power supply and adds a primary side sampling circuit; compared with the prior art, the ACDC adapter has the advantages that the control chip is removed, the resistors, the diodes and the transformer winding are reduced, the integration level of the primary side feedback ACDC adapter is improved, and the size of the adapter is reduced.

Description

Switching power supply circuit
Technical Field
The invention relates to the technical field of ACDC switching power supplies, in particular to a switching power supply circuit.
Background
The flyback ACDC structure has the advantages of simple control and easy regulation of output voltage, and is widely applied to occasions of power adapters with medium and small power. The flyback ACDC structure has two output feedback control modes of primary side feedback (PSR) and secondary side feedback (SSR). And a primary side feedback (PSR) ACDC can save an optical coupler and a controllable voltage stabilizing source TL431 device, has the advantages of simple structure and high cost performance, and is widely applied to occasions of low-power ACDC power supplies.
As shown in fig. 1, the system circuit structure of the primary side feedback (PSR) ACDC remains stable and unchanged for many years without much innovation. The system transformer T1 is provided with 3 transformer windings, wherein Lp is a primary winding, energy is stored when a switch is opened, ls is a secondary winding, the stored energy in the transformer is output when the switch is closed, L3 is an auxiliary winding and is responsible for supplying power to a chip and feeding back output voltage information, and after the switch is closed, voltage signals output by Ls and L3 are proportional to a turn ratio, so that a voltage signal of the Ls winding can be obtained by sampling a voltage signal of the L3 winding, the voltage signal of the Ls winding is equal to the output voltage plus the voltage drop of a rectifier diode D1, so that the voltage signal of the L3 can reflect the size of the output voltage, and the L3 winding is connected to the common ground of the primary side and is a high-voltage signal relative to the ground, so that the primary side feedback is called. The diode D7 is a rectifier diode, and because the output voltage of the auxiliary winding is a switching waveform, it needs to be shaped to obtain a dc voltage to supply power to the chip. The resistor Rd is a current-limiting resistor, the resistors R03 and R04 are auxiliary winding voltage dividing resistors, and the divided voltage value is input to a voltage sampling end FB of a primary side feedback (PSR) chip. The resistors R1 and R2 are starting resistors and are responsible for supplying power to a primary side feedback (PSR) chip VCC before the primary side feedback (PSR) chip and the system work. The resistors R5 and R6 are current sampling resistors, collect the current flowing through the primary stage Lp of the transformer, convert the current into a voltage signal and send the voltage signal to a primary side feedback (PSR) chip CS end.
Fig. 2 is a circuit block diagram of a conventional primary side feedback (PSR) chip. The feedback voltage sampling and holding module samples and holds the voltage of the FB, and then the FB is sent to the constant voltage control module, and meanwhile, an FB signal is sent to the constant current control module. And the outputs of the constant voltage control module and the constant current control module are sent to the S end of the RS trigger together, and the outputs of the constant voltage control module and the constant current control module control the opening of the switching signal PWM together. And the voltage of the CS is sent to a peak current control module, an output signal of the peak current control module is sent to an R end of an RS trigger, and the PWM of the switch chip is reset. The switching signal PWM controls the switching of the external power tube Q0 through the base current driving signal output by the driving circuit module.
The conventional system circuit of the primary side feedback ACDC is complex in circuit, and the integration level can be further improved.
Disclosure of Invention
In order to improve the integration level of the primary side feedback ACDC adapter, simplify a system circuit and reduce the size of the adapter, the invention provides a novel switching power supply circuit.
In order to alleviate the above problems, the technical scheme adopted by the invention is as follows:
a switching power supply circuit comprises an input module, a switching control module, a transformer and an output module which are sequentially connected, wherein the switching control module comprises an absorption circuit, a control chip, a switching triode and a chip power supply energy storage capacitor; when the switching triode is conducted, the control chip can obtain current from the switching triode to realize self-power supply; the control chip is provided with two primary side sampling ends, wherein one primary side sampling end is connected with the first end of the primary winding through a first detection resistance module, and the other primary side sampling end is connected with the second end of the primary winding through a second detection resistance module; the positive electrode of the chip power supply energy storage capacitor is connected with only the VDD pin of the control chip.
In a preferred embodiment of the present invention, a diode is disposed in a forward direction at a connection portion between the base pin of the control chip and the driving circuit, so as to achieve self-power.
In a preferred embodiment of the present invention, the first detection resistor module has and only includes one resistor, or includes more than two resistors connected in series.
In a preferred embodiment of the present invention, the second detection resistor module has and only includes one resistor, or includes more than two resistors connected in series.
In a preferred embodiment of the present invention, the control chip includes a primary sampling circuit, the primary sampling circuit includes a voltage signal VFB output terminal and two primary sampling terminals, the voltage vp of the first terminal and the voltage vc of the second terminal of the primary winding can be respectively detected by the two primary sampling terminals, and the voltage signal VFB proportional to the voltage difference between the two terminals of the primary winding can be output to the FB terminal of the primary feedback control circuit by the voltage signal VFB output terminal.
In a preferred embodiment of the present invention, the primary sampling circuit includes a first current mirror, a second current mirror, a current subtractor, an I/V converter, and a buffer; the first current mirror is used for converting the voltage vp into a first current; the second current mirror is used for converting the voltage vc into a second current; the current subtracter is used for subtracting the initial calibration current after the subtraction operation is carried out on the first current and the second current to obtain a primary voltage sampling current; the I/V converter is used for converting the primary voltage sampling current into primary voltage sampling voltage, and the primary voltage sampling voltage is processed by the buffer and then output to obtain a voltage signal VFB proportional to the voltage difference between the two ends of the primary winding.
In a preferred embodiment of the present invention, the primary side sampling current is calculated by the formula
Iso=n*Vs/R 34
Wherein R is 34 The resistance value of the second detection resistance module is n, the primary and secondary turns ratio of the transformer is n, and Vs is the output voltage of the secondary side of the transformer when the switching triode is closed.
In a preferred embodiment of the present invention, the control chip includes a CS current sampling circuit, the CS current sampling circuit includes a voltage signal VCS output terminal and a CS current input terminal, the CS current input terminal is configured to collect a current of the switching transistor, and the CS current sampling circuit is configured to obtain a VCS voltage proportional to the current of the switching transistor according to the current of the switching transistor, and send the VCS voltage to the CS terminal of the primary side feedback control circuit.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the VCC power supply voltage is obtained without rectifying the flyback voltage of the auxiliary winding when the switch is turned off, but self-power supply is realized by utilizing the base storage effect characteristic of the switch triode; a primary side sampling circuit is added, and output voltage sampling is realized by matching two primary side sampling ends with a detection resistance module; compared with the prior art, the invention reduces 3 resistors, one diode and one transformer winding, further improves the integration level of the primary side feedback ACDC adapter, simplifies the system circuit and reduces the volume of the power adapter.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a prior art switching power supply circuit;
FIG. 2 is a circuit block diagram of a prior art control chip;
FIG. 3 is a schematic diagram of the switching power supply circuit of the present invention;
FIG. 4 is a block circuit diagram of the control chip of the present invention;
FIG. 5 is a schematic diagram of a primary side sampling circuit of the present invention;
FIG. 6 is a diagram of an example of a primary side sampling circuit of the present invention;
FIG. 7 is a driving circuit diagram of the present invention;
FIG. 8 is a waveform diagram of the pulse, pg1 and Ng2 nodes of FIG. 7;
fig. 9 is a circuit diagram of the CS current sampling of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 3, the invention discloses a switching power supply circuit, which comprises an input module, a switching control module, a transformer T1 and an output module, which are connected in sequence, wherein the switching control module comprises an absorption circuit, a control chip U21, a switching triode Q0 and a chip power supply energy storage capacitor C1.
The input module is composed of diodes D1-D4 and a capacitor C0, and the output module is composed of a diode D6, a capacitor Cout and a resistor Rd 1.
The transformer T1 has and only includes a primary winding Lp and a secondary winding Ls.
The absorption circuit is connected in parallel with the primary winding Lp of the transformer T1, consists of a diode D0, resistors R7 and R8 and a capacitor C2 and is used for absorbing a voltage peak generated by flyback of the primary winding Lp.
The anode of the chip power supply energy storage capacitor C1 is connected with only the VDD pin of the control chip U21.
And a base pin of the control chip U21 is connected to the base electrode of the switching triode Q0 to control the switching of the switching triode Q0.
When the switching triode Q0 is turned on, the current of the primary winding Lp of the transformer T1 is increased, the current flows into the CS pin of the control chip U21 through the switching triode Q0, and the transformer T1 stores energy.
When the control chip U21 detects that the current flowing into the CS pin reaches a set value, the base outputs a low level to close the switching triode Q0. The primary winding Lp and the secondary winding Ls of the transformer T1 are both flyback to high level voltages.
The secondary winding Ls flyback high level voltage to conduct the diode D6, the stored energy of the transformer T1 charges the capacitor Cout through the secondary winding Ls and the diode D6, and the output voltage Vout rises. The voltage Vs of the synchronous secondary winding Ls also rises, and the voltage Vc of the second terminal of the primary winding Lp also rises, as is known from transformer principles.
In the invention, when the switching transistor Q0 is conducted, the control chip U21 can obtain current from the switching transistor Q0 to realize self-power supply. The control chip U21 Is provided with two primary side sampling ends Ip and Is.
When the switching triode Q0 is turned off, a voltage is also flyback-excited on the primary winding Lp of the transformer T1, and the transformer characteristics know that the voltage signal is the same as the voltage signal of the auxiliary winding in fig. 1 and is also related to the output voltage and the turn ratio, so that the output voltage information is obtained by sampling the voltage difference on the primary winding Lp when the switching triode Q0 is turned off, and the primary side feedback control function is realized.
However, the voltages at the two ends of the primary winding Lp are very high, so that the voltages at the two ends of the primary winding Lp need to be converted into currents respectively, and then the currents are subtracted and added to the internal resistor to be converted back into voltage signals, so that the voltage difference at the two ends of the transformer T1 can be obtained, and primary sampling of the output voltage is realized.
One primary side sampling end Ip of the control chip U21 Is connected with the first end of the primary winding through a first detection resistance module, and the other primary side sampling end Is connected with the second end of the primary winding through a second detection resistance module. In an alternative embodiment of the invention, the first detection resistance module comprises resistors R1, R2 connected in series, and the second detection resistance module comprises resistors R3, R4 connected in series. The control chip U21 detects the voltage difference between the two ends of the primary winding Lp through the resistors R1, R2, R3 and R4 to judge the magnitude of the output level, and further controls the output voltage to be constant.
In a low-power primary side feedback power supply (Pout < = 12W), a power triode is generally adopted, and the triode has a base storage effect characteristic, namely, after the triode is driven, the triode can be kept conducting for a period of time even if base current is not added. Therefore, in the present invention, this characteristic is used to realize self-power supply of the control chip U21 when the switching transistor Q0 is turned on.
Fig. 4 is a block circuit diagram of the control chip U21 according to the present invention.
The control chip U21 comprises a primary side feedback control circuit, a driving circuit, a primary side sampling circuit and a CS current sampling circuit.
The primary side sampling circuit detects the Ip and Is signals and generates a voltage signal VFB output proportional to the voltage difference between two ends of the primary winding Lp.
The current sampling signal CS voltage is input to the CS current sampling circuit, and the VCS voltage amplified in equal proportion is output.
The primary side feedback (PSR) control circuit has the same structure as the original primary side feedback (PSR) control circuit shown in fig. 2. The sampling voltage signal VFB is used for constant voltage and constant current control, and the sampling VCS signal is used for realizing peak current control. In the present invention, as shown in fig. 4, the driving circuit module is adjusted to combine the driving module with the self-powered module, and as shown in fig. 7, a diode D70 is added to the base pin driving circuit of the control chip U21 to prevent the base pin from being clamped by VDD, so that when the fet NM72 in fig. 7 is turned off, the voltage at the base pin can be increased to maintain the conduction of the transistor Q0.
Fig. 5 shows an implementation of the primary sampling circuit for the output voltage.
It Is known from fig. 3 that the input terminal Vp of the primary winding Lp Is connected to the Ip terminal of the control chip U21 through resistors R1 and R2, and the other terminal of the primary winding Lp Is connected to the Is terminal of the control chip U21 through resistors R3 and R4. The reason why the detection resistor module adopts the resistors connected in series is that two resistors are used for balancing power consumption, reliability is improved, and if the power of the resistors is enough, 1 resistor can be adopted.
The Ip and Is ports realize the input V/I conversion through current mirrors U51 and U52. At the same time, the current mirror at the Ip and Is ends clamps the voltage to a constant voltage Vt, so that the input current of Ip Is (Vp-Vt)/(R1 + R2), the input current of Is (Vc-Vt)/(R3 + R4), and the Vt value Is smaller relative to the voltages of Vp and Vc, so that Ip Is approximately equal to Vp/(R1 + R2) and Is approximately equal to Vc/(R3 + R4). And Vc = Vp + n × Vs, where n is the transformer primary-secondary turn ratio, vs is the output voltage of the secondary winding Ls when the switch is closed, and Vs = Vout + Vd. The control chip U21 performs a calibration operation before the power-on switch is operated, and then retains the calibration value I0= Vp/(R3 + R4) -Vp/(R1 + R2). In normal operation, the current subtracter U53 subtracts the Ip and the Is and then subtracts the initial calibration value I0, so as to obtain a current signal Iso sampled on the primary side of the output voltage, wherein the current formula Is as follows.
Id=（Vp+n*Vs）/(R3+R4)-Vp/(R1+R2)=I0+n*Vs/(R3+R4)
Iso=Id-I0=n*Vs/(R3+R4)
The current signal Iso is passed through the I/V converter U54 to obtain a sampled voltage signal, and then passed through the buffer U55 to output VFB to the feedback voltage sample-and-hold circuit in the primary feedback control circuit.
Fig. 6 shows an embodiment of the output voltage primary side sampling circuit.
The field effect transistors NM10, NM21, NM22, NM1, and NM2 form a current mirror U52 in fig. 5;
the field effect transistors NM11, NM13, NM14, NM3, NM4, PM13, PM14, PM3, PM4 constitute a current mirror U51 in fig. 5;
nodes a and VFB0 are equivalent to current subtractor U53 in fig. 5;
the resistor Rs is equivalent to the I/V converter U54 in FIG. 5;
the field-effect transistors NM15, NM16, NM17, NM18, NM19, NM5, NM6, NM7, NM8, NM9, NM12, NM25, NM26, NM27, PM5, PM6, PM7, PM8, PM15, PM16, PM17, PM18, PM25, PM26, PM27, PM12, the comparator U62, the and gate U63, and the enable addition and subtraction circuit U64 constitute the converter U56 in fig. 5.
The signals Is and Ip are converted into current signals Is2 and Ip1 through a current mirror formed by field effect tubes NM1 and NM2, NM3 and NM4, ip1 outputs Ip2 current through the current mirror formed by field effect tubes PM4 and PM3, the Ip2 current and the Is2 current are connected to an A node to be subjected to current subtraction to obtain Isp current, and then the Isp2 current Is obtained through a current mirror formed by the field effect tubes PM1 and PM2, wherein Isp2/Isp = n, and n Is an amplification and reduction coefficient during current mirror image. The Isp2 current and the calibration current I0 are superposed to obtain an Iso current, the Iso current is added to the resistor Rs to obtain a VFB0 reference voltage, and the VFB0 reference voltage is output through a U55 buffer to be sent to a reference voltage sampling circuit at the later stage. Therefore, accurate reference voltage sampling can be realized by adding external resistors R1, R2, R3 and R4 through pins Ip and Is.
The calibration current I0 Is the deviation of the Ip current and the Is current recorded before the control chip U21 Is operated, and the system has no current before the control chip U21 Is operated, i.e., vp = Vc, so that the internal sampling voltage VFB0 Is initialized to 0. The method comprises the following steps:
after power-on is completed, the internal circuit of the control chip U21 starts to work, but no switch is output at this time, vp = Vc and Init _ EN =1 are guaranteed, then the comparator U62 compares VFB0 with ground, if VFB0>0, out1 outputs a high level, and after being enabled by the and gate U63, out2 outputs a high level, which enables the pin cinittn of the add-subtract circuit U64 to be set to 1 and Cinit0-Cinit (n-1) to be set to 0, and enables the add-subtract circuit U64 to be added. At this time, the field effect transistor NM12 is turned on, the field effect transistor PM12 is turned off, the calibration current I0 flows OUT from the VFB0 node, and the I0 current gradually increases through the increment of Cinit0-Cinit (n-1), and when the I0 current is equal to the initial value of Isp, VFB0=0, the comparator U62 is inverted, and the OUT1 inverted level is sent to the latch pin LA of the enable addition and subtraction circuit U64, and the current value is latched, so that the initial calibration value I0 is obtained. Similarly, when the initial value of the node voltage VFB0 is 0, the comparator U62 outputs a low level, which sets cinittn, pins Cinit0 and Cinit0-Cinit (n-1) of the enable addition and subtraction circuit U64 to 1, and simultaneously enables the addition and subtraction circuit U64 to perform subtraction. At this time, the fet NM12 is turned off, the fet PM12 is turned on, the calibration current I0 flows OUT from the VFB0 node, and the current I0 gradually increases as Cinit0-Cinit (n-1) decreases, and when the current I0 is equal to the initial value of Isp, VFB0> =0, the U62 comparator is inverted, and the OUT1 inversion level is sent to the latch pin LA of the enable add-subtract circuit U64, and the current value is latched, so that the initial calibration value I0 current is obtained.
As shown in fig. 7, a scheme for realizing self-power supply for the control chip U21 is shown. Fig. 8 is a waveform diagram of the pulse, pg1 and Ng2 nodes in fig. 7. When PWM _ on =1, the field effect transistor PM72 is turned on through the inverter U74, the field effect transistor NM71 is turned off, and the I1 reference current is obtained through a current mirror formed by the field effect transistor PM73 and the PM74, and the Ibc current flows to a Base pin to drive the power triode Q0 to be turned on. The excess Ibc now drives current, causing Q0 to generate a base stored charge. R71, R72 and I72 sample VDD, where VDD _ s = (VDD-I72 × R71) × R72/(R71 + R72), I72 may increase the sampling gain of VDD variation. The VDD _ s is compared with a sawtooth wave to obtain the PWM signal pulse, so that when the VDD voltage is high, the low level time of the pulse signal is short, and when the VDD voltage is low, the low level time of the pulse signal is long. The pulse signal passes through two clock distribution control fets PM71 and NM72 of U72 that do not overlap with the enabled input U73. So that when the pulse signal is low, the fet NM72 is turned off and the fet PM71 is turned on. After the field effect transistor NM72 is turned off, the voltage of the CS node rises, the current of the Q0 flows to the energy storage capacitor C1 of the VDD through the PM71, and at this time, the voltage of the e pole (CS) of the transistor Q0 is higher than the VDD, but due to the base storage effect of the transistor Q0, the voltage of the b pole also increases, the transistor Q0 is still in a conducting state, and the low level time of the pulse is the VDD charging time. Because the base of the triode has a limited storage time (2-5 uS), the pulse becomes low and has a limited time to charge VDD, and the triode Q0 needs to be turned on again after a set time. After the pulse signal goes high, the field effect transistor NM72 is turned on, the PM71 is turned off, the CS voltage goes low, and the Ibc current continues to provide the base driving current for the transistor Q0. Since the entire on time of the transistor Q0 is maintained for a long time (3 uS to 10 uS), the process of turning on the transistor Q0 can be divided into a plurality of VDD charging times. Compared with the patent 201810601234.X, the method disclosed by the invention has the characteristics of long VDD charging time and stable VDD voltage, and the energy storage capacitor of the VDD can be a capacitor with a smaller capacitance value only at the last stage of the turn-off of the PWM.
As shown in fig. 7, the field effect transistor NM72 is a switching transistor in a chip, when the power transistor Q0 is turned on and the field effect transistor NM72 is turned on, a current flows to the field effect transistor NM72 through the transistor Q0, a voltage drop exists on the NM72, the larger the current is, the higher the voltage of the CS node is, and the CS current sampling circuit is used for collecting the current of the transistor Q0 to realize peak current control.
Fig. 9 shows an embodiment of the CS current sampling circuit according to the present invention.
In fig. 9, the fet NM91 is a sampling tube, the current Ics _ s of the fet NM94 is applied to the NM1 tube, and the fet NM94 is controlled such that the voltage drop generated when the current Ics _ s is applied to the fet NM91 is equal to the CS node voltage by comparing the voltages of the fets NM93 and NM 95. Therefore, ics _ Q0 × Rds _ NM72= Ics _ s _ Rds _ NM91, where Ics _ Q0 current is a current flowing through the transistor Q0, ics _ s current is a current flowing through the fet NM94, rds _ NM72 is the on-resistance of NM72, and Rds _ NM91 is the on-resistance of the fet NM91, so Ics _ s current is proportional to Ics _ Q0 current. Ics _ s is mirrored across resistor R91 by fet PM94 and PM95 to obtain a VCS voltage proportional to the Q0 current. This implements the CS current sampling function.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A switching power supply circuit comprises an input module, a switching control module, a transformer and an output module which are sequentially connected, wherein the switching control module comprises an absorption circuit, a control chip, a switching triode and a chip power supply energy storage capacitor; when the switching triode is conducted, the control chip can obtain current from the switching triode to realize self-power supply; the control chip is provided with two primary side sampling ends, wherein one primary side sampling end is connected with the first end of the primary winding through a first detection resistance module, and the other primary side sampling end is connected with the second end of the primary winding through a second detection resistance module; the positive electrode of the chip power supply energy storage capacitor is connected with only the VDD pin of the control chip;
the drive circuit includes: an inverter U74, a diode D70, resistors R71, R72, current sources I71, I72, a comparator U71, an and logic gate U72, and field effect transistors PM72, NM71, NM73, PM74, PM71, and NM72;
the diode D70 is used for preventing the base pin of the control chip from being clamped by VDD, that is, when the fet NM72 is turned off, the voltage of the base pin can be increased;
the inverter U74 is used for controlling the field effect transistors PM72 and NM71 according to the switch control signal PWM _ on;
the current source I71 is used for generating a reference current and sending the reference current to a current mirror consisting of field effect transistors PM73 and PM74 through a field effect transistor NM 73;
a current mirror composed of field effect transistors PM73 and PM74 is used for processing the reference current, and after the current Ibc is obtained, a base pin is input to drive a switch triode to be turned on;
the resistor R71, the resistor R72 and the current source I72 are used for sampling VDD to obtain VDD _ s;
the comparator U71 is used for comparing VDD _ s with a sawtooth wave SAW and obtaining a PWM signal pulse;
the AND logic gate U72 is used for logically AND-ing the PWM signal pulse and the switch control signal PWM _ on to obtain a psw signal;
generating two non-overlapped clock distribution signals Pg1 and Ng2 by using the psw signal, and respectively controlling the field effect transistors PM71 and NM72;
after the field effect transistor NM72 is turned off, the current of the switching triode flows to the chip power supply energy storage capacitor through the field effect transistor PM71 to realize energy storage, i.e. self-power supply.
2. The switching power supply circuit according to claim 1, wherein the first detection resistance module has and only includes one resistance.
3. The switching power supply circuit according to claim 1, wherein the first detection resistance module comprises two or more resistors connected in series.
4. The switching power supply circuit according to claim 1, wherein the second detection resistance module has and only includes one resistance.
5. The switching power supply circuit according to claim 1, wherein the second detection resistance module includes two or more resistors connected in series.
6. The switching power supply circuit according to claim 1, wherein the control chip comprises a primary side sampling circuit, the primary side sampling circuit comprises a voltage signal VFB output terminal and two primary side sampling terminals, the voltage vp at the first terminal and the voltage vc at the second terminal of the primary winding can be respectively detected by the two primary side sampling terminals, and the voltage signal VFB proportional to the voltage difference across the primary winding can be output to the FB terminal of the primary side feedback control circuit by the voltage signal VFB output terminal.
7. The switching power supply circuit according to claim 6, wherein the primary side sampling circuit comprises a first current mirror, a second current mirror, a current subtracter, an I/V converter and a buffer; the first current mirror is used for converting the voltage vp into a first current; the second current mirror is used for converting the voltage vc into a second current; the current subtracter is used for subtracting the initial calibration current after the subtraction operation is carried out on the first current and the second current to obtain a primary voltage sampling current; the I/V converter is used for converting the primary voltage sampling current into primary voltage sampling voltage, and the primary voltage sampling voltage is processed by the buffer and then output to obtain a voltage signal VFB proportional to the voltage difference between the two ends of the primary winding.
8. The switching power supply circuit according to claim 7, wherein the primary side sampling current is calculated by the formula
Iso=n*Vs/R 34
Wherein R is 34 The resistance value of the second detection resistance module is n, the primary and secondary turns ratio of the transformer is n, and Vs is the output voltage of the secondary side of the transformer when the switching triode is closed.
9. The switching power supply circuit according to claim 8, wherein the control chip comprises a CS current sampling circuit, the CS current sampling circuit comprises a voltage signal VCS output terminal and a CS current input terminal, the CS current input terminal is configured to collect a current of the switching transistor, and the CS current sampling circuit is configured to obtain a VCS voltage proportional to the current of the switching transistor according to the current of the switching transistor, and send the VCS voltage to the CS terminal of the primary feedback control circuit.
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US8698474B2 (en) * 2010-06-11 2014-04-15 System General Corp. Start-up circuit with low standby power loss for power converters
US9318965B2 (en) * 2012-10-10 2016-04-19 Flextronics Ap, Llc Method to control a minimum pulsewidth in a switch mode power supply
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