CN115371857A - Pressure sensor chip and processing method thereof - Google Patents

Abstract

The application relates to a pressure sensor chip and a processing method thereof, wherein the processing method comprises the following steps: preparing a device layer of the pressure sensor by using an SOI (silicon on insulator) silicon wafer; preparing a device supporting layer by using a common silicon wafer, and forming vertical metal interconnection holes in the device supporting layer; bonding the device layer and the device support layer; and guiding the metal lead of the device layer to the lower surface of the device supporting layer through the vertical metal interconnection hole by a TSV process. In the whole processing process, the metal wire bonding and TSV process is adopted, oil filling encapsulation is not needed, and the pressure sensor chip can be processed and manufactured simply and conveniently.

Description

Pressure sensor chip and processing method thereof

Technical Field

The application relates to the technical field of chip processing, in particular to a pressure sensor chip and a processing method thereof.

Background

A pressure sensor is a sensor that converts a pressure signal into an electrical signal, and is widely used in various fields and industries.

An MEMS (Micro-Electro-Mechanical System) pressure sensor is a novel pressure sensor, which is suitable for severe environments such as high impact, high overload, electric conduction, corrosion, radiation, etc., and is widely used in the fields of aerospace, military, industry, etc.

In a traditional MEMS pressure sensor chip packaged by lead bonding (gold wire bonding), an oil filling technology is usually adopted for protecting a gold wire from corrosion, but when the environmental temperature changes severely, the pressure sensor is subjected to large errors caused by expansion of silicon oil, and the problems of large volume, low overload resistance, complex later-stage packaging and the like exist. Therefore, a new pressure sensor chip processing scheme is urgently needed to avoid the problem of complex packaging.

Disclosure of Invention

In view of the above, it is desirable to provide a method for processing a pressure sensor chip that is easy to produce and a pressure sensor chip processed by the method.

A method of pressure sensor chip processing, the method comprising:

preparing a device layer of the pressure sensor by adopting an SOI (Silicon-On-Insulator) Silicon wafer;

preparing a device supporting layer by adopting a common silicon wafer;

bonding the device layer and the device support layer;

and guiding the metal lead of the device layer to the lower surface of the device supporting layer Through a Through-Silicon-Via (TSV) process, wherein the lower surface is the surface far away from one side of the device layer.

In one embodiment, the device layer for manufacturing the pressure sensor by using the SOI silicon wafer comprises:

preparing an SOI silicon wafer comprising a substrate, an oxygen-buried layer and a monocrystalline silicon layer;

respectively preparing a piezoresistor and an ohmic contact lead on the lower surface of the monocrystalline silicon layer;

manufacturing a metal lead on the lower surface of the monocrystalline silicon layer;

and connecting the metal lead with the lead of the ohmic contact, wherein the lower surface is the surface far away from one side of the buried oxide layer.

In one embodiment, after the preparing of the piezoresistor and the lead of the ohmic contact on the lower surface of the monocrystalline silicon layer respectively, the method further comprises:

depositing the buried oxide layer to form an insulating layer;

after the metal lead is connected with the lead of the ohmic contact, the method further comprises the following steps:

depositing an oxide layer on the upper surface of the monocrystalline silicon layer again; and flattening the upper surface of the monocrystalline silicon layer.

In one embodiment, the bonding the device layer and the device supporting layer comprises:

and bonding the device layer and the device supporting layer by adopting a silicon-silicon bonding process or a metal bonding process.

In one embodiment, before bonding the device layer and the device supporting layer, the method further includes:

and forming a vertical metal interconnection hole which is not conducted on the device supporting layer by adopting DRIE etching.

In one embodiment, the guiding the metal leads of the device layer to the lower surface of the device support layer through the TSV process includes:

grinding and removing the substrate of the device layer by adopting a mechanical grinding method;

removing the buried oxide layer by etching to expose the single crystal silicon layer;

conducting openings of vertical metal interconnection holes in the device supporting layer;

and filling a passivation layer and a metal conductive material in the conducted vertical metal interconnection hole so that the metal lead is guided to the lower surface of the device supporting layer through the metal conductive material.

In one embodiment, the guiding the metal leads of the device layer to the lower surface of the device support layer through the TSV process includes:

mechanically grinding one side of the substrate in the bonded SOI silicon wafer, and thinning the bonded SOI silicon wafer to a preset thickness;

conducting the non-conducted vertical metal interconnection hole openings in the device supporting layer;

filling a passivation layer and a metal conductive material in the vertical metal interconnection hole so that the metal lead is guided to the lower surface of the device supporting layer through the metal conductive material:

and etching the insulating layer and the substrate in the SOI silicon wafer to form a groove or a cross groove so as to expose the monocrystalline silicon layer.

In one embodiment, the aperture of the conducting end of the non-conducting vertical metal interconnection hole is smaller than that of the non-conducting end.

In one embodiment, the pressure sensor chip processing method further includes:

and guiding the metal lead on the lower surface of the device supporting layer to a preset appointed ball planting position and carrying out ball planting operation.

According to the pressure sensor chip processing method, the device layer of the pressure sensor is prepared by adopting the SOI silicon chip; preparing a device supporting layer by using a common silicon wafer, and forming vertical metal interconnection holes in the device supporting layer; bonding the device layer and the device support layer; and guiding the metal leads of the device layer to the lower surface of the device supporting layer through the vertical metal interconnection holes by a TSV process. In the whole processing process, the metal wire bonding and TSV process is adopted, oil filling encapsulation is not needed, and the pressure sensor chip can be processed and manufactured simply and conveniently.

In addition, the application also provides a pressure sensor chip which is processed by the pressure sensor chip processing method.

The pressure sensor chip is processed by the pressure sensor chip processing method, and can be widely applied in a large scale due to simple and convenient production process.

Drawings

FIG. 1 is a schematic flow chart of a method of processing a pressure sensor die according to one embodiment;

FIG. 2 is a schematic diagram of the structure of a device layer in one embodiment;

FIG. 3 is a schematic diagram of the structure of a device layer in another embodiment;

FIG. 4 is a schematic diagram of a post-etch structure of a device support layer in one embodiment;

FIG. 5 is a schematic diagram of the bonded structure of the device layer and the device handle layer in one embodiment;

FIG. 6 is a diagram illustrating the structure after bonding and conducting vertical metal interconnect holes in one embodiment;

FIG. 7 is a schematic diagram of a structure after processing by the TSV process in one embodiment;

FIG. 8 is a schematic diagram of a structure after processing by a TSV process in another embodiment;

fig. 9 is a schematic diagram of a structure after TSV process processing in yet another embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

As shown in fig. 1, the present application provides a method for processing a pressure sensor chip, the method comprising:

s200: and preparing a device layer of the pressure sensor by adopting an SOI silicon chip.

The device layer 100 may specifically include a monocrystalline silicon layer 130, a sensitive element (a varistor 140), a wire, a metal lead, and the like.

Specifically, as shown in fig. 2, the SOI silicon wafer includes a substrate, a buried oxide layer, and a single crystal silicon layer (sensitive film). The thickness of the monocrystalline silicon layer is 3-50 microns, piezoresistors and ohmic contact leads are respectively prepared on the monocrystalline silicon layer, metal leads are manufactured on the monocrystalline silicon layer, and the metal leads are connected with ohmic contact leads.

To further elaborate on the specific structure of the device layer 100, the following description will be made in detail. Specifically, the structure of the device layer 100 is specifically shown in fig. 3, the device layer 100 is prepared by using an SOI silicon wafer, the SOI silicon wafer includes a substrate 110, an oxygen buried layer 120 and a single crystal silicon layer 130, a varistor 140 and a lead 150 in ohmic contact are respectively prepared on the upper surface (the surface far from the substrate 110) of the single crystal silicon layer 130 by using an ion implantation process, then an oxide layer is deposited to form an insulating layer 160, a metal lead is prepared on the upper surface of the single crystal silicon layer 130 by using a sputtering or electroplating method, the metal lead is connected with the lead 150 in ohmic contact, a window is formed on the insulating layer 160 at a position corresponding to the metal lead, a metal conductor is filled in the window and the upper surface of the insulating layer 160, the metal conductor on the upper surface of the insulating layer 160 is removed, the metal conductor remaining in the window is retained to form a metal stop layer 170 (illustrated by two T-shaped structures in fig. 3), wherein the lower end of the metal stop layer 170 is connected with the metal lead, and the oxide layer is deposited again on the upper surface of the insulating layer 160 to form a new insulating layer as a surface insulating layer 180; note that the surface insulating layer 180 is an insulating layer formed again on the metal stopper layer 170, and is an insulating layer different from the insulating layer 160.

S400: and preparing a device supporting layer by adopting a common silicon wafer.

The device support layer 200 is prepared from a common silicon wafer, and the device support layer 200 can be understood as a support member of the entire pressure sensing chip. In particular, recesses and holes may be etched in the device support layer 200 to support achieving further specific functions or effects.

To further elaborate on the structure of the device support layer 200, a detailed description will be provided below. Specifically, as shown in fig. 4, the device supporting layer 200 is subjected to two etching processes on the upper surface of the device supporting layer 200, wherein the first etching process uses a dry etching process or a wet etching process to etch a groove with a depth of 5 to 50 μm at a corresponding position (directly under the wheatstone bridge) of the single crystal silicon layer 130. The second DRIE etch is used to form an opening etch of a specified depth, 100 to 500 microns, without forming a via. Wherein the first recess is used as a vacuum chamber for the pressure sensor and the second DRIE etch is used to form a hole that is subsequently used as a vertical metal interconnect.

S600: and bonding the device layer and the device supporting layer.

Bonding may be understood as combining the device layer 100 and the device handle layer 200. Specifically, the bonding may be achieved using a variety of processes, for example, the device layer 100 and the device support layer 200 may be bonded by a silicon-silicon bonding or metal bonding process. The resulting structure after bonding the device layer 100 shown in fig. 3 and the device supporting layer 200 shown in fig. 4 is shown in fig. 5.

S800: and guiding the metal lead of the device layer to the lower surface of the device supporting layer through the TSV process, wherein the lower surface is the surface far away from one side of the device layer.

TSV refers to a through silicon via technology, which is the latest technology for realizing interconnection between chips by making vertical conduction between chips and between wafers. Different from the traditional IC packaging bonding and the superposition technology using the salient points, the TSV can enable the stacking density of the chips in the three-dimensional direction to be maximum, the outline dimension to be minimum, and the chip speed and the performance of low power consumption to be greatly improved. Here, the metal leads of the device layer 100 are guided to the lower surface of the device support layer 200 through the TSV process, and the metal leads of the device layer 100 are led out, so that the whole process does not need to adopt oil sealing treatment in the conventional technology, and the processing is convenient. The specific processing procedure of the TSV process will be further described in the following embodiments.

In the pressure sensor chip processing method, the device layer 100 of the pressure sensor is prepared by adopting an SOI silicon chip; preparing a device supporting layer 200 by using a common silicon wafer, and forming vertical metal interconnection holes in the device supporting layer 200; bonding the device layer 100 and the device supporting layer 200; the metal leads of the device layer 100 are guided to the lower surface of the device support layer 200 through vertical metal interconnection holes by a TSV process. In the whole processing process, the metal wire bonding and TSV process is adopted, oil filling encapsulation is not needed, and the pressure sensor chip can be processed and manufactured simply and conveniently.

In one embodiment, the device layer of the pressure sensor is prepared by using an SOI silicon wafer and comprises the following components:

preparing an SOI silicon wafer comprising a substrate, an oxygen-buried layer and a monocrystalline silicon layer; respectively preparing a piezoresistor and an ohmic contact lead on the lower surface of the monocrystalline silicon layer; manufacturing a metal lead on the lower surface of the monocrystalline silicon layer; and connecting the metal lead with the lead in ohmic contact, wherein the lower surface is the surface far away from one side of the buried oxide layer.

As shown in fig. 3, the entire device layer 100 includes a substrate 110, a buried oxide layer 120, and a single crystal silicon layer 130, wherein a piezoresistor 140 and an ohmic contact lead 150 are respectively prepared on the surface of the single crystal silicon layer 130 by an ion implantation process, and then a metal lead is formed on the surface of the single crystal silicon layer 130 by a sputtering or electroplating method, and the metal lead is connected to the ohmic contact lead 150. Further, after preparing the piezoresistors 140 and the leads 150 of ohmic contact on the lower surface of the monocrystalline silicon layer 130, respectively, an insulating layer 160 may be formed by depositing silicon oxide, silicon nitride, or the like; after the metal wire is connected to the wire 150 of the ohmic contact, an oxide layer may be deposited again on the surface of the single crystal silicon layer 130 to form a surface insulating layer 180, and the surface insulating layer 180 is an insulating layer correspondingly covering the metal stop layer 170; the SOI surface is planarized, particularly by mechanical grinding, in preparation for the next step of bonding.

In one embodiment, before bonding the device layer and the device supporting layer, the method further includes:

DRIE etching is used in the device support layer to form non-conductive vertical metal interconnect holes.

As shown in fig. 4, after bonding the device layer 100 and the device supporting layer 200, the device supporting layer 200 may be etched, where the etching includes two etches, wherein the first etch uses a dry etch or a wet etch to etch a groove with a depth of 5 to 50 μm at a corresponding position (directly under the wheatstone bridge) of the single crystal silicon layer 130. Specifically, a vacuum cavity with a trapezoidal section is formed through wet etching, and the structure corresponding to the trapezoidal vacuum cavity is shown in fig. 4; a vacuum chamber having a rectangular cross section is formed by dry etching, and the rectangular vacuum chamber corresponds to the structure shown in fig. 5. And the second DRIE etching is used for forming an opening etching with a specific depth of 100-500 microns, and no through hole is formed. Wherein the first etching forms a recess that serves as a vacuum chamber for the pressure sensor and the second DRIE etching forms a hole that serves as a vertical metal interconnect after subsequent conduction. After etching, the device layer 100 and the device support layer 200 are bonded by a silicon-silicon bonding or metal bonding process to seal the piezoresistors 140 within the vacuum chamber. Further, the diameter of the conductive end in the non-conductive vertical metal interconnection hole is smaller than that of the non-conductive end, that is, the non-conductive vertical metal interconnection hole is trapezoidal, the diameter of the opening at the lower end of the trapezoid is smaller than that of the incompletely conductive upper end, where the lower end refers to the end which is in contact with the device layer 100 after being subsequently bonded with the device layer 100, and the upper end refers to the end which is away from the device layer 100 after being subsequently bonded with the device layer 100. When the TSV through hole with the small upper part and the large lower part is formed, the polymer accumulation on the side wall is less, and the side wall is smoother.

In one embodiment, the guiding the metal leads of the device layer to the lower surface of the device support layer through the TSV process comprises:

grinding and removing the substrate of the device layer by adopting a mechanical grinding method; removing the buried oxide layer by etching to expose the single crystal silicon layer; conducting the opening of the vertical metal interconnection hole in the device supporting layer; and filling a passivation layer and a metal conductive material in the conductive vertical metal interconnection hole so that the metal lead is guided to the lower surface of the device supporting layer through the metal conductive material.

This embodiment is an implementation manner of the TSV process. Specifically, a structure obtained after bonding the device layer and the device support layer is shown in fig. 5, and on the basis of the structure shown in fig. 5, a mechanical grinding method is firstly adopted for grinding the substrate of the device layer, that is, the mechanical grinding method directly removes the substrate oxide layer to be directly exposed, and then the buried oxide layer is removed through wet etching or dry etching, so that the whole single crystal silicon layer is exposed. Then, as for the device layer, as shown in fig. 6, on the basis of the structure shown in fig. 5, the non-conductive holes formed by the second etching are conducted to form conductive vertical metal interconnection holes, specifically, the remaining non-conductive portions formed by the second etching are removed from the back surface of the device supporting layer by mechanical grinding and blanket-etching processes to form through holes with a specific depth, which is understood to mean the depth of the holes formed by the second etching. And then etching the part in the through hole, which is in contact with the insulating layer in the device layer, stopping on the metal stop layer, filling a passivation layer in the through hole to insulate the contact side line of the two sides of the through hole and a common silicon wafer, filling a metal conductive material in the through hole, and directly contacting the metal stop layer with the metal conductive material, so as to guide the metal wire to the lower surface of the device supporting layer through the metal wire material, wherein the lower surface is the surface on one side of the device supporting layer, and the specific obtained structural diagram is shown in fig. 7. Furthermore, a metal lead wire led out from the lower surface of the device supporting layer (namely the bottom of the pressure sensor chip) can be led to a specified ball mounting position, and the ball mounting operation is carried out through a standard process. And after the process flow is finished, packaging can be completed through one-time reflow soldering.

In one embodiment, the guiding the metal leads of the device layer to the lower surface of the device support layer through the TSV process includes:

mechanically grinding one side of the substrate in the bonded SOI silicon chip, and thinning the bonded SOI silicon chip to a preset thickness; opening of the vertical metal interconnection hole which is not conducted in the device supporting layer is conducted; filling a passivation layer and a metal conductive material in the conducted vertical metal interconnection hole so that the metal lead is guided to the lower surface of the device supporting layer through the metal conductive material; and etching the insulating layer and the substrate in the SOI silicon wafer to form a groove or a cross-shaped groove so as to expose the monocrystalline silicon layer.

The embodiment is another implementation manner of the TSV process. Specifically, a structure obtained after bonding the device layer and the device supporting layer is as shown in fig. 5, and based on the structure shown in fig. 5, the substrate side of the SOI silicon wafer is mechanically ground for the device layer, and the bonded SOI silicon wafer is thinned to a specified thickness, where the specified thickness value may be specifically set according to actual needs, and it is noted that, here, the substrate and the insulating layer need to be retained. Then, as for the device layer, as shown in fig. 6, on the basis of the structure shown in fig. 5, the non-conductive holes are formed by the second etching, and the conductive vertical metal interconnection holes are formed, specifically, the remaining non-conductive portions of the second etching are made clear on the back surface of the device supporting layer by mechanical grinding and blanket-etching processes, so as to form the through holes with a specific depth, which is understood to mean the depth of the holes formed by the second etching. And then etching the part in the through hole, which is in contact with the insulating layer in the device layer, stopping on the metal stop layer, filling a passivation layer in the through hole to insulate the contact side lines of the two sides of the through hole and a common silicon wafer, filling a metal conductive material in the through hole, and directly contacting the metal stop layer with the metal conductive material, so that the metal wire is guided to the lower surface of the device supporting layer through the metal wire material, wherein the lower surface refers to the surface on one side of the device supporting layer, and the specific structural diagram is shown in fig. 7. In addition, the insulating layer and the substrate in the local area on the SOI silicon chip are etched by a dry etching method or a film wet etching method to form a groove or a cross-shaped groove so as to expose the middle single crystal silicon layer. Further, a metal wire led out from the lower surface of the device supporting layer (i.e., the bottom of the pressure sensor chip) may be led to a designated ball mounting position, and a ball mounting operation may be performed through a standard process, where a structure obtained by the method is shown in fig. 8 and 9, where fig. 8 corresponds to a structure in which a groove is formed in the insulating layer and the substrate, and fig. 9 corresponds to a structure in which a cross-shaped groove is formed in the insulating layer and the substrate. And after the process flow is finished, packaging can be finished through one-time reflow soldering.

The TSV process has the technical advantages that: 1. the thickness of the SOI silicon chip is reserved, and the structural strength of the final wafer product is improved. 2. The etching difficulty of the TSV through holes of the substrate layer of the device is reduced. 3. The pressure sensor can be used normally by etching a groove or a cross-shaped groove directly above the Wheatstone bridge to expose the single crystal silicon layer.

In the embodiment of the TSV process, the following technical advantages are provided: 1. the metal vertical interconnection can guide the metal lead of the bonding surface to the lower surface of the device supporting layer; 2. avoiding mechanical grinding debris from drilling into the TSV through holes; 3. when the TSV through hole with the small upper part and the large lower part is formed, polymer accumulation on the side wall is less, and the side wall is smoother; and the filling plating of the subsequent passivation layer and the metal layer is facilitated. The advantages ensure the electrical performance of the metal vertical interconnection between the upper layer wafer and the lower layer wafer.

In addition, in addition to the TSV process in 2, the following method can be adopted: carrying out bosch etching, passivation layer and metal material filling on the lower surface opening of the device supporting layer. After the SOI silicon wafer and the silicon wafer of the structure supporting layer are bonded, the structure supporting layer is ground to a preset thickness through a CMP (Chemical Mechanical Polishing) process, an opening is formed in the lower surface of the device supporting layer, and bosch etching is carried out until over-etching is formed on the metal stopping layer of the SOI silicon wafer. And filling a passivation layer in the through hole, etching the passivation layer at the bottom in the through hole, exposing the metal stop layer, and filling the metal conductive material.

Overall, in the above embodiments of the pressure sensor chip processing method of the present application, the following significant technical effects are achieved:

compared with the traditional preparation process (the piezoresistor is prepared on the upper surface of the monocrystalline silicon layer), the piezoresistor in the pressure sensor chip processing method effectively improves the anti-interference capability of the chip and the adaptability to selection of a harsh environment (compared with the traditional process, extra protective measures such as oil filling protection are usually adopted) because the piezoresistor is prevented from being directly exposed in the detected environment. Compared with the traditional lead bonding process, the chip achieves the effect of metal lead build-in through the TSV process, on one hand, the packaging space occupied by routing is reduced, on the other hand, the lead build-in does not need routing and later-stage oil filling protection, and even the packaging process can be completed through one-time reflow soldering in the later stage, so that the packaging process is greatly simplified. In addition, the chip achieves the purpose of lead built-in arrangement through the TSV process, so that the anti-interference capability of the chip is improved, and the chip has better adaptability to the use environment.

Furthermore, in order to improve the sensitivity of the pressure sensor chip, a mass block is manufactured on the upper surface of the monocrystalline silicon layer of the sensor (the mass block can be placed or not according to actual conditions and requirements); meanwhile, in order to avoid water accumulation or other impurities, a silicon supporting layer is etched above the SOI silicon wafer on which the monocrystalline silicon layer is positioned to manufacture a cross-shaped opening (a plurality of bosses are formed) so as to lead out the water accumulation possibly existing and improve the rigidity of the whole chip.

In addition, the application also provides a pressure sensor chip obtained by processing the pressure sensor chip processing method. The pressure sensor chip can be obtained by simple and convenient processing by adopting the pressure sensor chip processing method, has low cost and convenient production, and can be popularized and applied in a large scale.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims (10)

1. A method of pressure sensor chip processing, the method comprising:

preparing a device layer of the pressure sensor by using an SOI (silicon on insulator) silicon wafer;

preparing a device supporting layer by adopting a common silicon wafer;

bonding the device layer and the device support layer;

and guiding the metal leads of the device layer to the lower surface of the device supporting layer through a TSV process, wherein the lower surface is the surface far away from one side of the device layer.

2. The processing method according to claim 1, wherein the step of preparing the device layer of the pressure sensor by using the SOI silicon wafer comprises the following steps:

preparing an SOI silicon wafer comprising a substrate, an oxygen-buried layer and a monocrystalline silicon layer;

respectively preparing a piezoresistor and an ohmic contact lead on the lower surface of the monocrystalline silicon layer;

manufacturing a metal lead on the lower surface of the monocrystalline silicon layer;

and connecting the metal lead with the lead of the ohmic contact, wherein the lower surface is the surface far away from one side of the buried oxide layer.

3. The processing method according to claim 2,

after the piezoresistor and the lead wire of the ohmic contact are respectively prepared on the lower surface of the monocrystalline silicon layer, the method further comprises the following steps:

depositing the buried oxide layer to form an insulating layer;

after the metal lead is connected with the lead of the ohmic contact, the method further comprises the following steps:

depositing an oxide layer on the upper surface of the monocrystalline silicon layer again;

and flattening the upper surface of the monocrystalline silicon layer.

4. The process of claim 1, wherein said bonding said device layer and said device support layer comprises:

and bonding the device layer and the device supporting layer by adopting a silicon-silicon bonding process or a metal bonding process.

5. The process of claim 2, wherein prior to bonding the device layer and the device support layer, further comprising:

and forming a vertical metal interconnection hole which is not communicated on the device supporting layer by adopting DRIE etching.

6. The processing method according to claim 5, wherein the guiding the metal leads of the device layer to the lower surface of the device support layer by the TSV process comprises:

grinding and removing the substrate of the device layer by adopting a mechanical grinding method;

removing the buried oxide layer by etching to expose the single crystal silicon layer;

conducting openings of vertical metal interconnection holes in the device supporting layer;

and filling a passivation layer and a metal conductive material in the conducted vertical metal interconnection hole so that the metal lead is guided to the lower surface of the device supporting layer through the metal conductive material.

7. The processing method according to claim 5, wherein the guiding the metal leads of the device layer to the lower surface of the device support layer by the TSV process comprises:

mechanically grinding one side of the substrate in the bonded SOI silicon wafer, and thinning the bonded SOI silicon wafer to a preset thickness;

conducting the non-conducted vertical metal interconnection hole openings in the device supporting layer;

filling a passivation layer and a metal conductive material in the conducted vertical metal interconnection hole so that the metal lead is guided to the lower surface of the device supporting layer through the metal conductive material;

and etching the insulating layer and the substrate in the SOI silicon wafer to form a groove or a cross groove so as to expose the monocrystalline silicon layer.

8. The process of claim 5, wherein the diameter of the conductive end of the non-conductive vertical metal interconnection hole is smaller than the diameter of the non-conductive end.

9. The process of claim 6 or 7 or 8, further comprising:

and guiding the metal lead on the lower surface of the device supporting layer to a preset appointed ball planting position and carrying out ball planting operation.

10. A pressure sensor chip, wherein the pressure sensor chip is processed by the pressure sensor chip processing method according to any one of claims 1 to 9.

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