CN115357080A - High-performance LDO circuit based on switch dynamic switching - Google Patents
High-performance LDO circuit based on switch dynamic switching Download PDFInfo
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Abstract
The invention provides a high-performance LDO circuit based on switch dynamic switching, which comprises a voltage comparison unit, a phase inverter, a switch group and a load tube, wherein the inverting input end of the voltage comparison unit is externally connected with a VREF terminal, the non-inverting input end of the voltage comparison unit is externally connected with a voltage output end, the voltage output end is grounded through a first capacitor, the output end of the voltage comparison unit is electrically connected with the phase inverter, the output end of the phase inverter is connected with the switch group, the switch group is electrically connected with the load tube, and the output end of the phase inverter outputs a control signal to control the switch group to be switched so as to enable the load tube to be switched on or switched off, so that the voltage output end outputs voltage to be fed back to a voltage comparison module switching control signal. The invention greatly reduces the overall power consumption of the LDO circuit by the structural design of the switch type LDO circuit, the switching of the voltage comparison switch, the simple circuit structure and no influence of the loop stability.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a high-performance LDO circuit based on dynamic switching of a switch.
Background
The LDO mainly comprises a PMOS, an operational amplifier, a feedback resistor and a reference voltage. The main course of operation of LDO is with output voltage through divider resistance partial pressure, and divider resistance's voltage and benchmark reference voltage difference signal amplification put the output through fortune and adjust output voltage, and this process voltage output has unstable problem, and traditional PMOS fortune is put LDO and is passed through the loop feedback, and the stability problem of loop need be considered to the stable output voltage.
Disclosure of Invention
In view of the above, the present invention provides a high performance LDO circuit based on dynamic switching of switches.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: the utility model provides a high performance LDO circuit based on switch dynamic switching, includes voltage comparison unit, phase inverter, switch group and load tube, voltage comparison unit's inverting input is external to have the VREF terminal, voltage comparison unit's normal phase input is external to have voltage output, voltage output is through first electric capacity ground connection, voltage comparison unit's output with phase inverter electric connection, the output of phase inverter with the switch group links to each other, the switch group with load tube electric connection, the output control signal control switch of phase inverter organizes the switching so that the load tube switches on or shuts off to realize that voltage output voltage feeds back voltage comparison module switching control signal.
In the present invention, preferably, the output end of the inverter includes a low-level control signal terminal and a high-level control signal terminal, the switch group includes a first switch, a second switch, a third switch, a fourth switch and a fifth switch, the second switch and the third switch are all connected to the high-level control signal terminal, and the first switch, the fourth switch and the fifth switch are all connected to the low-level control signal terminal.
In the present invention, preferably, a drain of the load tube is connected to the positive input terminal of the voltage comparing unit through a second capacitor, and the drain of the load tube is grounded through a first resistor, a second resistor, and a third resistor connected in series to each other, a gate of the load tube is externally connected to a gate of a field effect tube, the drain of the field effect tube is grounded through a second switch, a source of the field effect tube is connected to a source of the load tube, the third switch is connected in parallel between the second capacitor and the first resistor, the first switch is connected in parallel between the source of the load tube and the gate of the load tube, the fourth switch is connected in parallel between the second capacitor and the second resistor, and the drain of the load tube is grounded through a fifth switch.
In the present invention, preferably, the voltage comparison unit includes a first MOS transistor to a twenty-first MOS transistor, a source of the first MOS transistor is connected to a source of the second MOS transistor and to a drain of the third MOS transistor, a gate of the first MOS transistor and a gate of the second MOS transistor are connected to a drain of the fifth MOS transistor and a drain of the sixth MOS transistor, respectively, a gate of the third MOS transistor, a gate of the fourth MOS transistor and a gate of the seventh MOS transistor are connected to a drain of the tenth MOS transistor, a gate of the tenth MOS transistor is externally connected to an ENN enable terminal, a drain of the first MOS transistor and a drain of the second MOS transistor are connected to a drain of the twelfth MOS transistor and a drain of the thirteenth MOS transistor, respectively, a gate of the twelfth MOS transistor is connected to a drain of the thirteenth MOS transistor, a gate of the thirteenth MOS transistor is connected to a drain of the twelfth MOS transistor, and the eleventh MOS transistor and the fourteenth MOS transistor are symmetrically connected to two sides of the twelfth MOS transistor and the thirteenth MOS transistor.
In the present invention, preferably, the drain of the twelfth MOS transistor is connected to the drain of the fifteenth MOS transistor and the gate of the seventeenth MOS transistor, the drain of the thirteenth MOS transistor is connected to the drain of the sixteenth MOS transistor and the gate of the eighteenth MOS transistor, the gate of the fifteenth MOS transistor and the gate of the sixteenth MOS transistor are both externally connected to an ENP enable terminal, the drain of the seventeenth MOS transistor is connected to the drain of the nineteenth MOS transistor, the drain of the eighteenth MOS transistor is connected to the drain of the twentieth MOS transistor and serves as an output terminal of the voltage comparison unit, the gate of the nineteenth MOS transistor is connected to the gate of the twentieth MOS transistor and the drain of the twenty-first MOS transistor, and the gate of the twenty-first MOS transistor is externally connected to an ENN enable terminal.
In the present invention, preferably, a VSS terminal is externally connected to a source of the tenth MOS transistor, a source of the seventh MOS transistor, a source of the fourth MOS transistor, a source of the third MOS transistor, a source of the nineteenth MOS transistor, a source of the twentieth MOS transistor, and a source of the twenty-first MOS transistor.
In the invention, preferably, a gate of the fifth MOS transistor and a gate of the sixth MOS transistor are respectively connected to a drain of the ninth MOS transistor and a drain of the eighth MOS transistor, a gate of the eighth MOS transistor is externally connected to a VP terminal, a gate of the ninth MOS transistor is externally connected to a VN terminal, a source of the eighth MOS transistor and a source of the ninth MOS transistor are both connected to a drain of the seventh MOS transistor, and a drain of the eighth MOS transistor, a drain of the ninth MOS transistor, a drain of the fifth MOS transistor and a drain of the sixth MOS transistor are respectively connected to a source of the eleventh MOS transistor through a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor.
In the invention, preferably, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, and the twenty-first MOS transistor are all N-type MOS transistors.
In the present invention, preferably, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, the seventeenth MOS transistor, and the eighteenth MOS transistor are all P-type MOS transistors.
The invention has the advantages and positive effects that: the output attack resistance can be improved, the response speed of the whole LDO is improved by improving the traditional operational amplifier structure of the LDO into a circuit structure with a voltage comparison unit and a switch group matched with each other, so that the transient response of an output load is improved, and the output attack resistance is improved; in addition, the traditional PMOS operational amplifier LDO stabilizes output voltage through loop feedback, and the stability of the loop needs to be considered; the voltage comparison unit and the switch group are matched with each other, the structure is simple, and compared with the traditional LDO circuit structure, the whole power consumption of the LDO circuit is greatly reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is an overall structure diagram of a high performance LDO circuit based on switch dynamic switching according to the present invention;
FIG. 2 is a schematic circuit diagram of a voltage comparison unit of a high performance LDO circuit based on switch dynamic switching according to the present invention;
FIG. 3 is a schematic diagram of a portion of the structure A of FIG. 2;
FIG. 4 is an enlarged partial schematic view of the structure B of FIG. 2;
in the figure: PASS, load tube; CMP1, a voltage comparison unit; VOUT, voltage output terminal; c1, a first capacitor; c2, a second capacitor; s1, controlling a signal terminal at a low level; S1N, a high-level control signal terminal; SW1, a first switch; SW2, a second switch; SW3, a third switch; SW4, fourth switch; SW5, the fifth switch; r1 and a first resistor; r2 and a second resistor; r3, a third resistor; m0, a field effect tube; m1, a first MOS tube; m2, a second MOS tube; m3, a third MOS tube; m4, a fourth MOS tube; m5, a fifth MOS tube; m6, a sixth MOS tube; m7, a seventh MOS tube; m8, an eighth MOS tube;
m9, a ninth MOS tube; m10, a tenth MOS tube; m11 and an eleventh MOS tube; m12 and a twelfth MOS tube; m13, a thirteenth MOS tube; m14 and a fourteenth MOS tube; m15, a fifteenth MOS tube; m16 and a sixteenth MOS tube; m17 and a seventeenth MOS tube; m18, an eighteenth MOS tube; m19, a nineteenth MOS tube; m20 and a twentieth MOS tube; m21 and a twenty-first MOS transistor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the present invention provides a high performance LDO circuit based on switch dynamic switching, including a voltage comparison unit CMP1, an inverter, a switch group, and a load tube PASS, where an inverting input terminal of the voltage comparison unit CMP1 is externally connected with a VREF terminal, a non-inverting input terminal of the voltage comparison unit CMP1 is externally connected with a voltage output terminal VOUT, the voltage output terminal VOUT is grounded through a first capacitor C1, an output terminal of the voltage comparison unit CMP1 is electrically connected with the inverter, an output terminal of the inverter is connected with the switch group, the switch group is electrically connected with the load tube PASS, and an output terminal of the inverter outputs a control signal to control the switch group to switch on or off the load tube PASS, so as to implement that the voltage output terminal VOUT outputs a voltage feedback voltage to a voltage comparison module switching control signal. The output end of the inverter outputs control signals S1 and S1N, S1 is a low-level control signal terminal, S1N is a high-level control signal terminal, the switch group comprises a first switch SW1 to a fifth switch SW5, when S1N is high level and S1 is low level, the first switch SW1, a fourth switch SW4 and the fifth switch SW5 are disconnected, the second switch SW2 and the third switch SW3 are connected, the load tube PASS charges the first capacitor C1, when the voltage of the VFB terminal is higher than the voltage of the VREF terminal, S1N is changed into low level, S1 is high level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are connected, the second switch SW2 and the third switch SW3 are disconnected, so that the PASS tube is disconnected, the voltage of the first capacitor C1 is discharged through the fifth switch SW5, the voltage output end VOUT becomes low, the voltage of the VFB is caused, when the voltage of the VFB terminal is lower than the voltage of the terminal, S1N is changed into low level again, the voltage is changed into the low level along with the comparison of the comparison switch group, and the dynamic output voltage of the CMP1 becomes low level, and the comparison circuit becomes low level.
In this embodiment, further, the output end of the inverter includes a low level control signal terminal S1 and a high level control signal terminal S1N, the switch group includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4 and a fifth switch SW5, the second switch SW2 and the third switch SW3 are both connected to the high level control signal terminal S1N, and the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are all connected to the low level control signal terminal S1.
In this embodiment, a drain of the load tube PASS is connected to the positive input terminal of the voltage comparison unit CMP1 through a second capacitor C2, the drain of the load tube PASS is grounded through a first resistor R1, a second resistor R2 and a third resistor R3 which are connected in series, a gate of the load tube PASS is externally connected to a gate of a field effect tube M0, a drain of the field effect tube M0 is grounded through a second switch SW2, a source of the field effect tube M0 is connected to a source of the load tube PASS, the third switch SW3 is connected in parallel between the second capacitor C2 and the first resistor R1, the first switch SW1 is connected in parallel between the source of the load tube PASS and the gate of the load tube PASS, the fourth switch SW4 is connected in parallel between the second capacitor C2 and the second resistor R2, and the drain of the load tube PASS is grounded through a fifth switch SW 5.
As shown in fig. 2, 3 and 4, in this embodiment, the voltage comparison unit CMP1 further includes first to twenty-first MOS transistors M1 to M21, a source of the first MOS transistor M1 is connected to a source of the second MOS transistor M2 and to a drain of the third MOS transistor M3, a gate of the first MOS transistor M1 and a gate of the second MOS transistor M2 are respectively connected to a drain of the fifth MOS transistor M5 and a drain of the sixth MOS transistor M6, a gate of the third MOS transistor M3, a gate of the fourth MOS transistor M4 and a gate of the seventh MOS transistor M7 are respectively connected to a drain of the tenth MOS transistor M10, a gate of the tenth MOS transistor M10 is externally connected to an ENN enable terminal, a drain of the first MOS transistor M1 and a drain of the second MOS transistor M2 are respectively connected to a drain of the twelfth MOS transistor M12 and a drain of the thirteenth MOS transistor M13, a gate of the twelfth MOS transistor M12 and a drain of the thirteenth MOS 13 are connected to a drain of the fourteenth MOS transistor M12, a drain of the thirteenth MOS 13, a drain of the fourteenth MOS transistor M12 and a drain of the fourteenth MOS 13 are connected to both sides of the fourteenth MOS transistor M12, and a drain of the fourteenth MOS 12.
In this embodiment, further, the drain of the twelfth MOS transistor M12 is connected to the drain of the fifteenth MOS transistor M15 and the gate of the seventeenth MOS transistor M17, the drain of the thirteenth MOS transistor M13 is connected to the drain of the sixteenth MOS transistor M16 and the gate of the eighteenth MOS transistor M18, the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are externally connected to the ENP enable terminal, the drain of the seventeenth MOS transistor M17 is connected to the drain of the nineteenth MOS transistor M19, the drain of the eighteenth MOS transistor M18 is connected to the drain of the twentieth MOS transistor M20 and is used as the output terminal of the voltage comparison unit CMP1, the gate of the nineteenth MOS transistor M19 is connected to the gate of the twentieth MOS transistor M20 and the drain of the twenty-first MOS transistor M21, and the gate of the twenty-first MOS transistor M21 is externally connected to the ENN enable terminal.
In this embodiment, the source of the tenth MOS transistor M10, the source of the seventh MOS transistor M7, the source of the fourth MOS transistor M4, the source of the third MOS transistor M3, the source of the nineteenth MOS transistor M19, the source of the twentieth MOS transistor M20, and the source of the twenty-first MOS transistor M21 are externally connected to a VSS terminal.
In this embodiment, further, the gate of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6 are respectively connected to the drain of the ninth MOS transistor M9 and the drain of the eighth MOS transistor M8, the gate of the eighth MOS transistor M8 is externally connected to a VP terminal, the gate of the ninth MOS transistor M9 is externally connected to a VN terminal, the source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are both connected to the drain of the seventh MOS transistor M7, and the drain of the eighth MOS transistor M8, the drain of the ninth MOS transistor M9, the drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6 are respectively connected to the source of the eleventh MOS transistor through the fourth resistor, the fifth resistor, the sixth resistor and the seventh resistor.
In this embodiment, further, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, and the twenty-first MOS transistor M21 are all configured as N-type MOS transistors.
In this embodiment, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, and an eighteenth MOS transistor M18 are all P-type MOS transistors.
The working principle and the working process of the invention are as follows: the reverse phase input end of the voltage comparison unit CMP1 is externally connected with a VREF terminal, the non-positive phase input end of the voltage comparison unit CMP1 is externally connected with a VFB terminal, the output end of the inverter outputs control signals S1 and S1N, S1 is a low level control signal terminal, S1N is a high level control signal terminal, the switch group comprises a first switch SW1 to a fifth switch SW5, when S1N is a high level and S1 is a low level, the first switch SW1, a fourth switch SW4 and the fifth switch SW5 are switched off, the second switch SW2 and the third switch SW3 are switched on, the load tube PASS charges the first capacitor C1, when the VFB terminal voltage is higher than the VREF terminal voltage, the S1 is a low level, the S1 is a high level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are switched on, the second switch SW2 and the third switch SW3 are switched off, the load tube PASS tube is switched off, the voltage of the first capacitor C1 is discharged through the fifth switch SW5, the voltage output end VOUT becomes low, when the voltage reaches a low level, the VFB terminal voltage, the VFB terminal becomes lower than the VFB terminal, the voltage is changed into a low level, the voltage comparison unit CMP1 is changed into a balanced circuit, and the voltage is changed into a balanced circuit, and the high level, and the output end of the CMP1 is changed into a balanced circuit, and the high level, and the output circuit is changed into a low level.
When the output load of the voltage output end VOUT jumps to be low, the voltage of the VFB terminal is quickly reduced through the second capacitor C2 and is directly fed back to the voltage comparison module CMP1, the S1 terminal is changed into low level, the S1N terminal is changed into high level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are turned off, the second switch SW2 and the third switch SW3 are turned on, and the load tube PASS is turned on to pull up the level of the voltage output end VOUT; when the output load of the voltage output end VOUT jumps to be high, the VFB terminal quickly becomes high through the second capacitor C2 and is directly fed back to the voltage comparison module CMP1, the voltage of the S1 terminal becomes high level, the voltage of the S1N terminal becomes low level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are conducted, the second switch SW2 and the third switch SW3 are turned off, the PASS tube of the load tube is turned off, the VOUT of the voltage output is discharged through the fifth switch SW5, and the level of the voltage output end VOUT is pulled low. The second capacitor C2 can be used for improving loop feedback and plays a role in accelerating the circuit during operation.
The invention can improve the output attack resistance, and improves the response speed of the whole LDO by changing the traditional operational amplifier structure of the LDO into a comparison switch structure, thereby improving the transient response of the output load and improving the output attack resistance; in addition, the traditional PMOS operational amplifier LDO stabilizes output voltage through loop feedback, and the stability of the loop needs to be considered; the voltage comparison unit and the switch group are matched with each other, the structure is simple, and compared with the traditional LDO circuit structure, the whole power consumption of the LDO circuit is greatly reduced.
The embodiments of the present invention have been described in detail, but the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should be covered by the present patent.
Claims (9)
1. The utility model provides a high performance LDO circuit based on switch dynamic switching, its characterized in that, includes voltage comparison unit, phase inverter, switch group and load tube, voltage comparison unit's inverting input is external to have the VREF terminal, voltage comparison unit's normal phase input is external to have voltage output, voltage output passes through first electric capacity ground connection, voltage comparison unit's output with phase inverter electric connection, the output of phase inverter with the switch group links to each other, the switch group with load tube electric connection, the output control signal control switch of phase inverter organizes the switching so that the load tube switches on or shuts off to realize that voltage output voltage feeds back voltage comparison module switching control signal.
2. The LDO circuit of claim 1, wherein the output of the inverter comprises a low-level control signal terminal and a high-level control signal terminal, the switch set comprises a first switch, a second switch, a third switch, a fourth switch and a fifth switch, the second switch and the third switch are connected to the high-level control signal terminal, and the first switch, the fourth switch and the fifth switch are connected to the low-level control signal terminal.
3. The LDO circuit based on the dynamic switching of the switch as claimed in claim 2, wherein a drain of the load transistor is connected to a non-inverting input terminal of the voltage comparing unit through a second capacitor, and the drain of the load transistor is grounded through a first resistor, a second resistor and a third resistor connected in series, the gate of the load transistor is externally connected to a gate of a field effect transistor, the drain of the field effect transistor is grounded through a second switch, a source of the field effect transistor is connected to the source of the load transistor, the third switch is connected in parallel between the second capacitor and the first resistor, the first switch is connected in parallel between the source of the load transistor and the gate of the load transistor, the fourth switch is connected in parallel between the second capacitor and the second resistor, and the drain of the load transistor is grounded through a fifth switch.
4. The switching dynamic switching based high performance LDO circuit according to claim 1, wherein the voltage comparison unit comprises a first MOS transistor to a twenty-first MOS transistor, the source of the first MOS transistor is connected to the source of the second MOS transistor and to the drain of the third MOS transistor, the gate of the first MOS transistor and the gate of the second MOS transistor are connected to the drain of the fifth MOS transistor and the drain of the sixth MOS transistor, respectively, the gate of the third MOS transistor, the gate of the fourth MOS transistor and the gate of the seventh MOS transistor are connected to the drain of the tenth MOS transistor, the gate of the tenth MOS transistor is externally connected to an ENN enable terminal, the drain of the first MOS transistor and the drain of the second MOS transistor are connected to the drain of the twelfth MOS transistor and the drain of the thirteenth MOS transistor, respectively, the gate of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor, the gate of the thirteenth MOS transistor is connected to the drain of the twelfth MOS transistor, and the eleventh MOS transistor and the fourteenth MOS transistor are symmetrically connected to both sides of the twelfth MOS transistor and the thirteenth MOS transistor.
5. The high-performance LDO circuit based on dynamic switching of switches is characterized in that a drain of a twelfth MOS transistor is connected with a drain of a fifteenth MOS transistor and a gate of a seventeenth MOS transistor, a drain of a thirteenth MOS transistor is connected with a drain of a sixteenth MOS transistor and a gate of an eighteenth MOS transistor, the gates of the fifteenth MOS transistor and the sixteenth MOS transistor are externally connected with an ENP enabling terminal, the drain of the seventeenth MOS transistor is connected with a drain of a nineteenth MOS transistor, the drain of the eighteenth MOS transistor is connected with a drain of a twentieth MOS transistor and serves as an output end of a voltage comparison unit, the gate of the nineteenth MOS transistor is connected with a gate of the twentieth MOS transistor and a drain of the twenty first MOS transistor, and the gate of the twenty first MOS transistor is externally connected with an ENN enabling terminal.
6. The high-performance LDO circuit based on dynamic switching of switches as claimed in claim 4, wherein the source of the tenth MOS transistor, the source of the seventh MOS transistor, the source of the fourth MOS transistor, the source of the third MOS transistor, the source of the nineteenth MOS transistor, the source of the twentieth MOS transistor and the source of the twenty-first MOS transistor are externally connected to a VSS terminal.
7. The high-performance LDO circuit based on dynamic switching of switches according to claim 4, wherein a gate of a fifth MOS transistor and a gate of a sixth MOS transistor are respectively connected to a drain of a ninth MOS transistor and a drain of an eighth MOS transistor, the gate of the eighth MOS transistor is externally connected with a VP terminal, the gate of the ninth MOS transistor is externally connected with a VN terminal, a source of the eighth MOS transistor and a source of the ninth MOS transistor are both connected to the drain of the seventh MOS transistor, and the drain of the eighth MOS transistor, the drain of the ninth MOS transistor, the drain of the fifth MOS transistor and the drain of the sixth MOS transistor are respectively connected to the source of the eleventh MOS transistor through a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor.
8. The high-performance LDO circuit based on dynamic switching of switches of claim 4, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor and the twenty-first MOS transistor are all N-type MOS transistors.
9. The high-performance LDO circuit based on dynamic switching of switches of claim 4, wherein an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor and an eighteenth MOS transistor are all configured as P-type MOS transistors.
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| CN202211079987.1A CN115357080B (en) | 2022-09-05 | 2022-09-05 | High-performance LDO circuit based on switch dynamic switching |
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| CN202211079987.1A CN115357080B (en) | 2022-09-05 | 2022-09-05 | High-performance LDO circuit based on switch dynamic switching |
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| CN115357080B CN115357080B (en) | 2024-01-30 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103529895A (en) * | 2013-10-31 | 2014-01-22 | 无锡中星微电子有限公司 | High-stability voltage regulator |
| US9734904B1 (en) * | 2016-11-22 | 2017-08-15 | SK Hynix Inc. | Digital low drop-out regulator and resistive memory device using the same |
| CN108932003A (en) * | 2017-05-22 | 2018-12-04 | 敦宏科技股份有限公司 | Voltage-stablizer and intelligent method for stabilizing voltage drop in intelligent type low-voltage |
| KR20200006749A (en) * | 2018-07-11 | 2020-01-21 | 고려대학교 산학협력단 | Dual mode low-dropout regulator and operation thereof |
| CN111462802A (en) * | 2019-01-22 | 2020-07-28 | 上海汉容微电子有限公司 | Reading circuit of NOR flash memory |
| CN112256081A (en) * | 2020-10-27 | 2021-01-22 | 电子科技大学 | Low dropout regulator with self-adaptive charge pump |
| CN214098248U (en) * | 2020-12-31 | 2021-08-31 | 深圳开阳电子股份有限公司 | Low-power consumption LDO circuit |
| CN114257216A (en) * | 2020-09-22 | 2022-03-29 | 深圳英集芯科技股份有限公司 | Two-phase three-order ring oscillator circuit, related chip and electronic device |
-
2022
- 2022-09-05 CN CN202211079987.1A patent/CN115357080B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103529895A (en) * | 2013-10-31 | 2014-01-22 | 无锡中星微电子有限公司 | High-stability voltage regulator |
| US9734904B1 (en) * | 2016-11-22 | 2017-08-15 | SK Hynix Inc. | Digital low drop-out regulator and resistive memory device using the same |
| CN108932003A (en) * | 2017-05-22 | 2018-12-04 | 敦宏科技股份有限公司 | Voltage-stablizer and intelligent method for stabilizing voltage drop in intelligent type low-voltage |
| KR20200006749A (en) * | 2018-07-11 | 2020-01-21 | 고려대학교 산학협력단 | Dual mode low-dropout regulator and operation thereof |
| CN111462802A (en) * | 2019-01-22 | 2020-07-28 | 上海汉容微电子有限公司 | Reading circuit of NOR flash memory |
| CN114257216A (en) * | 2020-09-22 | 2022-03-29 | 深圳英集芯科技股份有限公司 | Two-phase three-order ring oscillator circuit, related chip and electronic device |
| CN112256081A (en) * | 2020-10-27 | 2021-01-22 | 电子科技大学 | Low dropout regulator with self-adaptive charge pump |
| CN214098248U (en) * | 2020-12-31 | 2021-08-31 | 深圳开阳电子股份有限公司 | Low-power consumption LDO circuit |
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| CN115357080B (en) | 2024-01-30 |
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