CN115344079A - Pulse control equipment and use method thereof - Google Patents
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G—PHYSICS
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- H—ELECTRICITY
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- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
- H01S3/10—Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
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Abstract
The invention provides a pulse control device and a using method thereof, wherein the pulse control device comprises: the pulse width conversion device comprises a clock counter module, a clock comparator module, a pulse width batch configuration module, a pulse width to clock number module and a pulse width output controller module. Through organic combination, can produce the sequence pulse of high time accuracy, different pulse widths, clock counter module is with FPGA hardware external selection 50M active clock source, through PLL (phase-locked loop) rising frequency to 500MHz, each clock count precision can reach 2ns, the clock stability can reach 0.2ns level, has guaranteed signal accuracy in the source.
Description
Technical Field
The invention relates to the technical field of pulse width control, in particular to pulse control equipment and a using method thereof.
Background
The pulse control technology is widely applied to the fields of radar, ultrasonic flaw detection and laser control, and particularly, along with the rapid development of the detection technology, the requirements on the performance diversity, the reliability and the operation convenience of the controller are higher and higher. An ideal light source for laser machining or medical cosmetology, for example, is a laser light source with high output beam quality, adjustable pulse width, repetition frequency and peak power, high stability and high reliability. However, the Q-switched fiber lasers on the market at present are basically single pulse width lasers, i.e. both the pulse width and the duty cycle are fixed and not ideal in performance.
The pulse control device generating variable multi-pulse-width signals at present is based on an MCU chip, is limited by the precision of an external crystal oscillator and an MCU internal timer, has the pulse width precision of ms level generally, and cannot be switched quickly, namely, the reaction time of level conversion is also ms level, and the switching speed is insufficient, so that the control precision of a laser or other controlled devices is insufficient, for example, chinese patent CN105356205A discloses a long-pulse-width and high-peak-power quasi-continuous optical fiber laser system, a driving system generates pulse current to drive a pumping source to output ms-level quasi-continuous pumping light, the central wavelength of the pumping source is 915 +/-2 nm, the pulse width of the pumping light is within the range of 0.2-50ms, and the duty ratio is within the range of 10% -50%. Therefore, how to design a pulse control device with higher precision is a technical problem which needs to be solved urgently.
Disclosure of Invention
In view of this, the present invention provides a pulse control apparatus and a method for using the same to solve the existing problem of low precision in generating variable multi-pulse width signals.
The technical scheme of the invention is realized as follows: in one aspect, the present invention provides a pulse control apparatus, wherein the pulse control apparatus comprises:
the pulse width batch configuration module comprises a clock counter module, a clock comparator module, a pulse width batch configuration module, a pulse width to clock number conversion module and a pulse width output controller module;
the clock counter module is electrically connected with the clock comparator module and is used for counting clocks by self and sending the counted number to the clock comparator module;
the clock comparator module is used for comparing the counting number of the clock counter module with the set number of the pulse width to clock number conversion module;
the pulse width batch configuration module is electrically connected with the pulse width to clock number conversion module and used for storing parallel sequence pulse width data and sending the parallel sequence pulse width data to the pulse width to clock number conversion module;
the pulse width to clock number conversion module is electrically connected with the clock comparator module and is used for sending the set number to the clock comparator module;
the pulse width output controller module is electrically connected with the clock comparator module and used for outputting level voltage according to the comparison result of the clock comparator module.
On the basis of the above technical solution, preferably, the clock counter module receives a count RESET signal RESET _ CNT sent by the clock comparator module, starts to receive an external clock signal CLK, performs high-speed self-counting of a clock, and sends the count number CLK _ CNT to the clock comparator module.
On the basis of the above technical solution, preferably, the clock comparator module sends a count RESET signal RESET _ CNT to the clock counter module when a trigger condition is satisfied, that is, when the level voltage of the external trigger signal TRIG changes, the clock counter module starts counting from zero, compares the count number CLK _ CNT of the clock counter module with the SET number SET _ CNT of the PULSE width to clock number module, and sends an output signal to the PULSE width output controller module to change the output level voltage PULSE _ OUT and simultaneously change the PULSE width SHIFT state PULSE _ SHIFT when the count number CLK _ CNT of the clock counter module is equal to the SET number SET _ CNT of the PULSE width to clock number module;
when the RESET signal RESET is powered on or abnormal, the state of the RESET signal is changed to RESET the clock comparator module.
On the basis of the technical scheme, preferably, the PULSE width batch configuration module sequentially sends parallel sequence PULSE width data PULSE _ WIDE1, PULSE _ WIDE2, \ 8230according to the change of the PULSE width SHIFT state PULSE _ SHIFT, and the PULSE _ WIDE is sent to the PULSE width to clock number conversion module;
and when the RESET signal RESET is powered on or abnormal, changing the state of the RESET signal to RESET the pulse width batch configuration module.
On the basis of the above technical solution, preferably, the PULSE width to clock number conversion module converts the parallel sequence PULSE width data PULSE _ wide into the number of clock counts according to the SET PULSE width, that is, the SET number SET _ CNT, where i =1,2, \ 8230, n, and the calculation formula is as follows:
wherein f is CLK Is the clock frequency.
On the basis of the above technical solution, preferably, the PULSE width output controller module receives the result of the clock comparator module, changes the output level voltage PULSE _ OUT, and stops working after n times of output level voltage PULSE _ OUT changes are completed;
and when the RESET signal RESET is powered on or abnormal, changing the state of the RESET signal to RESET the pulse width output controller module.
On the basis of the above technical solution, preferably, the clock counter module, the clock comparator module, the pulse width batch configuration module, the pulse width to clock number conversion module, and the pulse width output controller module are all implemented on FPGA hardware through Verilog codes.
On the basis of the above technical solution, preferably, EP4CE10 from Altera is used as the FPGA hardware.
In another aspect, the present invention provides a method for using a pulse control device, which uses the pulse control device as described above, wherein the method includes the following steps:
s1, changing the state of a RESET signal when a RESET signal RESET is electrified or abnormal, and resetting a clock comparator module, a pulse width batch configuration module and a pulse width output controller module;
s2, when the level voltage of the external trigger signal TRIG changes, the initial level signal START sets the output level voltage PULSE _ OUT of the PULSE width output controller module;
s3, the clock counter module receives a counting RESET signal RESET _ CNT sent by the clock comparator module, starts to receive an external clock signal CLK, performs clock self-adding counting, and sends the counting number CLK _ CNT to the clock comparator module;
s4, sending the parallel sequence PULSE width data PULSE _ WIDE1 to a PULSE width to clock number conversion module by a PULSE width batch configuration module, and converting the PULSE width to a SET number SET _ CNT;
s5, comparing the counting number CLK _ CNT of the clock counter module with the setting number SET _ CNT of the PULSE width to clock number conversion module by the clock comparator module, changing the output level voltage PULSE _ OUT by the PULSE width output controller module when the counting number CLK _ CNT is equal to the setting number SET _ CNT of the PULSE width to clock number conversion module, simultaneously performing PULSE width shift by the PULSE width batch configuration module, outputting the next parallel sequence PULSE width data PULSE _ WIDE2, sending a counting RESET signal RESET _ CNT by the clock comparator module, resetting the clock counter module, performing clock self-adding counting again by the clock counter, comparing by the clock comparator module again, changing the output level voltage PULSE _ OUT again when the counting number CLK _ CNT is equal to the setting number SET _ CNT, and repeating the steps until n PULSEs are output and then stopping working.
Compared with the prior art, the pulse control equipment and the using method thereof have the following beneficial effects:
(1) The clock counter module selects a 50M active clock source from the exterior of FPGA hardware, the frequency is raised to 500MHz through a PLL (phase-locked loop), the counting precision of each clock can reach 2ns, the clock stability can reach 0.2ns level, and the signal precision is ensured at the source;
(2) Pulse widths are configured in batch through the pulse width batch configuration module, and are configured in advance, so that computing resources in the working process of the system are not occupied;
(3) And the pulse width-to-clock number module realizes that the configured time sequence data Mi and Ni are converted into the counting number in batches in advance and are converted into integral multiples representing the minimum time unit. After the integer multiple is obtained, the int type calculation efficiency is higher, and the influence on the system is smaller.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of a pulse control apparatus of the present invention;
FIG. 2 is a schematic diagram of the operation of the pulse control apparatus of the present invention;
fig. 3 is a schematic diagram of time-series data of the pulse control device of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example one
As shown in fig. 1 to 2, a pulse control apparatus of the present invention, wherein the pulse control apparatus comprises:
the pulse width batch configuration module comprises a clock counter module, a clock comparator module, a pulse width batch configuration module, a pulse width to clock number conversion module and a pulse width output controller module;
the clock counter module is electrically connected with the clock comparator module and is used for counting clocks by self and sending the counted number to the clock comparator module;
the clock comparator module is used for comparing the counting number of the clock counter module with the set number of the pulse width to clock number conversion module;
the pulse width batch configuration module is electrically connected with the pulse width to clock number conversion module and used for storing parallel sequence pulse width data and sending the parallel sequence pulse width data to the pulse width to clock number conversion module;
the pulse width to clock number conversion module is electrically connected with the clock comparator module and is used for sending the set number to the clock comparator module;
the pulse width output controller module is electrically connected with the clock comparator module and used for outputting level voltage according to the comparison result of the clock comparator module.
The equipment adopts logic IP core to realize a trigger type variable multi-pulse width, the precision of the pulse width can reach ns level, a modularized product is formed through design, simulation and verification, the rapid transplantation among different platforms can be realized, and the product development process is accelerated.
The clock counter module receives a counting RESET signal RESET _ CNT sent by the clock comparator module, starts to receive an external clock signal CLK, performs high-speed clock self-adding counting, and sends the counting number CLK _ CNT to the clock comparator module.
The clock counter module selects a 50M active clock source from the exterior of FPGA hardware, the frequency is raised to 500MHz through a PLL (phase-locked loop), the counting precision of each clock can reach 2ns, the clock stability can reach 0.2ns level, and the signal precision is ensured at the source. The external clock signal CLK is clocked, and after triggering, counting is started from 0, e.g. recording the duration of high level reaching N x CLK, N x I.e. the count number CLK _ CNT.
When a trigger condition is met, namely the level voltage of the external trigger signal TRIG changes, the clock comparator module sends a counting RESET signal RESET _ CNT to the clock counter module, the clock counter module starts counting from zero, compares the counting number CLK _ CNT of the clock counter module with the SET number SET _ CNT of the PULSE width to clock number conversion module, and sends an output signal to the PULSE width output controller module to change the output level voltage PULSE _ OUT and change the PULSE width SHIFT state PULSE _ SHIFT when the counting number CLK _ CNT and the SET number SET _ CNT are equal;
when the RESET signal RESET is powered on or abnormal, the state of the RESET signal is changed to RESET the clock comparator module.
The clock comparator block is a device that generates an interrupt when the clock count value equals or exceeds a value specified by a program, that is, compares the count number CLK _ CNT of the clock counter block with the SET number SET _ CNT of the pulse width clock count by clock number block, and outputs a stop signal when CLK _ CNT = SET _ CNT, for example.
The PULSE width batch configuration module sequentially sends parallel sequence PULSE width data PULSE _ WIDE1, PULSE _ WIDE2, 8230according to the change of a PULSE width SHIFT state PULSE _ SHIFT;
and when the RESET signal RESET is powered on or abnormal, changing the state of the RESET signal to RESET the pulse width batch configuration module.
As shown in FIG. 3, the PULSE width batch configuration module can freely configure the time series data Mi and Ni (low and high level durations) of the required parallel sequence PULSE width data PULSE _ WIDE1, PULSE _ WIDE2, \8230, PULSE _ WIDEn through external communication, wherein i =1,2, \8230, n, and can send the time series data Mi and Ni to the PULSE width to clock number module at the moment of power-on start of the device, and the PULSE width batch configuration module is used for batch configuration of PULSE widths, and is configured in advance, and does not occupy the computing resources in the working process of the system.
The PULSE width to clock number conversion module converts parallel sequence PULSE width data PULSE _ WIDEi into the number of clock counts according to the SET PULSE width, namely the SET number SET _ CNT, wherein i =1,2, \8230, n, and the calculation formula is as follows:
wherein f is CLK Is the clock frequency.
And the pulse width-to-clock number module realizes that the configured time sequence data Mi and Ni are converted into the counting number in batches in advance and are converted into integral multiples representing the minimum time unit. The general time configuration is 0.002-1000.000ms, the time configuration is float double precision type, the calculation occupies resources, the speed is slow, if the batch calculation is not carried out in advance, the calculation is carried out in the pulse timing process, the system resources are occupied, the pulse output time of the pulse width output controller module is uncertain (generally, 10-1000 times of the minimum time unit 2ns are different, namely, the dynamic error of ms level), after the pulse output time becomes integral multiple, the int type calculation efficiency is higher, and the influence on the system is smaller.
The PULSE width output controller module receives the result of the clock comparator module, changes the output level voltage PULSE _ OUT, and stops working after n times of output level voltage PULSE _ OUT changes are completed;
and when the RESET signal RESET is powered on or abnormal, changing the state of the RESET signal to RESET the pulse width output controller module.
The PULSE width output controller module changes the output level voltage PULSE _ OUT, the PULSE width batch configuration module performs PULSE width shift at the same time, next parallel sequence PULSE width data PULSE _ WIDE2 is output, the clock comparator module sends OUT a counting RESET signal RESET _ CNT, the clock counter module RESETs again, the clock counter counts again by the clock counter, the clock comparator module compares again, when the two are equal, the output level voltage PULSE _ OUT is changed again, the operation is circulated until n PULSEs are output, and then the operation is stopped.
The clock counter module, the clock comparator module, the pulse width batch configuration module, the pulse width to clock number conversion module and the pulse width output controller module are all realized on FPGA hardware through Verilog codes.
The method can receive an external serial port sending instruction and is realized by an NIOS system driver of the FPGA.
The FPGA hardware adopts the EP4CE10 of Altera corporation.
And (3) externally selecting a 50M clock source, and increasing the frequency to 500MHz through PLL, wherein the counting precision of each clock can reach 2ns.
The pulse control device in this embodiment can set different time sequence data Mi and Ni, where Mi and Ni are not necessarily the same, and implement sequence change rhythm control of pulse signal output, that is, the variable multiple pulse widths can generate sequence pulses with high time accuracy and different pulse widths through organic combination, so as to achieve application effects in complex scenes, for example, in an active excitation experiment, an accurate activation effect can be achieved by controlling the time of the changed pulse width.
Example two
There is provided a method for using a pulse control device according to an embodiment, including the steps of:
s1, changing the state of a RESET signal to RESET a clock comparator module, a pulse width batch configuration module and a pulse width output controller module when a RESET signal RESET is electrified or abnormal;
s2, when the level voltage of the external trigger signal TRIG changes, the initial level signal START sets the output level voltage PULSE _ OUT of the PULSE width output controller module;
s3, the clock counter module receives a counting RESET signal RESET _ CNT sent by the clock comparator module, starts to receive an external clock signal CLK, performs clock self-adding counting, and sends the counting number CLK _ CNT to the clock comparator module;
s4, sending the parallel sequence PULSE width data PULSE _ WIDE1 to a PULSE width to clock number conversion module by a PULSE width batch configuration module, and converting the PULSE width to a SET number SET _ CNT;
s5, comparing the counting number CLK _ CNT of the clock counter module with the setting number SET _ CNT of the PULSE width to clock number conversion module by the clock comparator module, changing the output level voltage PULSE _ OUT by the PULSE width output controller module when the counting number CLK _ CNT is equal to the setting number SET _ CNT of the PULSE width to clock number conversion module, simultaneously performing PULSE width shift by the PULSE width batch configuration module, outputting the next parallel sequence PULSE width data PULSE _ WIDE2, sending a counting RESET signal RESET _ CNT by the clock comparator module, resetting the clock counter module, performing clock self-adding counting again by the clock counter, comparing by the clock comparator module again, changing the output level voltage PULSE _ OUT again when the counting number CLK _ CNT is equal to the setting number SET _ CNT, and repeating the steps until n PULSEs are output and then stopping working.
As shown in fig. 2, the trigger provides a trigger signal, such as a PLC, a high-low output sensor, etc.; the computer or other serial port controllers send data to the memory space of the NIOS through serial communication (RXD) to carry out parameter configuration; the RESET can realize the erasing and emptying control of parameters; the output level voltage PULSE _ OUT is directly connected to an IO control port of laser equipment through a PULSE output port, and the existence of laser output is controlled.
The application method of the pulse control equipment in the embodiment is completed by adopting a standard Verilog language, and by adopting a modular design method, the pulse control equipment can receive an external serial port sending instruction, and an NIOS (network input/output) inside the FPGA drives an IP (Internet protocol) core, so that the flexibility and the expansibility are improved, and nanosecond trigger type variable multi-pulse-width square waves can be generated by FPGA hardware.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.
Claims (8)
1. A pulse control apparatus characterized by: the pulse control apparatus includes:
the pulse width batch configuration module comprises a clock counter module, a clock comparator module, a pulse width batch configuration module, a pulse width to clock number conversion module and a pulse width output controller module;
the clock counter module is electrically connected with the clock comparator module and is used for counting clocks by self and sending the counted number to the clock comparator module;
the clock comparator module is used for comparing the counting number of the clock counter module with the set number of the pulse width to clock number conversion module;
the pulse width batch configuration module is electrically connected with the pulse width to clock number conversion module and used for storing parallel sequence pulse width data and sending the parallel sequence pulse width data to the pulse width to clock number conversion module;
the pulse width to clock number conversion module is electrically connected with the clock comparator module and is used for sending the set number to the clock comparator module;
the pulse width output controller module is electrically connected with the clock comparator module and used for outputting level voltage according to the comparison result of the clock comparator module.
2. The pulse control apparatus according to claim 1, wherein: the clock counter module receives a counting RESET signal RESET _ CNT sent by the clock comparator module, starts to receive an external clock signal CLK, performs high-speed clock self-adding counting, and sends the counting number CLK _ CNT to the clock comparator module.
3. The pulse control apparatus according to claim 2, wherein: when a trigger condition is met, namely level voltage change occurs in an external trigger signal TRIG, the clock comparator module sends a counting RESET signal RESET _ CNT to the clock counter module, the clock counter module starts counting from zero, compares the counting number CLK _ CNT of the clock counter module with the SET number SET _ CNT of the PULSE width to clock number conversion module, and sends an output signal to the PULSE width output controller module to change an output level voltage PULSE _ OUT and a PULSE width SHIFT state PULSE _ SHIFT when the counting number CLK _ CNT and the SET number SET _ CNT are equal;
when the RESET signal RESET is powered on or abnormal, the state of the RESET signal is changed to RESET the clock comparator module.
4. A pulse control apparatus according to claim 3, wherein: the PULSE width batch configuration module sequentially sends parallel sequence PULSE width data PULSE _ WIDE1, PULSE _ WIDE2, \ 8230according to the change of the PULSE width SHIFT state PULSE _ SHIFT;
and when the RESET signal RESET is powered on or abnormal, changing the state of the RESET signal to RESET the pulse width batch configuration module.
5. Pulse control device according to claim 4, characterized in that: the PULSE width to clock number module converts the parallel sequence PULSE width data PULSE _ WIDEi into the number of clock counts according to the SET PULSE width, namely the SET number SET _ CNT, wherein i =1,2, \8230, n, and the calculation formula is as follows:
wherein, f CLK Is the clock frequency.
6. A pulse control apparatus according to claim 3, wherein: the PULSE width output controller module receives the result of the clock comparator module, changes the output level voltage PULSE _ OUT, and stops working after n times of output level voltage PULSE _ OUT changes are completed;
and when the RESET signal RESET is powered on or abnormal, changing the state of the RESET signal to RESET the pulse width output controller module.
7. The pulse control apparatus according to claim 1, wherein: the clock counter module, the clock comparator module, the pulse width batch configuration module, the pulse width to clock number conversion module and the pulse width output controller module are all realized on FPGA hardware through Verilog codes.
8. Use of a pulse control device according to any of claims 1-7, characterized in that: the method comprises the following steps:
s1, changing the state of a RESET signal when a RESET signal RESET is electrified or abnormal, and resetting a clock comparator module, a pulse width batch configuration module and a pulse width output controller module;
s2, when the level voltage of the external trigger signal TRIG changes, setting the output level voltage PULSE _ OUT of the PULSE width output controller module by the initial level signal START;
s3, the clock counter module receives a counting RESET signal RESET _ CNT sent by the clock comparator module, starts to receive an external clock signal CLK, performs clock self-adding counting, and sends the counting number CLK _ CNT to the clock comparator module;
s4, sending parallel sequence PULSE width data PULSE _ WIDE1 to a PULSE width to clock number conversion module by a PULSE width batch configuration module, and converting the PULSE width to SET number SET _ CNT;
s5, comparing the counting number CLK _ CNT of the clock counter module with the setting number SET _ CNT of the PULSE width to clock number module by the clock comparator module, changing the output level voltage PULSE _ OUT by the PULSE width output controller module when the counting number CLK _ CNT and the setting number SET _ CNT are equal, simultaneously performing PULSE width shift by the PULSE width batch configuration module, outputting the next parallel sequence PULSE width data PULSE _ WIDE2, sending a counting RESET signal RESET _ CNT by the clock comparator module, resetting the clock counter module, performing clock self-counting again by the clock counter, comparing by the clock comparator module again, changing the output level voltage PULSE _ OUT again when the counting number CLK _ CNT and the setting number SET _ CNT are equal, and circulating until n PULSEs are output and stopping working.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102668379A (en) * | 2009-10-13 | 2012-09-12 | 相干公司 | Digital pulse-width-modulation control of a radio frequency power supply for pulsed laser |
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| CN115344079B (en) | 2023-03-10 |
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