CN115332227A - Chip area typesetting method - Google Patents

Chip area typesetting method Download PDF

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Publication number
CN115332227A
CN115332227A CN202110506288.XA CN202110506288A CN115332227A CN 115332227 A CN115332227 A CN 115332227A CN 202110506288 A CN202110506288 A CN 202110506288A CN 115332227 A CN115332227 A CN 115332227A
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China
Prior art keywords
preset
chip
debugging
area
initial
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CN202110506288.XA
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Chinese (zh)
Inventor
左孝
张诗华
赵志平
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110506288.XA priority Critical patent/CN115332227A/en
Publication of CN115332227A publication Critical patent/CN115332227A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information

Abstract

A method for chip area typesetting comprises the following steps: providing a preset wafer area, a process node and a preset chip area; arranging a plurality of rectangular initial chip regions which are mutually independent in a preset wafer region according to the area of a preset chip, wherein the initial chip regions have an initial preset length and an initial preset width; debugging the initial preset length and the initial preset width for a plurality of times according to the preset chip area and the process node so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, wherein the chip areas have the preset chip area, and the number of the chip areas is greater than that of the preset chip areas. The chip area typesetting method can improve the number of chips which can be manufactured on one wafer, reduce the waste of raw materials and improve the productivity and benefit of semiconductor manufacturing.

Description

Chip area typesetting method
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for typesetting a chip area.
Background
With the rapid development of integrated circuit manufacturing technology, the electronic devices in the integrated circuits are smaller and smaller, and the integration level of the integrated circuits is higher and higher. Accordingly, as the degree of integration of integrated circuits increases, the number of chips that can be formed on one wafer (wafer) increases.
Generally, in the prior art, before designing a chip, simulation deduction is performed according to a wafer size and several preset chip shapes, and chip regions corresponding to the chip shapes are roughly typeset in a wafer region corresponding to the wafer for several times to form a corresponding chip region typesetting scheme. By each chip area typesetting scheme, the number of chips which can be manufactured on a wafer under the corresponding chip shape, a plurality of typesetting modes of the chip shape on the wafer and the like can be obtained. And then, after selecting a chip typesetting scheme, carrying out subsequent chip design according to the chip shape in the chip typesetting scheme.
As is well known, since wafers are disposable raw materials and each wafer is expensive, it is necessary to manufacture as many chips as possible on one wafer to fully utilize the raw materials and increase the productivity and efficiency of semiconductor manufacturing.
However, the chip area layout scheme of the prior art can manufacture a small number of chips on one wafer, resulting in waste of raw materials and poor yield and efficiency of semiconductor manufacturing.
Disclosure of Invention
The invention provides a method for typesetting chip areas, which aims to increase the number of chips which can be manufactured on a wafer, reduce the waste of raw materials and improve the productivity and benefit of semiconductor manufacturing.
In order to solve the above technical problem, a technical solution of the present invention provides a method for chip area typesetting, including: providing a preset wafer area, a process node and a preset chip area; arranging a plurality of rectangular initial chip regions which are mutually independent in a preset wafer region according to the area of a preset chip, wherein the initial chip regions have an initial preset length and an initial preset width; debugging the initial preset length and the initial preset width for a plurality of times according to the preset chip area and the process node so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, wherein the chip areas have the preset chip area, and the number of the chip areas is greater than that of the preset chip areas.
Optionally, the number of times of the debugging process is more than 2; the method for debugging processing each time comprises the following steps: adjusting an initial preset length and an initial preset width according to a preset chip area and a process node, and acquiring a debugging preset length and a debugging preset width, wherein the debugging preset lengths are different at each time, and the debugging preset widths are different at each time; according to the preset debugging length and the preset debugging width, a plurality of rectangular debugging chip regions which are independent from each other are arranged in the preset wafer region, and the debugging chip regions have preset chip areas.
Optionally, the method for performing debugging processing for several times includes: providing preset debugging times; and debugging the preset debugging times, and acquiring the debugging preset length and the debugging preset width corresponding to each debugging.
Optionally, the method for performing debugging processing for several times further includes: providing a preset change percentage, a preset change function or a preset change quantity; the method for debugging processing each time further comprises the following steps: and changing the debugging preset length and the debugging preset width acquired at the n-1 th time according to the preset change percentage, the preset change function or the preset change quantity to form the debugging preset length and the debugging preset width acquired at the n-th time, wherein n is a natural number greater than or equal to 2.
Optionally, the method for performing debugging processing on the initial preset length and the initial preset width for several times according to the preset chip area and the process node to arrange a plurality of mutually independent rectangular chip regions in the preset wafer region includes: according to the method, a plurality of rectangular chip areas which are independent from each other are arranged in a preset wafer area once the debugging chip areas with the largest number are arranged in a plurality of times of debugging processing, and the chip areas have debugging preset lengths and debugging preset widths corresponding to the debugging processing.
Optionally, the method of performing debugging processing on the initial preset length and the initial preset width for several times according to the preset chip area and the process node to arrange a plurality of mutually independent rectangular chip regions in the preset wafer region further includes: when the maximum and same number of debugging chip regions are arranged for multiple times in a plurality of times of debugging processing, a plurality of mutually independent rectangular chip regions are arranged in a preset wafer region according to the arrangement of the maximum number of debugging chip regions for one time, and the chip regions have debugging preset lengths and debugging preset widths corresponding to the debugging processing.
Optionally, the method further includes: providing a preset cutting path width; arranging the initial chip areas according to the preset cutting channel width, wherein the preset cutting channel width is formed between every two adjacent initial chip areas; and carrying out debugging treatment for a plurality of times according to the width of the cutting channel, wherein the preset cutting channel width is arranged between adjacent chip areas.
Optionally, the preset wafer region includes a groove region and a wafer identification region, the groove region is used for fixing the wafer, the groove region and the initial chip region are independent of each other, the groove region and the chip region are independent of each other, the wafer identification region is used for forming marks for distinguishing wafers, the wafer identification region and the initial chip region are independent of each other, and the wafer identification region and the chip region are independent of each other.
Optionally, the method further includes: providing a width of the edge region; arranging the initial chip areas according to the width of the edge areas, wherein the minimum distance between the edges of the initial chip areas and the edges of the preset wafer areas is larger than or equal to the width of the edge areas; and carrying out debugging processing for a plurality of times according to the width of the edge area, wherein the minimum distance between the edge of the chip area and the edge of the preset wafer area is greater than or equal to the width of the edge area.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for typesetting the chip area provided by the technical scheme of the invention, the chip area has the preset chip area and is obtained after adjustment based on the process node, so that the chip area meets the design requirement of the chip with the preset chip area. On the basis, after the initial chip areas are arranged, debugging processing is carried out for a plurality of times on the initial preset length and the initial preset width according to the preset chip area and the process node so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, therefore, fine debugging can be carried out on the typesetting basis of the initial chip areas through the debugging processing, and more chip areas compared with the initial chip areas are formed in the preset wafer area, so that a more optimized chip area typesetting method and a more reasonable chip area shape are obtained, and further, the number of chips which can be manufactured on one wafer is increased, the waste of raw materials is reduced, and the productivity and the benefit of semiconductor manufacturing are improved.
Drawings
FIG. 1 is a flowchart illustrating a method for chip region layout according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a predetermined wafer area;
FIG. 3 is a layout diagram of an initial chip region;
FIG. 4 is a flowchart illustrating the debugging process of FIG. 1;
FIG. 5 is a layout diagram of a debug chip area.
Detailed Description
As described in the background, the chip area layout scheme of the prior art can produce a smaller number of chips on a wafer, resulting in a waste of raw materials and a poor yield and efficiency of semiconductor manufacturing.
In order to solve the technical problem, an embodiment of the present invention provides a method for typesetting a chip region, where a plurality of rectangular chip regions independent of each other are arranged in a preset wafer region by performing debugging processing on an initial preset length and an initial preset width for a plurality of times according to a preset chip area and a process node, and the chip regions have preset chip areas, and the number of the chip regions is greater than that of the preset chip regions, so that the number of chips that can be manufactured on one wafer can be increased, waste of raw materials can be reduced, and the yield and benefit of semiconductor manufacturing can be increased.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
Fig. 1 is a flowchart illustrating a method for typesetting a chip area according to an embodiment of the invention.
Referring to fig. 1, the method for typesetting a chip region includes:
step S100, providing a preset wafer region, a process node and a preset chip area;
step S110, arranging a plurality of mutually independent rectangular initial chip regions in a preset wafer region according to the area of a preset chip, wherein the initial chip regions have an initial preset length and an initial preset width;
step S120, debugging the initial preset length and the initial preset width for a plurality of times according to the preset chip area and the process node, so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, wherein the chip areas have the preset chip area, and the number of the chip areas is greater than that of the preset chip areas.
The process node is the minimum line width that the semiconductor structure reaches during the integrated circuit processing, i.e., the characteristic dimension that the semiconductor structure reaches.
Since the chip region has the preset chip area and is obtained after adjustment based on the process node, the chip region meets the design requirement of the chip with the preset chip area. On the basis, after the initial chip areas are arranged, debugging processing is carried out for a plurality of times on the initial preset length and the initial preset width according to the preset chip area and the process node so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, therefore, fine debugging can be carried out on the typesetting basis of the initial chip areas through the debugging processing, and more chip areas compared with the initial chip areas are formed in the preset wafer area, so that a more optimized chip area typesetting method and a more reasonable chip area shape are obtained, and further, the number of chips which can be manufactured on one wafer is increased, the waste of raw materials is reduced, and the productivity and the benefit of semiconductor manufacturing are improved.
Referring to fig. 2, fig. 2 is a schematic diagram of a predetermined wafer area in fig. 1, and a predetermined wafer area 100 is provided.
In the present embodiment, the predetermined wafer area 100 is provided according to the diameter dimension D of the wafer to be used when manufacturing the chip.
For example, in a chip manufacturing process, when a wafer with a diameter of 200mm is scheduled to be used, a preset wafer area is provided by simulating an area corresponding to the shape of the wafer with the diameter.
It should be understood that the predetermined wafer area is not limited to be provided based on a wafer having a diameter of 200mm, for example, when a wafer having a diameter of 300mm is intended to be used, the predetermined wafer area 100 is provided based on a wafer having a diameter of 300mm, etc.
In this embodiment, the predetermined chip area S is provided according to the occupied area of the chip.
Specifically, before the chip is finally designed in detail, the required area of the chip is estimated according to the process node, the functional requirements of the chip and the like, so as to determine the preset chip area S corresponding to the chip.
In this embodiment, the predetermined wafer area 100 includes a notch area 101 (notch) and a wafer mark area 102 (Id Zone area), and the wafer mark area 102 is used to form a mark for distinguishing each wafer.
In this embodiment, the groove region 101 is located in the wafer mark region 102.
It should be noted that, although fig. 2 illustrates the default wafer area 100, the groove area 101 and the wafer mark area 102 separately. However, in the process of actually composing the chip regions, the preset wafer region 100, the preset groove region 101, and the wafer mark region 102 may be separately obtained and displayed by providing the wafer size (for example, the diameter size D of the wafer), or in the process of executing step S110, the corresponding preset wafer region 100, groove region 101, and wafer mark region 102 may be obtained, and the preset wafer region 100, groove region 101, and wafer mark region 102 may be displayed in synchronization with the arranged plurality of initial chip regions.
Referring to fig. 3, fig. 3 is a schematic layout diagram of initial chip regions, in which a plurality of independent rectangular initial chip regions 110 are arranged in a predetermined wafer region 100 according to a predetermined chip area S, the initial chip regions 110 have an initial predetermined length H X And an initial preset width W X 。
Specifically, the area of each initial chip region 110 is a preset chip area S.
In this embodiment, the method for arranging a plurality of independent rectangular initial chip regions 110 in the predetermined wafer region 100 according to the predetermined chip area S includes: obtaining an initial preset length H according to a preset chip area S X And an initial preset width W X Wherein the initial preset length H X And an initial preset width W X The product of (a) and (b) is equal to the preset chip area S; a plurality of the glass fibers are provided with initial preset lengths H X And an initial preset width W X Are arrayed in a first direction X and a second direction Y in a predetermined wafer area 100, having an initial predetermined length H X And an initial preset width W X The rectangular area of (1) is the initial chip area 110, and the first direction X and the second direction Y are perpendicular to each other.
In this embodiment, the groove region 101 and the initial chip region are independent from each other, and the wafer mark region 102 and the initial chip region are independent from each other. Specifically, the initial chip regions 110 are arranged in the predetermined wafer region 100 except for the groove region 101 and the wafer identification region 102.
In the present embodiment, a predetermined scribe line width M is provided. And, while arranging a plurality of initial chip regions 110 according to a preset chip area S, also arranging the initial chip regions 110 according to the preset scribe lane width M. Specifically, the preset scribe line width M exists between adjacent initial chip regions 110, that is, a scribe line region exists between adjacent initial chip regions 110.
In the present embodiment, the edge region width W is provided E (Edge Exclusion). And, a plurality of chips are arranged according to the preset chip area SWhile the initial chip region 110 is formed, it is also based on the width W of the edge region E The preliminary chip region 110 is arranged. Specifically, the minimum distance between the edge of the initial chip region 110 and the edge of the predetermined wafer region 100 is greater than or equal to the edge region width W E 。
The preset scribe line width M is formed between the adjacent initial chip regions 110, and the minimum distance between the edge of the initial chip region 110 and the edge of the preset wafer region 100 is greater than or equal to the edge region width W E The layout of the initial chip region 110 can be made to have the same limitation as the layout of the debug chip region in the subsequent debug processing.
It should be noted that fig. 3 only schematically illustrates a portion of the initial chip region 110 arranged in the predetermined wafer region 100. Meanwhile, although the pre-wafer area 100, the groove area 101, the wafer mark area 102 and the initial chip area 110 are schematically shown in fig. 3 for easy understanding, the pre-wafer area 100, the groove area 101, the wafer mark area 102 and the initial chip area 110 may not be shown in step S110, but the pre-wafer area 100, the groove area 101, the wafer mark area 102 and the initial chip area 110 may be provided by the wafer size (e.g., the diameter size D of the wafer) and the initial pre-set length H X And an initial preset width W X The parameters are calculated and parameters related to the layout of the initial chip regions 110, such as the number of the initial chip regions 110, are output.
In the present embodiment, the number of times of the debugging process in step S120 is 2 times or more. Through more than 2 times of debugging processing, at least 2 sets of parameters corresponding to the debugging processing can be acquired, thereby facilitating the arrangement of a greater number of chip areas in the preset wafer area 100.
In other embodiments, the number of times of the debugging process in step S120 is 1.
Referring to fig. 4, fig. 4 is a schematic flowchart of the debugging process in fig. 1, where the method of debugging process each time includes:
step S121, adjusting an initial preset length and an initial preset width according to a preset chip area and a process node, and acquiring a debugging preset length and a debugging preset width, wherein the debugging preset length is different for each time, and the debugging preset width is different for each time;
step S122, arranging a plurality of mutually independent rectangular debugging chip regions in a preset wafer region according to the debugging preset length and the debugging preset width, wherein the debugging chip regions have preset chip areas.
Referring to fig. 5, fig. 5 is a schematic layout diagram of a debug chip area, where an initial preset length H is adjusted according to a preset chip area S and a process node X And an initial preset width W X Obtaining a preset debugging length H T And debugging the preset width W T Each debugging preset length H T Different, each time the preset width W is debugged T Different; according to a preset debugging length H T And debugging the preset width W T A plurality of rectangular debug chip regions 120 that are independent of each other are arranged in the preset wafer region 100, and the debug chip regions 120 have a preset chip area S.
Specifically, the debug chip area 120 has a debug default length H T And debugging the preset width W T Debugging the preset length H T And debugging the preset width W T The product of (a) is equal to the predetermined chip area S.
It should be noted that, for convenience of understanding, fig. 5 schematically shows layout diagrams of 2 types of debug chip regions 120, and in the layout diagram of each debug chip region 120, only a part of the debug chip regions 120 arranged in the predetermined wafer region 100 is schematically shown. In fig. 5, the layout diagram of each debug chip region 120 corresponds to the result after 1 debug processing, and in the layout diagrams of the 2 debug chip regions 120, the shapes and sizes of the debug chip regions 120 are different. Specifically, in a layout diagram of the debug chip area 120, the debug chip area 120 has a debug default length H T1 And debugging the preset width W T1 In another layout diagram of the debug chip area 120, the debug chip area 120 has a debug default length H T2 And debugging the preset width W T2 And, debugging the preset length H T1 And debugging preset length H T2 In contrast to this, the present invention is,debugging preset width W T1 And debugging the preset width W T2 Different.
It should be noted that, during the actual debugging process, the preset length H is set despite each debugging T Different, each debugging preset width W T Different, that is, the layout of the debug chip area 120 differs from one time to another. However, after each debugging process, the number of the debug chip regions 120 arranged in the predetermined wafer region 100 may be the same or different.
It should be understood that the number of times of the debugging process is not limited to 2 times, and may be performed 3 times or more according to actual needs.
In this embodiment, the method for performing debugging processing for several times includes: providing preset debugging times; debugging processing of preset debugging times is carried out, and a preset debugging length H corresponding to each debugging processing is obtained T And debugging the preset width W T 。
In other embodiments, the final debugging times may also be determined in the process of several times of debugging processing according to the actual debugging result.
In this embodiment, the method for performing debugging processing for several times further includes: providing a preset change percentage, a preset change function or a preset change quantity. Moreover, the method for debugging processing each time further comprises the following steps: changing the debugging preset length H acquired at the n-1 st time according to the preset change percentage, the preset change function or the preset change quantity Tn-1 And debugging the preset width W Tn-1 Forming the debugging preset length H acquired at the nth time Tn And debugging the preset width W Tn Wherein n is a natural number greater than or equal to 2.
Specifically, the initial preset length H is changed according to a preset change percentage, a preset change function or a preset change amount X And an initial preset width W X Forming a 1 st debug preset length H T1 And debugging the preset width W T1 。
For example, the initial preset length H X And an initial preset width W X Respectively multiplying the preset change percentages to form the preset debugging length of the 1 st timeH T1 And debugging the preset width W T1 To perform the 1 st debugging process. On the basis, starting from the 2 nd debugging processing, the debugging preset length H acquired from the n-1 st time is sequentially obtained Tn-1 And debugging the preset width W Tn-1 Respectively multiplying the preset change percentages to form the debugging preset length H acquired at the nth time Tn And debugging the preset width W Tn 。
In this embodiment, the initial preset length H is determined according to the preset chip area S and the process node pair X And an initial preset width W X The method of performing the debugging process several times to arrange a plurality of mutually independent rectangular chip regions in the preset wafer region 100 includes: arranging a plurality of mutually independent rectangular chip areas in a preset wafer area 100 according to the condition that the maximum number of debugging chip areas 120 is arranged in a plurality of times of debugging processing, wherein the chip areas have debugging preset lengths H corresponding to the debugging processing T And debugging the preset width W T . Therefore, the typesetting of the chip area can be better optimized, the number of chips which can be manufactured on one wafer is further increased, the waste of raw materials is reduced, and the productivity and the benefit of semiconductor manufacturing are improved.
Specifically, by each debugging process, a debugging result corresponding to the debugging process can be acquired: the number of the debug chip regions 120, and the debug preset length H associated with the layout of the debug chip regions 120 T And debugging the preset width W T And the like. After obtaining the debugging results corresponding to the debugging processes for a plurality of times, the debugging process for the debugging chip region 120 with the largest number is selected, and the typesetting method of the debugging chip region 120 corresponding to the debugging process for this time is used as the method for arranging the chip regions in the preset wafer region 100. That is, the typesetting method of the debug chip area 120 corresponding to the debugging process is used as the typesetting method of the chip area, and correspondingly, the debug chip area 120 in the debugging process is used as the chip area.
In this embodiment, the initial preset length H is determined according to the preset chip area S and the process node pair X And an initial preset width W X Performing debugging process for several timesThe method for arranging a plurality of mutually independent rectangular chip regions in the preset wafer region 100 further includes: when the maximum and same number of debug chip regions 120 are arranged for a plurality of times in the plurality of debugging processes, a plurality of rectangular chip regions independent of each other are arranged in the preset wafer region 100 according to the arrangement of the maximum number of debug chip regions 120 for the first time, and the chip regions have the debug preset length H corresponding to the debugging process for the time Tn And debugging the preset width W Tn 。
In other embodiments, when the maximum and same number of debug chip regions are arranged for multiple times in the debugging processing of multiple times, a plurality of rectangular chip regions which are mutually independent and are arranged in the wafer region are preset according to any one of the debug chip regions, and each chip region has a debug preset length H corresponding to the debugging processing of the time Tn And debugging the preset width W Tn 。
It should be noted that, according to actual manufacturing requirements, the chip regions with the same shape may be arranged in the whole predetermined wafer region 100 to manufacture the same chips on one wafer. The debugging process may be performed in at least two non-overlapping regions of the predetermined wafer region 100, and the chip regions with different shapes may be arranged, so as to manufacture at least 2 different types of chips on one wafer.
In this embodiment, the groove region 101 and the debug chip region 120 are independent from each other, and the wafer mark region 102 and the debug chip region 120 are independent from each other. Specifically, the debug chip area 120 is arranged in the predetermined wafer area 100 except for the groove area 101 and the wafer mark area 102. Accordingly, the chip regions are arranged in the predetermined wafer region 100 except for the groove region 101 and the wafer mark region 102.
In this embodiment, the method for chip region layout further includes: and carrying out debugging treatment for a plurality of times according to the width M of the cutting channel. In each debugging process, the preset scribe line width M exists between adjacent debugging chip areas 120, that is, a scribe line area also exists between adjacent debugging chip areas 120. Correspondingly, the preset scribe line width M exists between adjacent chip regions, that is, the scribe line regions also exist between adjacent chip regions.
By making the preset Scribe Lane width M between adjacent chip regions, that is, making the Scribe Lane region between adjacent chip regions, a space of a Scribe Lane (Scribe Lane) is reserved for manufacturing chips, so as to cut a wafer to form a plurality of chips.
It should be understood that the shape of the scribe line region between adjacent debug chip regions 120 changes with the size of the debug chip region 120 at each debug process.
In this embodiment, the method for chip region layout further includes: according to the width W of the edge region E The debugging process is performed several times. In each debugging process, the minimum distance between the edge of the debugging chip area 120 and the edge of the preset wafer area 100 is greater than or equal to the width W of the edge area E . Correspondingly, the minimum distance between the edge of the chip region and the edge of the predetermined wafer region 100 is greater than or equal to the edge region width W E 。
Because the risk of deformation and other defects in the edge region of the wafer is high, the minimum distance between the edge of the chip region and the edge of the preset wafer region 100 is larger than or equal to the width W of the edge region E The influence of the defects such as deformation and the like of the edge area on the chip is reduced, and the performance and the reliability of the chip are improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (9)

1. A method for typesetting in a chip area is characterized by comprising the following steps:
providing a preset wafer area, a process node and a preset chip area;
arranging a plurality of rectangular initial chip regions which are mutually independent in a preset wafer region according to the area of a preset chip, wherein the initial chip regions have an initial preset length and an initial preset width;
and debugging the initial preset length and the initial preset width for a plurality of times according to the preset chip area and the process node so as to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area, wherein the chip areas have the preset chip area, and the number of the chip areas is greater than that of the preset chip areas.
2. The method for chip area typesetting according to claim 1, wherein the number of times of debugging processing is more than 2; the method for debugging processing each time comprises the following steps: adjusting an initial preset length and an initial preset width according to a preset chip area and a process node, and acquiring a debugging preset length and a debugging preset width, wherein the debugging preset length is different for each time, and the debugging preset width is different for each time; according to the preset debugging length and the preset debugging width, a plurality of rectangular debugging chip regions which are independent from each other are arranged in the preset wafer region, and the debugging chip regions have preset chip areas.
3. The method for chip area layout according to claim 2, wherein the method for performing debugging process for several times comprises: providing preset debugging times; and debugging for preset debugging times is carried out, and a preset debugging length and a preset debugging width corresponding to each debugging are obtained.
4. The method for chip area typesetting according to claim 2, wherein the method for performing debugging process for several times further comprises: providing a preset change percentage, a preset change function or a preset change quantity; the method for debugging processing each time further comprises the following steps: and changing the debugging preset length and the debugging preset width acquired at the n-1 th time according to the preset change percentage, the preset change function or the preset change amount to form the debugging preset length and the debugging preset width acquired at the n th time, wherein n is a natural number greater than or equal to 2.
5. The method for chip area layout according to claim 2, wherein the method for performing debugging processing on the initial preset length and the initial preset width for a plurality of times according to the preset chip area and the process node to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area comprises: according to the method, a plurality of mutually independent rectangular chip areas are arranged in a preset wafer area once the maximum number of debugging chip areas are arranged in a plurality of times of debugging processing, and the chip areas have debugging preset lengths and debugging preset widths corresponding to the debugging processing.
6. The method for chip area layout according to claim 5, wherein the method of performing debugging processing on the initial preset length and the initial preset width for several times according to the preset chip area and the process node to arrange a plurality of mutually independent rectangular chip areas in the preset wafer area further comprises: when the maximum and same number of debugging chip regions are arranged for multiple times in a plurality of times of debugging processing, a plurality of mutually independent rectangular chip regions are arranged in a preset wafer region according to the arrangement of the maximum number of debugging chip regions for one time, and the chip regions have debugging preset lengths and debugging preset widths corresponding to the debugging processing.
7. The method for chip area layout according to claim 1, further comprising: providing a preset cutting line width; arranging the initial chip areas according to the preset cutting channel width, wherein the preset cutting channel width is formed between the adjacent initial chip areas; and carrying out debugging treatment for a plurality of times according to the width of the cutting channel, wherein the preset cutting channel width is arranged between adjacent chip areas.
8. The method for chip area layout according to claim 1, wherein the predetermined wafer area includes a groove area and a wafer mark area, the groove area is used for fixing the wafer, the groove area is independent of the initial chip area, the groove area is independent of the chip area, the wafer mark area is used for forming a mark for distinguishing each wafer, the wafer mark area is independent of the initial chip area, and the wafer mark area is independent of the chip area.
9. The method for chip area typesetting according to claim 1, further comprising: providing a width of the edge region; arranging the initial chip areas according to the width of the edge areas, wherein the minimum distance between the edge of the initial chip area and the edge of the preset wafer area is larger than or equal to the width of the edge areas; and carrying out debugging processing for a plurality of times according to the width of the edge area, wherein the minimum distance between the edge of the chip area and the edge of the preset wafer area is greater than or equal to the width of the edge area.
CN202110506288.XA 2021-05-10 2021-05-10 Chip area typesetting method Pending CN115332227A (en)

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