CN111444668B - Method for carrying out layout wiring on transistors in array to be tested one by one - Google Patents
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Abstract
The invention relates to a method for carrying out layout wiring on transistors in an array to be tested one by one, which comprises a pretreatment process and a wiring process; determining to correspond the candidate device to the metal frame and determining the position of the candidate device through a pretreatment process; each pin of the device under test is routed through a routing process. The invention can ensure wiring quality and save time while processing and wiring the devices to be tested one by one.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method for carrying out layout wiring on transistors in an array to be tested one by one.
Background
With the rapid development of integrated circuit technology, integrated circuits enter into ultra-deep submicron age, so that the feature size of electronic devices is smaller and smaller, the scale of chips is larger and larger, more and more components can be integrated on a single chip, the complexity is rapidly increased, the wiring method in a layout can not meet the requirement of integrated circuit design by a manual design wiring method, and computer automatic wiring has occupied a larger proportion in layout design wiring.
The transistors integrated thereon may be different for the test chip, with these transistors forming the array under test, meaning that each device under test must be handled and routed individually, and processing time is saved while guaranteeing each routing quality, as DRC and LVS still need to be run at handling and routing.
Therefore, for the array to be tested composed of different transistors, it is highly desirable to provide a layout wiring method with high quality and high efficiency.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a method for carrying out layout wiring on transistors in an array to be tested one by one, which can meet the wiring requirements of the array to be tested formed by different transistors. In order to achieve the above purpose, the technical scheme of the invention is as follows:
providing a method for carrying out layout wiring on transistors in an array to be tested one by one, wherein the method comprises a pretreatment process and a wiring process;
the pretreatment process specifically comprises the following steps:
step (1): acquiring the positions of all candidate Devices (DUTs), and determining a device to be tested corresponding to each metal frame (frame) from the candidate devices;
step (2): finding out a metal polygon M1 corresponding to each pin of the device to be tested, and removing all other M1, all M2 and above metal polygons; the integrated circuit chip manufacturing comprises extremely complex technological processes, a plurality of process layers are involved in the layout design, and metal layers for wire connection in the layout are generally represented by M0, M1, M2 and the like from bottom to top; the metal polygon M1 and the metal polygon M2 refer to metal polygons on the M1 and the M2 respectively;
the wiring process specifically comprises the following steps:
step (3): selecting a device to be tested, taking a pin which is not subjected to wiring treatment in the device to be tested, and setting the initial value of a parameter x to be 0;
step (4): rectangular segmentation is carried out on the metal polygon M1 corresponding to the pin, so as to obtain a plurality of rectangles; when the values of x are different, the rectangular segmentation modes are different;
after rectangular segmentation, let x=x+1;
step (5): judging whether a rectangle meeting wiring conditions exists in the obtained rectangles: if yes, marking the rectangle meeting the wiring condition as the routable rectangle, then selecting one routable rectangle, and continuing the processing of the step (6); if not, performing rectangular segmentation judgment;
the rectangular segmentation judgment means that: judging whether the value of x is smaller than the frequency threshold, if yes, repeating the step (4), otherwise, failing the pin wiring, namely failing the wiring of the device to be tested, and executing the step (9);
step (6): judging whether wiring paths exist in the routable rectangle and the corresponding metal frame or not: if so, wiring the rectangle and the metal frame according to the wiring path, and processing in the step (8); if not, marking the rectangle as non-routable, and executing the step (7);
step (7): judging whether a routable rectangle exists: if yes, selecting a routable rectangle to repeatedly execute the step (6); if not, performing rectangular segmentation judgment;
step (8): checking whether all pins of the device to be tested are processed, if so, continuing to execute the step (9), otherwise, selecting an unprocessed pin in the device to be tested, resetting x to an initial value of 0, and processing in the step (4);
step (9): checking whether all the devices to be tested are processed, if yes, completing wiring, otherwise, selecting an untreated device to be tested, taking a pin which is not processed by wiring in the device to be tested, resetting x to be an initial value of 0, and processing in the step (4).
As a further improvement, in the step (1), if the positions of all candidate devices are known, the position information is directly imported; if the positions of the candidate devices are not known, searching and acquiring the positions of all the candidate devices.
As a further improvement, searching and acquiring the positions of all candidate devices specifically comprises the following steps:
step a: let GT polygon be a polygon with polysilicon layer (poly layer) and diffusion layer (diff layer), SD polygon be a polygon with diffusion layer but without polysilicon layer;
acquiring all GT polygons, and setting one GT polygon as G; the S polygon is an SD polygon connected with the left side of the G, and the D polygon is an SD polygon connected with the right side of the G;
step b: searching whether G is connected with metal, if G is connected with metal, processing in step c, otherwise, processing in step h;
step c: for G, checking whether an S polygon and a D polygon exist at the same time, if so, processing in the step D, otherwise, processing in the step h;
step d: checking whether the D polygon is connected with metal, if so, processing in the step f, otherwise, processing in the step e;
step e: check if the D polygon is connected with another GT polygon: if yes, replacing the D polygon of the G with the GT polygon, and checking again until the step D is finished; if not, the step h is carried out;
step f: check if the S polygon has metal attached: if so, adding the transistor (G, D, S) to a device list and proceeding to step h; if not, go to step g for treatment;
step g: check if the S polygon is connected with another GT polygon: if yes, replacing the S polygon of G with the GT polygon, and checking again in the step f; if not, the step h is carried out;
step h: checking whether all the GT polygons obtained in the step a are processed, if so, processing in the step i, otherwise, setting an unprocessed GT polygon as G, and repeating the processing in the step b;
step i: for the obtained equipment list, taking a transistor in the equipment list to perform the processing of the step j;
step j: identifying whether the implanted impurity (implant) of the transistor is an N-type impurity or a P-type impurity, and identifying whether the well (well) of the transistor is a P-type well or an N-type well; then, it is determined whether or not an impurity region opposite to the implanted impurity exists in the same well:
if so, locating an impurity region opposite to the injected impurity in the same well, identifying a metal polygon B, adding the transistor (G, D, S, B) to a candidate list, and taking the transistor (G, D, S, B) as a candidate device, wherein the transistor (G, D, S, B) has four pins, namely a pin G, a pin D, a pin S and a pin B;
if not, directly adding the transistor (G, D, S) to a candidate list, wherein the transistor (G, D, S) has three pins, namely a pin G, a pin D and a pin S, as candidate devices;
step k: checking whether the transistors in the equipment list are processed, if so, completing the search of the candidate devices, otherwise, taking an unprocessed transistor to step j and repeating the processing.
As a further improvement, in the step (4), the rectangular division of the metal polygon M1 means: when three adjacent vertexes form a convex structure, two adjacent vertexes are taken as two vertexes of a rectangle, the rectangle is divided from the metal polygon and added into a rectangle list until the metal polygon is divided into a plurality of rectangles.
As a further improvement, in the rectangular division judgment, the threshold value of the number of times of x is 2;
when the value of x is 0, the rotation direction is set clockwise when the metal polygon M1 is rectangular divided, and when the value of x is 1, the rotation direction is set counterclockwise when the metal polygon M1 is rectangular divided; and for the same metal polygon M1, segmentation starts from the same vertex.
As a further improvement, in the step (5), the rectangle satisfying the wiring condition is a rectangle having an area exceeding a threshold value, and the rectangle having an area smaller than the threshold value cannot be wired.
As a further improvement, in the step (6), it is determined whether or not a wiring path exists in the rectangle and the corresponding metal frame, specifically including the steps of:
step m: searching paths from the rectangle to the corresponding metal frame to obtain a plurality of paths, and marking the paths as unprocessed;
step n: selecting a shortest path from the unprocessed paths;
step o: judging the shortest path:
if the shortest path is an unassigned path, indicating that wiring can be performed, the shortest path being the wiring path, and marking the path as assigned to the pin;
if the shortest path is an allocated path, judging whether an unprocessed path exists, if so, repeating the processing until the step n, and if not, judging that the rectangle and the corresponding metal frame do not have wiring paths.
As a further improvement, in the step (1), each metal frame is defined as a corresponding device under test, and among the candidate devices that can be selected, the candidate device that is located within the range of the metal frame and closest to the center of the metal frame (each metal frame corresponds to only one device under test, and each device under test corresponds to only one metal frame).
As a further improvement, for the case of wiring failure of the metal frame and the corresponding device under test, marking all the devices under test which have failed in wiring as non-selectable, and judging whether there are any candidate devices which can be selected for all the corresponding metal frames, respectively:
if the metal frame has no candidate device which can be selected, the wiring fails;
if the metal frame has a candidate device which can be selected, determining a device to be tested for the metal frame again; then, for all newly determined devices under test, go to step (2) for re-execution.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention carries out pretreatment and wiring on the devices to be tested one by one, can meet the wiring requirements of the arrays to be tested consisting of different transistors, and ensures the wiring quality.
2. When the method and the device are used for preprocessing before wiring each pin of the device to be tested, only the metal polygon M1 corresponding to each pin is reserved for subsequent wiring operation, and time is saved.
Drawings
FIG. 1 is a schematic diagram of finding and acquiring all candidate device locations.
Fig. 2 is a schematic flow chart of the wiring process in the present invention.
Fig. 3 is a schematic diagram of rectangular segmentation of a metal polygon.
FIG. 4 is a diagram of an embodiment of a Device Under Test (DUT).
Fig. 5 is a diagram of an embodiment of a metal frame (frame).
Fig. 6 is a diagram of an embodiment of a device under test and a metal frame after routing.
Detailed Description
The invention is described in further detail below with reference to the attached drawings and detailed description:
a method for carrying out layout wiring on transistors in an array to be tested one by one comprises a pretreatment process and a wiring process; the method can ensure wiring quality and save time while processing and wiring the devices to be tested one by one. The following will specifically describe.
The pretreatment process specifically comprises the following steps:
step (1): if the locations of all candidate Devices (DUTs) are known, directly importing location information; if the positions of the candidate devices are not known, searching and acquiring the positions of all the candidate devices. After the positions of all candidate devices are obtained, determining a device to be tested corresponding to each metal frame (frame) from the candidate devices, wherein the device to be tested is a candidate device which is positioned in the range of the metal frame and is closest to the center of the metal frame in the selectable candidate devices; each metal frame corresponds to only 1 device to be tested, and each device to be tested corresponds to only 1 metal frame.
The searching and obtaining the position of the candidate device, as shown in fig. 1, specifically includes the following steps:
step a: let GT polygon be a polygon with polysilicon layer (poly layer) and diffusion layer (diff layer), SD polygon be a polygon with diffusion layer but without polysilicon layer;
acquiring all GT polygons, and setting one GT polygon as G; the S polygon is an SD polygon connected with the left side of the G, and the D polygon is an SD polygon connected with the right side of the G;
step b: searching whether G is connected with metal, if G is connected with metal, processing in step c, otherwise, processing in step h;
step c: for G, checking whether an S polygon and a D polygon exist at the same time, if so, processing in the step D, otherwise, processing in the step h;
step d: checking whether the D polygon is connected with metal, if so, processing in the step f, otherwise, processing in the step e;
step e: check if the D polygon is connected with another GT polygon: if yes, replacing the D polygon of the G with the GT polygon, and checking again until the step D is finished; if not, the step h is carried out;
step f: check if the S polygon has metal attached: if so, adding the transistor (G, D, S) to a device list and proceeding to step h; if not, go to step g for treatment;
step g: check if the S polygon is connected with another GT polygon: if yes, replacing the S polygon of G with the GT polygon, and checking again in the step f; if not, the step h is carried out;
step h: checking whether all the GT polygons obtained in the step a are processed, if so, processing in the step i, otherwise, setting an unprocessed GT polygon as G, and repeating the processing in the step b;
step i: for the obtained equipment list, taking a transistor in the equipment list to perform the processing of the step j;
step j: identifying whether the implanted impurity (implant) of the transistor is an N-type impurity or a P-type impurity, and identifying whether the well (well) of the transistor is a P-type well or an N-type well; then, it is determined whether or not an impurity region opposite to the implanted impurity exists in the same well:
if so, locating an impurity region opposite to the injected impurity in the same well, identifying a metal polygon B, adding the transistor (G, D, S, B) to a candidate list, and taking the transistor (G, D, S, B) as a candidate device, wherein the transistor (G, D, S, B) has four pins, namely a pin G, a pin D, a pin S and a pin B;
if not, directly adding the transistor (G, D, S) to a candidate list, wherein the transistor (G, D, S) has three pins, namely a pin G, a pin D and a pin S, as candidate devices;
step k: checking whether the transistors in the equipment list are processed, if so, completing the search of the candidate devices, otherwise, taking an unprocessed transistor to step j and repeating the processing.
Step (2): finding out the metal polygon M1 corresponding to each pin of the device to be tested, and removing other M1 and all M2 and above metal polygons.
As shown in fig. 2, the wiring process specifically includes the steps of:
step (3): selecting a device to be tested, taking a pin which is not subjected to wiring treatment in the device to be tested, and setting the initial value of x as 0.
Step (4): rectangular segmentation is carried out on the metal polygon M1 corresponding to the pin, so as to obtain a plurality of rectangles; when the values of x are different, the rectangular segmentation modes are different; after the rectangular division, let x=x+1.
The rectangular division of the metal polygon M1 refers to: as shown in fig. 3, when the vertices are traversed in the rotation direction starting from one vertex of the metal polygon and the adjacent three vertices form a convex structure, two of the adjacent vertices are used as two vertices of a rectangle, the rectangle is divided from the metal polygon and added into a rectangle list until the metal polygon is divided into a plurality of rectangles. When the value of x is 0, the rotation direction is set clockwise when the metal polygon M1 is rectangular divided, and when the value of x is 1, the rotation direction is set counterclockwise when the metal polygon M1 is rectangular divided; and for the same metal polygon M1, segmentation starts from the same vertex.
Step (5): judging whether a rectangle meeting wiring conditions exists in the obtained rectangles: if yes, marking the rectangle meeting the wiring condition as the routable rectangle, then selecting one routable rectangle, and continuing the processing of the step (6); if not, rectangular segmentation judgment is performed.
The rectangle satisfying the wiring condition is a rectangle having an area exceeding a threshold value, and a rectangle having an area smaller than the threshold value cannot be wired.
The rectangular segmentation judgment means that: and (3) judging whether the value of x is smaller than the frequency threshold, if so, repeating the step (4), otherwise, failing the pin wiring, namely failing the wiring of the device to be tested, and repeating the step (9).
Step (6): judging whether wiring paths exist in the routable rectangle and the corresponding metal frame or not: if so, wiring the rectangle and the metal frame through M2 according to the wiring path, and proceeding to the step (8); if not, marking the rectangle as non-routable, and proceeding to step (7).
The method for judging whether the rectangle and the corresponding metal frame have wiring paths specifically comprises the following steps:
step m: searching paths from the rectangle to the corresponding metal frame to obtain a plurality of paths, and marking the paths as unprocessed;
step n: selecting a shortest path from the unprocessed paths;
step o: judging the shortest path: if the shortest path is an unassigned path, indicating that wiring can be performed, the shortest path being the wiring path, and marking the path as assigned to the pin; if the shortest path is an allocated path, judging whether an unprocessed path exists, if so, repeating the processing until the step n, and if not, judging that the rectangle and the corresponding metal frame do not have wiring paths.
Step (7): judging whether a routable rectangle exists: if yes, selecting a routable rectangle to repeatedly execute the step (6); if not, rectangular segmentation judgment is performed.
Step (8): checking whether all pins of the device to be tested are processed, if so, continuing to execute the step (9), otherwise, selecting an unprocessed pin in the device to be tested, resetting x to an initial value of 0, and processing in the step (4).
Step (9): checking whether all the devices to be tested are processed, if yes, completing wiring, otherwise, selecting an untreated device to be tested, taking a pin which is not processed by wiring in the device to be tested, resetting x to be an initial value of 0, and processing in the step (4).
In the method for carrying out layout wiring on the transistors in the array to be tested one by one, for the condition that the metal frame and the corresponding device to be tested are failed in wiring, marking all the devices to be tested which are failed in wiring as non-selectable, and judging whether selectable candidate devices exist for all the corresponding metal frames or not: if the metal frame has no candidate device which can be selected, the wiring fails; if the metal frame has a candidate device which can be selected, determining a device to be tested for the metal frame again; then, for all newly determined devices under test, go to step (2) for re-execution.
In the area A1 in fig. 4, a Device Under Test (DUT) is located, in fig. 5, a metal frame (frame), and after wiring is performed by using the method of performing layout wiring on transistors in the array under test one by one, the device under test and the metal frame after wiring are shown in the area A2 in fig. 6.
The method comprises the steps of completing time realization of layout wiring by using a to-be-tested array consisting of 128×128 different transistors and adopting the method of carrying out layout wiring on the transistors in the to-be-tested array one by one: the pretreatment time is not more than 3 minutes, the wiring time is not more than 2 minutes, the whole layout wiring time is not more than 5 minutes, and excellent high efficiency is experienced.
Finally, it should be noted that the above list is only specific embodiments of the present invention. Obviously, the invention is not limited to the above embodiments, but many variations are possible. All modifications directly derived or suggested to one skilled in the art from the present disclosure should be considered as being within the scope of the present invention.
Claims (9)
1. A method for carrying out layout wiring on transistors in an array to be tested one by one is characterized in that,
the method comprises a pretreatment process and a wiring process;
the pretreatment process specifically comprises the following steps:
step (1): acquiring the positions of all candidate devices, and determining the device to be tested corresponding to each metal frame from the candidate devices;
step (2): finding out a metal polygon M1 corresponding to each pin of the device to be tested, and removing all other metal polygons M1, and all M2 and above metal polygons;
the wiring process specifically comprises the following steps:
step (3): selecting a device to be tested, taking a pin which is not subjected to wiring treatment in the device to be tested, and setting the initial value of a parameter x to be 0; step (4): rectangular segmentation is carried out on the metal polygon M1 corresponding to the pin, so as to obtain a plurality of rectangles; when the values of x are different, the rectangular segmentation modes are different;
after rectangular segmentation, let x=x+1;
step (5): judging whether a rectangle meeting wiring conditions exists in the obtained rectangles: if yes, marking the rectangle meeting the wiring condition as the routable rectangle, then selecting one routable rectangle, and continuing the processing of the step (6); if not, performing rectangular segmentation judgment;
the rectangular segmentation judgment means that: judging whether the value of x is smaller than the frequency threshold, if yes, repeating the step (4), otherwise, failing the pin wiring, namely failing the wiring of the device to be tested, and executing the step (9);
step (6): judging whether wiring paths exist in the routable rectangle and the corresponding metal frame or not: if so, wiring the rectangle and the metal frame according to the wiring path, and processing in the step (8); if not, marking the rectangle as non-routable, and executing the step (7); step (7): judging whether a routable rectangle exists: if yes, selecting a routable rectangle to repeatedly execute the step (6); if not, performing rectangular segmentation judgment;
step (8): checking whether all pins of the device to be tested are processed, if so, continuing to execute the step (9), otherwise, selecting an unprocessed pin in the device to be tested, resetting x to an initial value of 0, and processing in the step (4);
step (9): checking whether all the devices to be tested are processed, if yes, completing wiring, otherwise, selecting an untreated device to be tested, taking a pin which is not processed by wiring in the device to be tested, resetting x to be an initial value of 0, and processing in the step (4).
2. The method for layout wiring of transistors in an array to be tested one by one according to claim 1, wherein in the step (1), if the positions of all candidate devices are known, the position information is directly imported; if the positions of the candidate devices are not known, searching and acquiring the positions of all the candidate devices.
3. The method for layout wiring of transistors in an array to be tested one by one according to claim 2, wherein the steps of searching and obtaining the positions of all candidate devices comprise the following steps:
step a: let GT polygon be a polygon with polysilicon layer and diffusion layer, SD polygon be a polygon with diffusion layer but without polysilicon layer;
acquiring all GT polygons, and setting one GT polygon as G; the S polygon is an SD polygon connected with the left side of the G, and the D polygon is an SD polygon connected with the right side of the G;
step b: searching whether G is connected with metal, if G is connected with metal, processing in step c, otherwise, processing in step h;
step c: for G, checking whether an S polygon and a D polygon exist at the same time, if so, processing in the step D, otherwise, processing in the step h;
step d: checking whether the D polygon is connected with metal, if so, processing in the step f, otherwise, processing in the step e;
step e: check if the D polygon is connected with another GT polygon: if yes, replacing the D polygon of the G with the GT polygon, and checking again until the step D is finished; if not, the step h is carried out;
step f: check if the S polygon has metal attached: if yes, adding the transistor GDS to the equipment list, and processing in the step h; if not, go to step g for treatment;
step g: check if the S polygon is connected with another GT polygon: if yes, replacing the S polygon of G with the GT polygon, and checking again in the step f; if not, the step h is carried out;
step h: checking whether all the GT polygons obtained in the step a are processed, if so, processing in the step i, otherwise, setting an unprocessed GT polygon as G, and repeating the processing in the step b;
step i: for the obtained equipment list, taking a transistor in the equipment list to perform the processing of the step j;
step j: identifying whether the implanted impurity of the transistor is an N-type impurity or a P-type impurity, and identifying whether the well of the transistor is a P-type well or an N-type well; then, it is judged whether or not an impurity region opposite to the implanted impurity is present in the well of the transistor:
if so, locating an impurity region opposite to the injected impurity in the well of the transistor, identifying a metal polygon B, adding a transistor GDSB to the candidate list, wherein the transistor GDSB has four pins, namely a pin G, a pin D, a pin S and a pin B, as candidate devices;
if not, directly adding a transistor GDS to the candidate list, wherein the transistor GDS is provided with three pins, namely a pin G, a pin D and a pin S, as candidate devices;
step k: checking whether the transistors in the equipment list are processed, if so, completing the search of the candidate devices, otherwise, taking an unprocessed transistor to step j and repeating the processing.
4. The method for layout wiring of transistors in an array to be tested one by one according to claim 1, wherein in the step (4), the rectangular division of the metal polygon M1 means: when three adjacent vertexes form a convex structure, two adjacent vertexes are taken as two vertexes of a rectangle, the rectangle is divided from the metal polygon and added into a rectangle list until the metal polygon is divided into a plurality of rectangles.
5. The method for layout wiring of transistors in an array to be tested one by one according to claim 4, wherein in the rectangular segmentation judgment, the number of times of x is 2;
when the value of x is 0, the rotation direction is set clockwise when the metal polygon M1 is rectangular divided, and when the value of x is 1, the rotation direction is set counterclockwise when the metal polygon M1 is rectangular divided; and for the same metal polygon M1, segmentation starts from the same vertex.
6. The method for individually routing the layout of the transistors in the array to be tested according to claim 1, wherein in the step (5), the rectangle meeting the routing condition is a rectangle with an area exceeding a threshold value, and the rectangle with an area smaller than the threshold value cannot be routed.
7. The method for layout wiring of transistors in an array to be tested one by one according to claim 1, wherein in the step (6), it is determined whether a wiring path exists between a rectangle and a corresponding metal frame, specifically comprising the following steps:
step m: searching paths from the rectangle to the corresponding metal frame to obtain a plurality of paths, and marking the paths as unprocessed;
step n: selecting a shortest path from the unprocessed paths;
step o: judging the shortest path:
if the shortest path is an unassigned path, indicating that wiring can be performed, the shortest path being the wiring path, and marking the path as assigned to the pin;
if the shortest path is an allocated path, judging whether an unprocessed path exists, if so, repeating the processing until the step n, and if not, judging that the rectangle and the corresponding metal frame do not have wiring paths.
8. The method according to claim 1, wherein in the step (1), each metal frame corresponds to a device under test, and each device under test corresponds to only one metal frame, and the device under test is a candidate device that is located within the range of the metal frame and closest to the center of the metal frame, among the candidate devices that can be selected.
9. The method for individually performing layout wiring on transistors in an array to be tested according to claim 8, wherein for the case that the metal frame and the corresponding device to be tested fail in wiring, all devices to be tested that fail in wiring are marked as being unable to be selected, and whether there are any candidate devices that can be selected is determined for all corresponding metal frames, respectively:
if the metal frame has no candidate device which can be selected, the wiring fails;
if the metal frame has a candidate device which can be selected, determining a device to be tested for the metal frame again; then, for all newly determined devices under test, go to step (2) for re-execution.
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