CN111444668A - Method for carrying out layout wiring on transistors in array to be tested one by one - Google Patents
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Abstract
The invention relates to a method for carrying out layout wiring on transistors in an array to be tested one by one, which comprises a preprocessing process and a wiring process; determining the candidate device to correspond to the metal frame through a preprocessing process and determining the position of the candidate device; and wiring each pin of the device to be tested through a wiring process. The invention can ensure the wiring quality and save time while processing and wiring the devices to be tested one by one.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method for carrying out layout wiring on transistors in an array to be tested one by one.
Background
With the rapid development of integrated circuit technology, integrated circuits enter an ultra-deep submicron era, so that the characteristic size of electronic devices is smaller and smaller, the scale of chips is larger and larger, more and more components can be integrated on a single chip, the complexity is increased sharply, the wiring method in a layout cannot meet the design requirement of the integrated circuits by a manual wiring method, and the automatic wiring of a computer occupies a larger and larger proportion in layout design wiring.
The transistors integrated on the test chip may be different, and the array under test is composed of these transistors, meaning that each device under test must be processed and wired individually, and processing time is saved while ensuring the quality of each wire, since it is still necessary to run DRC and L VS while processing and wiring.
Therefore, it is urgently needed to provide a high-quality and efficient layout wiring method for an array to be tested composed of different transistors.
Disclosure of Invention
The invention mainly aims to overcome the defects in the prior art and provide a method for carrying out layout wiring on transistors in an array to be tested one by one, so that the wiring requirement of the array to be tested consisting of different transistors can be met. In order to achieve the purpose, the technical scheme of the invention is as follows:
the method for carrying out layout wiring on transistors in an array to be tested one by one comprises a preprocessing process and a wiring process;
the pretreatment process specifically comprises the following steps:
step (1): acquiring the positions of all candidate Devices (DUT), and determining the device to be tested corresponding to each metal frame (frame) from the candidate devices;
step (2): finding out a metal polygon M1 corresponding to each pin of the device to be tested, and removing all other metal polygons M1, all metal polygons M2 and above; the manufacturing of the integrated circuit chip comprises an extremely complex process, a plurality of process layers are involved in layout design, and metal layers for lead connection in the layout are generally represented by M0, M1, M2 and the like from bottom to top; the metal polygons M1 and M2 are metal polygons on M1 and M2, respectively;
the wiring process specifically comprises the following steps:
and (3): selecting a device to be tested, taking a pin which is not subjected to wiring processing in the device to be tested, and setting the initial value of the parameter x as 0;
and (4): performing rectangular segmentation on the metal polygon M1 corresponding to the pin to obtain a plurality of rectangles; when the value of x is different, the rectangular division modes are different;
after rectangular division, let x be x + 1;
and (5): judging whether the obtained rectangles have rectangles meeting wiring conditions: if yes, marking the rectangle meeting the wiring condition as a routable rectangle, then selecting one routable rectangle, and continuing the processing of the step (6); if not, performing rectangle segmentation judgment;
the rectangle division judgment means: judging whether the value of x is smaller than a frequency threshold value, if so, repeating the step (4), otherwise, failing to wire the pin, namely failing to wire the device to be tested, and executing the step (9);
and (6): judging whether the routable rectangle and the corresponding metal frame have a routing path: if yes, wiring the rectangle and the metal frame according to the wiring path, and performing the step (8); if not, marking the rectangle as not-routable, and executing the step (7);
and (7): judging whether a routable rectangle exists: if yes, selecting a rectangle capable of being wired, and repeating the step (6); if not, performing rectangle segmentation judgment;
and (8): checking whether all pins of the device to be tested are processed, if so, continuing to execute the step (9), otherwise, selecting an unprocessed pin in the device to be tested, and resetting x to an initial value 0 until the step (4) is processed;
and (9): and (4) checking whether all the devices to be tested are processed, if so, finishing wiring, otherwise, selecting an unprocessed device to be tested, taking an unprocessed pin in the device to be tested, and resetting x to an initial value 0 until the step (4) is processed.
As a further improvement, in the step (1), if the positions of all candidate devices are known, directly importing position information; and if the positions of the candidate devices are unknown, searching and acquiring the positions of all the candidate devices.
As a further improvement, the finding and obtaining the positions of all candidate devices specifically includes the following steps:
step a: let GT polygon be a polygon with a polysilicon layer (poly layer) and a diffusion layer (diff layer), SD polygon be a polygon with a diffusion layer but no polysilicon layer;
acquiring all GT polygons, and randomly selecting one GT polygon as G; setting the S polygon as the SD polygon connected with the left side of the G, and setting the D polygon as the SD polygon connected with the right side of the G;
step b: searching whether the G is connected with the metal, if the G is connected with the metal, processing to the step c, and otherwise, processing to the step h;
step c: for G, checking whether an S polygon and a D polygon exist at the same time, if so, processing to step D, otherwise, processing to step h;
step d: checking whether the D polygon is connected with metal, if so, processing in the step f, and otherwise, processing in the step e;
step e: check if the D polygon has another GT polygon connected: if yes, replacing the D polygon of G with the GT polygon, and rechecking in step D; if not, processing in the step h;
step f: check if the S polygon has metal attached: if yes, adding the transistor (G, D, S) to the device list, and processing to the step h; if not, processing in the step g;
step g: check if this S polygon is connected to another GT polygon: if yes, replacing the S polygon of G with the GT polygon, and rechecking in step f; if not, processing in the step h;
step h: checking whether the GT polygons obtained in the step a are processed, if so, processing in the step i, otherwise, setting an unprocessed GT polygon as G, and repeating the step b;
step i: for the obtained equipment list, taking a transistor in the equipment list to carry out the processing of the step j;
step j: firstly, identifying whether an implanted impurity (implant) of the transistor is an N-type impurity or a P-type impurity, and then identifying whether a well (well) of the transistor is a P-type well or an N-type well; then, it is determined whether an impurity region opposite to the implanted impurity exists in the same well:
if so, locating an impurity region opposite to the impurity implantation in the same well, identifying a metal polygon B, adding the transistor (G, D, S, B) to a candidate list as a candidate device, wherein the transistor (G, D, S, B) has four pins, namely a pin G, a pin D, a pin S and a pin B;
if not, directly adding the transistor (G, D, S) to a candidate list as a candidate device, wherein the transistor (G, D, S) has three pins, namely a pin G, a pin D and a pin S;
step k: and (e) checking whether all the transistors in the equipment list are processed, if so, finishing the search of the candidate device, and otherwise, taking an unprocessed transistor to the step j for repeated processing.
As a further improvement, in the step (4), the rectangular division of the metal polygon M1 refers to: and traversing the vertexes along the rotation direction from one vertex of the metal polygon, and when three adjacent vertexes form a convex structure, taking two adjacent vertexes as two vertexes of a rectangle, dividing the rectangle from the metal polygon and adding the rectangle into a rectangle list until the metal polygon is divided into a plurality of rectangles.
As a further improvement, in the rectangular division judgment, the threshold of the number of times of x is 2;
when the value of x is 0, the rotation direction is set to be clockwise when the metal polygon M1 is rectangularly divided, and when the value of x is 1, the rotation direction is set to be counterclockwise when the metal polygon M1 is rectangularly divided; and starting the segmentation from the same vertex for the same metal polygon M1.
As a further improvement, in the step (5), the rectangle satisfying the wiring condition is a rectangle having an area exceeding a threshold value, and a rectangle having an area smaller than the threshold value cannot be wired.
As a further improvement, in the step (6), judging whether the rectangular shape and the corresponding metal frame have the wiring path specifically includes the following steps:
step m: exploring paths from the rectangle to the corresponding metal frame to obtain a plurality of paths which are respectively marked as unprocessed;
step n: selecting a shortest path from the unprocessed paths;
step o: and (3) judging the shortest path:
if the shortest path is an unallocated path, it is indicated that routing can be performed, the shortest path is used as a routing path, and the routing path is marked as being allocated to the pin;
if the shortest path is an allocated path, judging whether an unprocessed path still exists, if so, repeating the step n, and if not, judging that the rectangular and the corresponding metal frame do not have a wiring path.
As a further improvement, in step (1), the corresponding device under test determined by each metal frame is a candidate device located in the range of the metal frame and closest to the center of the metal frame, among the selectable candidate devices (each metal frame corresponds to only one device under test, and each device under test corresponds to only one metal frame).
As a further improvement, for the case of failed wiring of the metal frame and the corresponding device to be tested, all devices to be tested with failed wiring are marked as being unselectable, and whether there are still selectable candidate devices is judged for all corresponding metal frames:
if the metal frame has no selectable candidate device, wiring fails;
if the metal frame has selectable candidate devices, determining a device to be tested for the metal frame again; and then, for all newly determined devices to be tested, the step (2) is executed again.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention preprocesses and wires the device to be tested one by one, can meet the wiring requirement of the array to be tested composed of different transistors, and ensures the wiring quality.
2. When the method is used for preprocessing each pin of the device to be tested before wiring, only the metal polygon M1 corresponding to each pin is reserved for subsequent wiring operation, so that the time is saved.
Drawings
Fig. 1 is a schematic diagram of finding and acquiring all candidate device positions.
Fig. 2 is a flow chart illustrating a wiring process in the present invention.
Fig. 3 is a schematic diagram of rectangular division of a metal polygon.
FIG. 4 is a diagram of an embodiment of a Device Under Test (DUT).
Fig. 5 is a diagram of an embodiment of a metal frame (frame).
FIG. 6 is a diagram of an embodiment of a device under test and a metal frame after wiring.
Detailed Description
The invention is described in further detail below with reference to the following detailed description and accompanying drawings:
a method for carrying out layout wiring on transistors in an array to be tested one by one comprises a preprocessing process and a wiring process; the method can ensure the wiring quality and save time while processing and wiring the devices to be tested one by one. As will be described in detail below.
The pretreatment process specifically comprises the following steps:
step (1): if the positions of all candidate Devices (DUT) are known, directly importing position information; and if the positions of the candidate devices are unknown, searching and acquiring the positions of all the candidate devices. After the positions of all candidate devices are obtained, determining a device to be tested corresponding to each metal frame (frame) from the candidate devices, wherein the device to be tested is the candidate device which is positioned in the range of the metal frame and is closest to the center of the metal frame in the selectable candidate devices; each metal frame only corresponds to 1 device to be tested, and each device to be tested only corresponds to 1 metal frame.
As shown in fig. 1, the finding and obtaining of the position of the candidate device specifically includes the following steps:
step a: let GT polygon be a polygon with a polysilicon layer (poly layer) and a diffusion layer (diff layer), SD polygon be a polygon with a diffusion layer but no polysilicon layer;
acquiring all GT polygons, and randomly selecting one GT polygon as G; setting the S polygon as the SD polygon connected with the left side of the G, and setting the D polygon as the SD polygon connected with the right side of the G;
step b: searching whether the G is connected with the metal, if the G is connected with the metal, processing to the step c, and otherwise, processing to the step h;
step c: for G, checking whether an S polygon and a D polygon exist at the same time, if so, processing to step D, otherwise, processing to step h;
step d: checking whether the D polygon is connected with metal, if so, processing in the step f, and otherwise, processing in the step e;
step e: check if the D polygon has another GT polygon connected: if yes, replacing the D polygon of G with the GT polygon, and rechecking in step D; if not, processing in the step h;
step f: check if the S polygon has metal attached: if yes, adding the transistor (G, D, S) to the device list, and processing to the step h; if not, processing in the step g;
step g: check if this S polygon is connected to another GT polygon: if yes, replacing the S polygon of G with the GT polygon, and rechecking in step f; if not, processing in the step h;
step h: checking whether the GT polygons obtained in the step a are processed, if so, processing in the step i, otherwise, setting an unprocessed GT polygon as G, and repeating the step b;
step i: for the obtained equipment list, taking a transistor in the equipment list to carry out the processing of the step j;
step j: firstly, identifying whether an implanted impurity (implant) of the transistor is an N-type impurity or a P-type impurity, and then identifying whether a well (well) of the transistor is a P-type well or an N-type well; then, it is determined whether an impurity region opposite to the implanted impurity exists in the same well:
if so, locating an impurity region opposite to the impurity implantation in the same well, identifying a metal polygon B, adding the transistor (G, D, S, B) to a candidate list as a candidate device, wherein the transistor (G, D, S, B) has four pins, namely a pin G, a pin D, a pin S and a pin B;
if not, directly adding the transistor (G, D, S) to a candidate list as a candidate device, wherein the transistor (G, D, S) has three pins, namely a pin G, a pin D and a pin S;
step k: and (e) checking whether all the transistors in the equipment list are processed, if so, finishing the search of the candidate device, and otherwise, taking an unprocessed transistor to the step j for repeated processing.
Step (2): and finding the metal polygon M1 corresponding to each pin of the device to be tested, and removing other M1 and all M2 and above metal polygons.
As shown in fig. 2, the wiring process specifically includes the following steps:
and (3): selecting a device to be tested, taking a pin which is not subjected to wiring processing in the device to be tested, and setting the initial value of x to be 0.
And (4): performing rectangular segmentation on the metal polygon M1 corresponding to the pin to obtain a plurality of rectangles; when the value of x is different, the rectangular division modes are different; after the rectangular division, let x be x + 1.
The rectangular division of the metal polygon M1 means that: as shown in fig. 3, from one vertex of the metal polygon, traversing the vertices along the rotation direction, and when three adjacent vertices form a convex structure, taking two adjacent vertices as two vertices of a rectangle, dividing the rectangle from the metal polygon and adding the rectangle into a rectangle list until the metal polygon is divided into a plurality of rectangles. When the value of x is 0, the rotation direction is set to be clockwise when the metal polygon M1 is rectangularly divided, and when the value of x is 1, the rotation direction is set to be counterclockwise when the metal polygon M1 is rectangularly divided; and starting the segmentation from the same vertex for the same metal polygon M1.
And (5): judging whether the obtained rectangles have rectangles meeting wiring conditions: if yes, marking the rectangle meeting the wiring condition as a routable rectangle, then selecting one routable rectangle, and continuing the processing of the step (6); if not, the rectangle division judgment is carried out.
The rectangle satisfying the wiring condition is a rectangle having an area exceeding a threshold, and a rectangle having an area smaller than the threshold cannot be wired.
The rectangle division judgment means: and (4) judging whether the value of x is smaller than a frequency threshold value, if so, repeating the step (4), otherwise, failing to wire the pin, namely, failing to wire the device to be tested, and executing the step (9).
And (6): judging whether the routable rectangle and the corresponding metal frame have a routing path: if the rectangular frame exists, the rectangular frame and the metal frame are wired through M2 according to the wiring path, and the step (8) is carried out; if not, the rectangle is marked as not routable and the process proceeds to step (7).
The method for judging whether the rectangular and the corresponding metal frame have the wiring path specifically comprises the following steps:
step m: exploring paths from the rectangle to the corresponding metal frame to obtain a plurality of paths which are respectively marked as unprocessed;
step n: selecting a shortest path from the unprocessed paths;
step o: and (3) judging the shortest path: if the shortest path is an unallocated path, it is indicated that routing can be performed, the shortest path is used as a routing path, and the routing path is marked as being allocated to the pin; if the shortest path is an allocated path, judging whether an unprocessed path still exists, if so, repeating the step n, and if not, judging that the rectangular and the corresponding metal frame do not have a wiring path.
And (7): judging whether a routable rectangle exists: if yes, selecting a rectangle capable of being wired, and repeating the step (6); if not, the rectangle division judgment is carried out.
And (8): checking whether all pins of the device to be tested are processed, if so, continuing to execute the step (9), otherwise, selecting an unprocessed pin in the device to be tested, and resetting x to an initial value 0 until the step (4) is processed.
And (9): and (4) checking whether all the devices to be tested are processed, if so, finishing wiring, otherwise, selecting an unprocessed device to be tested, taking an unprocessed pin in the device to be tested, and resetting x to an initial value 0 until the step (4) is processed.
In the method for performing layout wiring on the transistors in the array to be tested one by one, for the condition that the metal frame and the corresponding device to be tested fail to be wired, all the devices to be tested which fail to be wired are marked as being unselectable, and whether selectable candidate devices exist or not is judged for all the corresponding metal frames respectively: if the metal frame has no selectable candidate device, wiring fails; if the metal frame has selectable candidate devices, determining a device to be tested for the metal frame again; and then, for all newly determined devices to be tested, the step (2) is executed again.
In the area a1 in fig. 4, a Device Under Test (DUT) is located, and in fig. 5, a metal frame (frame) is located, and after the layout wiring method is used for the transistors in the array under test one by one, the device under test and the metal frame shown in the area a2 in fig. 6 are obtained.
The method for completing the layout wiring by using the array to be tested consisting of 128 × 128 different transistors and the method for performing the layout wiring on the transistors in the array to be tested one by one is used, the preprocessing time is not more than 3 minutes, the wiring time is not more than 2 minutes, the wiring time of the whole layout is not more than 5 minutes, and the excellent high efficiency is experienced.
Finally, it should be noted that the above-mentioned list is only a specific embodiment of the present invention. It is obvious that the present invention is not limited to the above embodiments, but many variations are possible. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the present invention are to be considered within the scope of the invention.
Claims (9)
1. A method for carrying out layout wiring on transistors in an array to be tested one by one is characterized by comprising a preprocessing process and a wiring process;
the pretreatment process specifically comprises the following steps:
step (1): obtaining the positions of all candidate devices, and determining the device to be tested corresponding to each metal frame from the candidate devices;
step (2): finding out a metal polygon M1 corresponding to each pin of the device to be tested, and removing all other metal polygons M1, and all metal polygons M2 and above;
the wiring process specifically comprises the following steps:
and (3): selecting a device to be tested, taking a pin which is not subjected to wiring processing in the device to be tested, and setting the initial value of the parameter x as 0;
and (4): performing rectangular segmentation on the metal polygon M1 corresponding to the pin to obtain a plurality of rectangles; when the value of x is different, the rectangular division modes are different;
after rectangular division, let x be x + 1;
and (5): judging whether the obtained rectangles have rectangles meeting wiring conditions: if yes, marking the rectangle meeting the wiring condition as a routable rectangle, then selecting one routable rectangle, and continuing the processing of the step (6); if not, performing rectangle segmentation judgment;
the rectangle division judgment means: judging whether the value of x is smaller than a frequency threshold value, if so, repeating the step (4), otherwise, failing to wire the pin, namely failing to wire the device to be tested, and executing the step (9);
and (6): judging whether the routable rectangle and the corresponding metal frame have a routing path: if yes, wiring the rectangle and the metal frame according to the wiring path, and performing the step (8); if not, marking the rectangle as not-routable, and executing the step (7);
and (7): judging whether a routable rectangle exists: if yes, selecting a rectangle capable of being wired, and repeating the step (6); if not, performing rectangle segmentation judgment;
and (8): checking whether all pins of the device to be tested are processed, if so, continuing to execute the step (9), otherwise, selecting an unprocessed pin in the device to be tested, and resetting x to an initial value 0 until the step (4) is processed;
and (9): and (4) checking whether all the devices to be tested are processed, if so, finishing wiring, otherwise, selecting an unprocessed device to be tested, taking an unprocessed pin in the device to be tested, and resetting x to an initial value 0 until the step (4) is processed.
2. The method for performing layout wiring on transistors in an array to be tested one by one according to claim 1, wherein in the step (1), if the positions of all candidate devices are known, position information is directly imported; and if the positions of the candidate devices are unknown, searching and acquiring the positions of all the candidate devices.
3. The method for performing layout wiring on transistors in an array to be tested one by one according to claim 2, wherein the step of finding and acquiring the positions of all candidate devices specifically comprises the following steps:
step a: the GT polygon is a polygon with a polysilicon layer and a diffusion layer, and the SD polygon is a polygon with a diffusion layer but no polysilicon layer;
acquiring all GT polygons, and randomly selecting one GT polygon as G; setting the S polygon as the SD polygon connected with the left side of the G, and setting the D polygon as the SD polygon connected with the right side of the G;
step b: searching whether the G is connected with the metal, if the G is connected with the metal, processing to the step c, and otherwise, processing to the step h;
step c: for G, checking whether an S polygon and a D polygon exist at the same time, if so, processing to step D, otherwise, processing to step h;
step d: checking whether the D polygon is connected with metal, if so, processing in the step f, and otherwise, processing in the step e;
step e: check if the D polygon has another GT polygon connected: if yes, replacing the D polygon of G with the GT polygon, and rechecking in step D; if not, processing in the step h;
step f: check if the S polygon has metal attached: if yes, adding the transistor (G, D, S) to the device list, and processing to the step h; if not, processing in the step g;
step g: check if this S polygon is connected to another GT polygon: if yes, replacing the S polygon of G with the GT polygon, and rechecking in step f; if not, processing in the step h;
step h: checking whether the GT polygons obtained in the step a are processed, if so, processing in the step i, otherwise, setting an unprocessed GT polygon as G, and repeating the step b;
step i: for the obtained equipment list, taking a transistor in the equipment list to carry out the processing of the step j;
step j: firstly, identifying whether the injected impurities of the transistor are N-type impurities or P-type impurities, and then identifying whether the well of the transistor is a P-type well or an N-type well; then, it is determined whether an impurity region opposite to the implanted impurity exists in the same well:
if so, locating an impurity region opposite to the impurity implantation in the same well, identifying a metal polygon B, adding the transistor (G, D, S, B) to a candidate list as a candidate device, wherein the transistor (G, D, S, B) has four pins, namely a pin G, a pin D, a pin S and a pin B;
if not, directly adding the transistor (G, D, S) to a candidate list as a candidate device, wherein the transistor (G, D, S) has three pins, namely a pin G, a pin D and a pin S;
step k: and (e) checking whether all the transistors in the equipment list are processed, if so, finishing the search of the candidate device, and otherwise, taking an unprocessed transistor to the step j for repeated processing.
4. The method for performing layout wiring on transistors in an array to be tested one by one according to claim 1, wherein in the step (4), the rectangular division of the metal polygon M1 is: and traversing the vertexes along the rotation direction from one vertex of the metal polygon, and when three adjacent vertexes form a convex structure, taking two adjacent vertexes as two vertexes of a rectangle, dividing the rectangle from the metal polygon and adding the rectangle into a rectangle list until the metal polygon is divided into a plurality of rectangles.
5. The method for performing layout wiring on transistors in an array to be tested one by one according to claim 4, wherein in the rectangle division judgment, the threshold of x times is 2;
when the value of x is 0, the rotation direction is set to be clockwise when the metal polygon M1 is rectangularly divided, and when the value of x is 1, the rotation direction is set to be counterclockwise when the metal polygon M1 is rectangularly divided; and starting the segmentation from the same vertex for the same metal polygon M1.
6. The method for performing layout wiring on transistors in an array to be tested one by one according to claim 1, wherein in the step (5), the rectangle satisfying the wiring condition is a rectangle with an area exceeding a threshold, and the rectangle with an area smaller than the threshold cannot be subjected to wiring.
7. The method according to claim 1, wherein in the step (6), it is determined whether a wiring path exists between the rectangle and the corresponding metal frame, and the method specifically includes the following steps:
step m: exploring paths from the rectangle to the corresponding metal frame to obtain a plurality of paths which are respectively marked as unprocessed;
step n: selecting a shortest path from the unprocessed paths;
step o: and (3) judging the shortest path:
if the shortest path is an unallocated path, it is indicated that routing can be performed, the shortest path is used as a routing path, and the routing path is marked as being allocated to the pin;
if the shortest path is an allocated path, judging whether an unprocessed path still exists, if so, repeating the step n, and if not, judging that the rectangular and the corresponding metal frame do not have a wiring path.
8. The method according to claim 1, wherein in step (1), the device under test determined by each metal frame is a candidate device located in the range of the metal frame and closest to the center of the metal frame among the selectable candidate devices, each metal frame corresponds to only one device under test, and each device under test corresponds to only one metal frame.
9. The method according to claim 8, wherein for the case of failed wiring of the metal frame and the corresponding device under test, all devices under test with failed wiring are marked as being unselectable, and whether there are any more selectable candidate devices is determined for all corresponding metal frames:
if the metal frame has no selectable candidate device, wiring fails;
if the metal frame has selectable candidate devices, determining a device to be tested for the metal frame again; and then, for all newly determined devices to be tested, the step (2) is executed again.
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