CN117059510B - Method, device, equipment and storage medium for processing performance parameters of crystal grains in wafer - Google Patents

Method, device, equipment and storage medium for processing performance parameters of crystal grains in wafer Download PDF

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CN117059510B
CN117059510B CN202311311669.8A CN202311311669A CN117059510B CN 117059510 B CN117059510 B CN 117059510B CN 202311311669 A CN202311311669 A CN 202311311669A CN 117059510 B CN117059510 B CN 117059510B
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performance parameter
wafer
test
parameter distribution
performance
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CN117059510A (en
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欧阳睿
邹欢
李凯亮
刘静
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Ziguang Tongxin Microelectronics Co Ltd
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Ziguang Tongxin Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D21/00—Measuring or testing not otherwise provided for
    • G01D21/02—Measuring two or more variables by means not covered by a single other subclass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30204—Marker
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30—Computing systems specially adapted for manufacturing

Abstract

The application discloses a processing method, a processing device, processing equipment and a storage medium for performance parameters of crystal grains in a wafer, wherein coordinate information and performance parameters of each crystal grain in a test wafer are obtained; determining a reference value and a step value based on performance parameters of each grain in the test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval; and generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein each crystal grain corresponding region in the performance parameter distribution diagram is provided with a mark corresponding to a performance parameter distribution interval to which the performance parameter of the crystal grain belongs, so that the trend distribution characteristics of the performance parameter of the crystal grain in the wafer can be intuitively and clearly and accurately identified from the performance parameter distribution diagram, and the process parameters influencing the performance parameter of the crystal grain in the wafer are optimized by combining the process information related to the processing of corresponding devices, thereby improving the product quality, the consistency of the performance, the stability and the yield.

Description

Method, device, equipment and storage medium for processing performance parameters of crystal grains in wafer
Technical Field
The present disclosure relates to the field of semiconductor product manufacturing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for processing performance parameters of a die in a wafer.
Background
An integrated circuit is a semiconductor chip that contains many electrical components that handle various functions. Integrated circuits are manufactured by creating a number of identical circuits on a wafer, each identical circuit constituting a die, and after dicing the dies on the wafer, packaging the integrated circuits. The wafer production of integrated circuits takes several months, and several hundred independent process steps are repeated to perform core processes such as cleaning, photoresist coating, exposing, developing, etching, doping, annealing, etc., so a series of tests are required to ensure that the integrated circuits produced on the wafer are within the specification range. In the current production process, conventional testing methods include wafer acceptance testing (Wafer Acceptance Test, WAT), pre-package wafer testing (CP), and post-package Final Test (FT).
The WAT test is a sampling test, and tests a test key paved at a specific position on a wafer so as to infer whether a key process of a crystal grain is normal and stable, and the key process is oriented to a device level. The CP test and the FT test are 100% tests performed on all dies in the wafer. The CP test is a screening test for a wafer, and performs a related function and performance screening test on the wafer, so as to pick out a bad die (die) before packaging, improve the yield of the factory, and reduce the subsequent package cost. The FT test is mainly a basic functional test of the packaged finished product to detect the damaged chips during dicing and packaging.
The emphasis of WAT test, CP test and FT test are different, but there are obvious disadvantages. WAT testing is directed to the device layer, and uses the sample grain sampling result in the wafer to represent the overall wafer distribution condition, and has limitations. Although 100% of crystal grains in the wafer participate in the test in the CP/FT test, the test is managed by screening out crystal grains meeting the range of design specifications, the yield can reflect the fluctuation direction of the process, but the trend of the process deviation direction cannot be intuitively represented, and sufficient allowance can be left in the design and the manufacture, so that the specification limit is too loose, the actual performances among the crystal grains in the wafer are obviously different, and the consistency of products cannot be effectively ensured.
Disclosure of Invention
In order to solve the technical problems, the embodiments of the present application provide a processing method, apparatus, device and storage medium for a die performance parameter in a wafer, so as to provide a distribution diagram for intuitively and explicitly characterizing the die performance parameter in the wafer by processing the die performance parameter in the wafer, thereby facilitating accurate identification of trend distribution characteristics of the die performance parameter in the wafer, optimizing process parameters affecting the die performance parameter in the wafer in combination with process information related to processing of corresponding devices, and improving product quality, uniformity of performance, stability and yield.
In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions:
a processing method of a crystal grain performance parameter in a wafer comprises the following steps:
acquiring coordinate information and performance parameters of each crystal grain in a test wafer;
determining a reference value and a step value based on performance parameters of each crystal grain in a test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval;
and generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein each crystal grain corresponding region in the performance parameter distribution diagram is provided with a mark corresponding to a performance parameter distribution interval to which the performance parameter of the crystal grain belongs.
Optionally, determining the reference value and the step value based on the performance parameters of each die in the test wafer includes:
calculating an average value of the performance parameters of all the dies in the test wafer based on the performance parameters of each die in the test waferAs a reference value and calculate the standard deviation sigma of the performance parameters of all dies in the test wafer as a step value.
Optionally, setting a plurality of performance parameter distribution intervals based on the reference value and the step value includes:
according to less than-3σ；/>-3σ to->-2σ；/>-2σ to->-σ；/>-sigma to->；/>To->+σ；/>+sigma to->+2σ；/>+2σ to->+3σ and greater than +.>And setting 8 performance parameter distribution intervals, wherein the boundary points of two adjacent performance parameter distribution intervals are contained in any one interval of the two adjacent performance parameter distribution intervals.
Optionally, the processing method further includes, when generating the performance parameter distribution map of the test wafer:
and setting the area corresponding to the crystal grain with the missing performance parameter in the performance parameter distribution diagram as a preset mark, wherein the preset mark is different from the mark corresponding to each performance parameter distribution interval.
Optionally, setting the marks corresponding to the performance parameter distribution intervals includes:
setting the corresponding colors of the performance parameter distribution intervals, wherein the colors corresponding to the different performance parameter distribution intervals are different.
Optionally, obtaining the coordinate information and the performance parameters of each die in the test wafer includes:
in a test log of a wafer test before packaging (CP test) or a finished product test after packaging (FT test), acquiring batch numbers of a plurality of wafers, wafer numbers, and coordinate information and performance parameters of crystal grains in each wafer;
and determining one or more wafers as test wafers according to the batch numbers and the wafer numbers, and extracting coordinate information and performance parameters of each die in the test wafers.
Optionally, the performance parameter of the die includes at least one of voltage, current, capacitance, and frequency.
An apparatus for processing performance parameters of a die in a wafer, comprising:
the acquisition unit is used for acquiring coordinate information and performance parameters of each crystal grain in the test wafer;
the computing unit is used for determining a reference value and a step value based on the performance parameters of each crystal grain in the test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval;
and the image unit is used for generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein the corresponding area of each crystal grain in the performance parameter distribution diagram is provided with a mark corresponding to the performance parameter distribution interval of the crystal grain.
An apparatus for processing die performance parameters in a wafer, comprising: a memory and a processor;
the memory is used for storing programs;
the processor is used for executing the program to realize each step of the processing method of the performance parameters of the crystal grains in the wafer.
A storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method for processing die performance parameters in a wafer described above.
Compared with the prior art, the technical scheme has the following advantages:
according to the processing method for the performance parameters of the crystal grains in the wafer, the coordinate information and the performance parameters of all the crystal grains in the test wafer are obtained; determining a reference value and a step value based on performance parameters of each grain in the test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval; and generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein each crystal grain corresponding region in the performance parameter distribution diagram is provided with a mark corresponding to a performance parameter distribution interval to which the performance parameter of the crystal grain belongs, so that the trend distribution characteristic of the performance parameter of the crystal grain in the wafer can be intuitively and clearly and accurately identified from the performance parameter distribution diagram, the process parameters influencing the performance parameter of the crystal grain in the wafer are optimized by combining the process information related to the processing of corresponding devices, and the product quality, the consistency of the performance, the stability and the yield are improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic top view of a wafer;
FIG. 2 is a flow chart of a method for processing performance parameters of a die in a wafer according to an embodiment of the present disclosure;
FIG. 3 is a graph showing a performance parameter profile of a test wafer obtained by a method for processing die performance parameters in a wafer according to an embodiment of the present application;
FIG. 4 is a graph showing the performance parameter profile of a test wafer obtained by the processing method according to the embodiment of the present application after the process of improving the performance parameter profile of the test wafer shown in FIG. 3;
FIG. 5 is a schematic diagram showing a normal distribution of a performance parameter of each die in a wafer produced by an original process and a wafer tested by a processing method according to an embodiment of the present application after the process is improved;
FIG. 6 is a schematic diagram of a device for processing performance parameters of a die in a wafer according to an embodiment of the present disclosure;
fig. 7 is a block diagram of a hardware structure of a processing apparatus for processing performance parameters of a die in a wafer according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
For the sake of understanding the present application, fig. 1 shows a schematic top view of a wafer 10, and it can be seen that the wafer 10 includes a plurality of dies 11, after the plurality of dies 11 are formed on the wafer 10, the dies 11 are cut, and each die 11 is packaged to form an integrated circuit chip.
Fig. 2 is a schematic flow chart of a processing method of a die performance parameter in a wafer according to an embodiment of the present application, and as shown in fig. 2, the processing method includes:
s100: coordinate information and performance parameters of each die in the test wafer are obtained.
The coordinate information of the crystal grains in the wafer refers to the position information of the crystal grains in the wafer, and if the positions of different crystal grains in the wafer are different, the coordinate information of the different crystal grains is also different, and the positions of the crystal grains in the wafer can be positioned through the coordinate information of the crystal grains in the wafer.
The performance parameter of the die in the wafer is a parameter representing the performance and the function of the die in the wafer, and may be a key electrical parameter having a great influence on the performance and the function of the chip, for example, at least one of voltage, current, capacitance and frequency, specifically, for example, a reference voltage of the chip, etc., but the application is not limited to the specific parameter, and the specific parameter is determined according to the situation.
Alternatively, since the wafer test before packaging (CP test) and the finished product test after packaging (FT test) are both 100% tests performed on all the dies in the wafer, the coordinate information and the performance parameters of each die in the test wafer can be obtained from the test logs of the wafer test before packaging (CP test) and the finished product test after packaging (FT test). However, the present application is not limited thereto, and the coordinate information and performance parameters of each die in the test wafer may be obtained from other 100% tests performed on all dies in the wafer.
Specifically, step 100 includes the steps of:
s110: in a test log of a wafer test before packaging (CP test) or a finished product test after packaging (FT test), acquiring batch numbers of a plurality of wafers, wafer numbers, and coordinate information and performance parameters of crystal grains in each wafer;
s120: and determining one or more wafers as test wafers according to the batch numbers and the wafer numbers, and extracting coordinate information and performance parameters of each die in the test wafers.
It should be noted that, wafers (Wafer) are the smallest processing units for manufacturing integrated circuit chips, and are circulated in batches (LOT) in the manufacturing process of wafers, and a LOT (LOT) is generally formed by using a plurality of (e.g. 25) wafers (Wafer), and specific wafers can be determined by a certain LOT number and a certain Wafer number, and the wafers in the same LOT are subjected to the same equipment processing at a certain station, so that the influence of the process and equipment of the production line can leave a distribution of obvious trend on the wafers in the LOT.
The wafer test before packaging (CP test) is usually completed by an automated test equipment (Automatic Test Equipment, ATE), and a wafer test result Map (Chip Probe Map, CP Map) representing the distribution of the Chip function test results is output on the Probe (Probe) equipment during the test, in the wafer test result Map, different BIN values are used for the qualified chips passing the Chip function test and the failed chips failing the test according to the set BIN value relationship, so that in a test log of the wafer test before packaging (CP test), the lot number of the wafer, the wafer number, and the coordinate information and performance parameters of the die in each wafer are recorded, and in a test log of the wafer test before packaging (CP test), the lot number of a plurality of wafers, the wafer number, and the coordinate information and performance parameters of the die in each wafer can be obtained;
the finished product test (FT test) after encapsulation is finished by ATE and a handle, and chips passing and not passing the test are distinguished and treated by the handle on physical placement, so that the batch number of the wafer, the wafer number and the coordinate information and performance parameters of the crystal grains in each wafer are recorded in a test log of the finished product test (FT test) after encapsulation, and the batch numbers of a plurality of wafers, the wafer numbers and the coordinate information and performance parameters of the crystal grains in each wafer can be obtained in the test log of the finished product test (FT test) after encapsulation;
furthermore, one or more wafers can be determined as test wafers according to the batch number and the wafer number, and the coordinate information and the performance parameters of each die in the test wafers can be extracted.
S200: and determining a reference value and a step value based on the performance parameters of each crystal grain in the test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval.
Optionally, determining the reference value and the step value based on the performance parameters of each die in the test wafer includes:
s210: calculating a test based on performance parameters of each die in the test waferAverage value of performance parameters of all dies in test waferAs a reference value and calculate the standard deviation sigma of the performance parameters of all dies in the test wafer as a step value.
Thus, further alternatively, a plurality of performance parameter distribution intervals may be set in accordance with the central limit theorem. Specifically, based on the reference valueAnd a step value sigma, the setting of the plurality of performance parameter distribution intervals comprising:
s220: according to less than-3σ；/>-3σ to->-2σ；/>-2σ to->-σ；/>-sigma to->；/>To->+σ；/>+sigma to->+2σ；/>+2σ to->+3σ and greater than +.>And setting 8 performance parameter distribution intervals, wherein the boundary points of two adjacent performance parameter distribution intervals are contained in any one interval of the two adjacent performance parameter distribution intervals.
Assuming that the performance parameter of one die in the test wafer is a, table 1 shows the case where the performance parameter a of the die is distributed in the 8 performance parameter distribution intervals. Wherein the boundary point between two adjacent performance parameter distribution intervals is included in any one interval of the two adjacent performance parameter distribution intervals, for example,is->-sigma to->Interval sum->To->Boundary points of the +sigma interval, which may belong to +.>-sigma to->The interval may also belong to->To->The +σ interval, as the case may be.
TABLE 1 Performance parameter distribution intervals for die in wafer
It should be noted that the present application is directed to testing the average value of the performance parameters of all dies in a waferWhen the standard deviation sigma of the performance parameters of all the dies in the wafer is used as the reference value and the step value is used as the step value, the method is not limited to setting 8 performance parameter distribution intervals only in the above mode.
First, the present application does not limit the number of performance parameter distribution intervals set, for example, it may be as follows-2σ；/>-2σ to->-σ；/>-sigma to->；/>To->+σ；/>+sigma to->+2σ and greater than +.>+2σ, setting 6 performance parameter distribution intervals, and optionally setting the distribution intervals smaller than +.>-σ；/>-sigma to->；/>To->+σ and greater than->+σ, 4 performance parameter distribution intervals are set.
The present application is not limited to the use of the above-described reference valueThe symmetrically distributed performance parameter distribution interval can also be used as +.>The asymmetrically distributed performance parameter distribution interval may, for example, be smaller than +.>-2σ；-2σ to->-σ；/>-sigma to->；/>To->+σ；/>+sigma to->+2σ；/>+2σ to->+3σ and greater than +.>+3σ, 7 performance parameter distribution intervals are set, at which time the 7 performance parameter distribution intervals are +.>And asymmetrically distributed.
The present application is not limited to setting the performance parameter distribution interval by using a single step value σ, and may also be set by using step values of other multiples (including integer multiples or non-integer multiples), for example, according to a value smaller than-6σ；/>-6σ to->-4σ；/>-4σ to->-σ；/>-2σ to->；/>To->+2σ；/>+2σ to->+4σ；/>+4σ to->+6σ and greater than +.>Setting 8 performance parameter distribution intervals by +6σ, wherein the performance parameter distribution intervals are set by a step value of 2 times, namely 2σ; for another example, according to less than->-1.5σ；/>-1.5 sigma to->-σ；/>-sigma to->-0.5σ；/>-0.5 sigma to->；/>To->+0.5σ；/>+0.5σ to ∈0>+σ；/>+sigma to->+1.5σ and greater than +.>+1.5σ, 8 performance parameter distribution intervals are set, and at this time, the performance parameter distribution intervals are set with a step value of 0.5 times, that is, 0.5σ, as the case may be.
It should also be noted that the present application is not limited to testing the average value of the performance parameters of all dies in a waferAs a reference value, alternatively, the median X of the performance parameters of all dies in the wafer can also be tested 0.5 As a reference value, as the case may be. It will be appreciated that the average value of the performance parameters of all dies in the test wafer +.>The sum of the performance parameters (X1, X2 … Xn) for all dies in the test wafer divided by the number of dies (n) is expressed as:
arranging the performance parameters of all the dies in the test wafer as X in order from small to large (1) 、X (2) …X (n) Then median X 0.5 Can be expressed as:
when n is an odd number, X 0.5 =X ((n+1)/2) The method comprises the steps of carrying out a first treatment on the surface of the When n is even, X 0.5 =(X (n/2) +X ((n/2)+1) )/2。
The application is not limited to the standard deviation sigma of the performance parameters of all dies in the test wafer as the step value, but alternatively, the variance sigma of the performance parameters of all dies in the test wafer 2 As step values, as the case may be.
In practical application, a suitable performance parameter distribution interval can be set according to the characteristics of specific performance parameters of the grains in the wafer, so that the performance parameters of the grains with similar performance are divided into the same performance parameter distribution interval, and the performance parameters of the grains with larger performance difference are divided into different performance parameter distribution intervals, so that the trend distribution characteristics of the performance parameters of the grains in the wafer are intuitively, explicitly and accurately identified in the performance parameter distribution map of the test wafer.
In step S200, after each performance parameter distribution interval is set, the marks corresponding to each performance parameter distribution interval are further set, and the marks corresponding to different performance parameter distribution intervals are different.
Optionally, setting the marks corresponding to the performance parameter distribution intervals includes:
s230: setting the corresponding colors of the performance parameter distribution intervals, wherein the colors corresponding to the different performance parameter distribution intervals are different.
For example, as shown in Table 1, according to less than-3σ；/>-3σ to->-2σ；/>-2σ to->-σ；/>-sigma to->；/>To->+σ；/>+sigma to->+2σ；/>+2σ to->+3σ and greater than +.>+3σ, after setting 8 performance parameter distribution intervals, will be less than +.>The flag in this interval 3 sigma is set to dark blue, will +.>-3σ to->The mark of the-2σ interval is set to black, and-2σ to->The flag in this interval of-sigma is set to light blue, will +.>-2σ to->The flag of this interval is set to yellow, will +.>To->The flag in this section +sigma is set to green, and +.>+sigma to->The flag in this interval +2σ is set to purple, and+2σ to->The flag in this section +3σ is set to red, which will be greater than +.>The flag for this interval +3σ is set to orange. Of course, the above color setting is only an example, and the setting color of the specific performance parameter distribution interval is not limited in the present application, and is specific as the case may be.
S300: and generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein each crystal grain corresponding region in the performance parameter distribution diagram is provided with a mark corresponding to a performance parameter distribution interval to which the performance parameter of the crystal grain belongs.
Alternatively, the performance of all dies in a wafer may be testedAverage value of parametersAnd establishing a hash table according to the standard deviation sigma and the coordinate information and performance parameters of each crystal grain in the test wafer, so as to quickly determine the performance parameter distribution interval and the corresponding mark of each crystal grain in the test wafer according to the coordinate information of each crystal grain in the test wafer, and correspondingly marking the corresponding area of each crystal grain in the performance parameter distribution map of the test wafer, thereby finally generating the performance parameter distribution map of the test wafer.
Alternatively, the corresponding areas of the dies may be marked one by one in the performance parameter distribution diagram of the test wafer, or the corresponding areas of the dies may be marked at the same time, as the case may be.
Considering that there may be some cases where there is a test result of the die missing performance parameter in the test of the performance parameter of each die in the wafer, such as the wafer before packaging (CP test) or the finished product after packaging (FT test), the processing method, when generating the performance parameter distribution map of the test wafer, optionally further includes:
s400: and setting the area corresponding to the crystal grain with the missing performance parameter in the performance parameter distribution diagram of the test wafer as a preset mark, wherein the preset mark is different from the mark corresponding to each performance parameter distribution section.
For example, in the case of the marks corresponding to the respective performance parameter distribution sections shown in table 1, the areas corresponding to the dies whose performance parameters are missing in the performance parameter distribution diagram of the test wafer may be set to be blank.
Fig. 3 shows a performance parameter distribution diagram of a test wafer obtained by a processing method of performance parameters of dies in a wafer according to an embodiment of the present application, and it can be seen that the performance parameter distribution diagram of the test wafer can intuitively and explicitly identify the trend distribution characteristics of the performance parameters of the dies in the wafer accurately, so that engineers can combine process information related to device processing to locate a process technology, optimize the process parameters affecting the corresponding performance parameters of the dies in the wafer, improve the trend distribution caused by the process reasons, reduce the differences of quality, performance and the like among chips, and improve the consistency, stability and yield of product quality and performance.
Fig. 4 shows a performance parameter distribution diagram of a test wafer obtained by the processing method according to the embodiment of the present application after the performance parameter distribution diagram improvement process of the test wafer shown in fig. 3, and comparing with fig. 3, it can be seen that the performance parameters of each die in the wafer shown in fig. 4 approach the same mark, i.e. approach the same performance parameter distribution interval, that is, the uniformity of the performance parameters of each die in the wafer is greatly improved.
Fig. 5 is a schematic diagram showing a normal distribution comparison of a performance parameter of each die in a wafer produced by an original process and a wafer tested by a processing method according to an embodiment of the present application, where the wafer tested by the processing method according to the embodiment of the present application has a performance parameter distribution diagram, and it can be seen that the quality, uniformity, stability and yield of the wafer produced are greatly improved after the processing method is improved by the processing method according to the embodiment of the present application.
In summary, the method for processing the performance parameters of the crystal grains in the wafer provided by the embodiment of the application obtains the coordinate information and the performance parameters of each crystal grain in the test wafer; determining a reference value and a step value based on performance parameters of each crystal grain in the test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value of integer multiple, and setting marks corresponding to the performance parameter distribution intervals; according to the coordinate information of each crystal grain in the test wafer, a performance parameter distribution diagram of the test wafer is generated, the corresponding area of each crystal grain in the performance parameter distribution diagram is provided with a mark corresponding to the performance parameter distribution interval of the crystal grain, so that the trend distribution characteristics of the performance parameters of the crystal grain in the wafer can be intuitively and clearly and accurately identified from the performance parameter distribution diagram, the process parameters influencing the performance parameters of the crystal grain in the wafer are optimized by combining the process information related to the processing of corresponding devices, and the product quality, the consistency of the performance, the stability and the yield are improved.
The embodiment of the application also provides a processing device for performance parameters of crystal grains in a wafer, as shown in fig. 6, the device comprises:
an acquiring unit 100, configured to acquire coordinate information and performance parameters of each die in the test wafer;
a calculating unit 200, configured to determine a reference value and a step value based on performance parameters of each die in the test wafer, set a plurality of performance parameter distribution intervals based on the reference value and the step value, and set a flag corresponding to each performance parameter distribution interval;
and the image unit 300 is configured to generate a performance parameter distribution diagram of the test wafer according to the coordinate information of each die in the test wafer, where each die corresponding region in the performance parameter distribution diagram has a mark corresponding to a performance parameter distribution interval to which the performance parameter of the die belongs.
Since the device for processing the performance parameter of the die in the wafer and the method for processing the performance parameter of the die in the wafer are correspondingly referred to each other, and each step of the method for processing the performance parameter of the die in the wafer provided by the embodiment of the application has been discussed in detail, the details are not repeated here.
The embodiment of the application also provides processing equipment for the performance parameters of the crystal grains in the wafer, such as a computer. Alternatively, fig. 7 shows a hardware block diagram of a die performance parameter processing apparatus in a wafer, and as shown in fig. 7, the die performance parameter processing apparatus in a wafer may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4;
in the embodiment of the application, the number of the processor 1, the communication interface 2, the memory 3 and the communication bus 4 is at least one, and the processor 1, the communication interface 2 and the memory 3 complete communication with each other through the communication bus 4;
processor 1 may be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present invention, etc.;
the memory 3 may comprise a high-speed RAM memory, and may further comprise a non-volatile memory (non-volatile memory) or the like, such as at least one magnetic disk memory;
wherein the memory stores a program, the processor is operable to invoke the program stored in the memory, the program operable to:
acquiring coordinate information and performance parameters of each crystal grain in a test wafer;
determining a reference value and a step value based on performance parameters of each crystal grain in the test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval;
and generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein each crystal grain corresponding region in the performance parameter distribution diagram is provided with a mark corresponding to a performance parameter distribution interval to which the performance parameter of the crystal grain belongs.
Alternatively, the refinement function and the extension function of the program may be described above, and will not be described here.
The embodiment of the application also provides a storage medium, which may store a program adapted to be executed by a processor, the program being configured to:
acquiring coordinate information and performance parameters of each crystal grain in a test wafer;
determining a reference value and a step value based on performance parameters of each crystal grain in the test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval;
and generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein each crystal grain corresponding region in the performance parameter distribution diagram is provided with a mark corresponding to a performance parameter distribution interval to which the performance parameter of the crystal grain belongs.
Optionally, the refinement function and the extension function of the program may be described above, and are not described herein.
In the description, each part is described in a parallel and progressive mode, and each part is mainly described as a difference with other parts, and all parts are identical and similar to each other.
The features described in the various embodiments of the present disclosure may be interchanged or combined with one another in the description to enable those skilled in the art to make or use the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method for processing a die performance parameter in a wafer, comprising:
acquiring coordinate information and performance parameters of each crystal grain in a test wafer;
determining a reference value and a step value based on performance parameters of each crystal grain in a test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval;
and generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein each crystal grain corresponding region in the performance parameter distribution diagram is provided with a mark corresponding to a performance parameter distribution interval to which the performance parameter of the crystal grain belongs.
2. The method of claim 1, wherein determining the reference value and the step value based on the performance parameters of each die in the test wafer comprises:
calculating an average value of the performance parameters of all the dies in the test wafer based on the performance parameters of each die in the test waferAs a reference value and calculate the standard deviation sigma of the performance parameters of all dies in the test wafer as a step value.
3. The method of processing a die performance parameter in a wafer according to claim 2, wherein setting a plurality of performance parameter distribution intervals based on the reference value and the step value comprises:
according to less than-3σ；/>-3σ to->-2σ；/>-2σ to->-σ；/>-sigma to->；/>To->+σ；/>+sigma to->+2σ；+2σ to->+3σ and greater than +.>And setting 8 performance parameter distribution intervals, wherein the boundary points of two adjacent performance parameter distribution intervals are contained in any one interval of the two adjacent performance parameter distribution intervals.
4. The method of claim 1, wherein the processing method further comprises, when generating the profile of the performance parameter of the test wafer:
and setting the area corresponding to the crystal grain with the missing performance parameter in the performance parameter distribution diagram as a preset mark, wherein the preset mark is different from the mark corresponding to each performance parameter distribution interval.
5. The method of claim 1, wherein setting the corresponding flag for each performance parameter distribution interval comprises:
setting the corresponding colors of the performance parameter distribution intervals, wherein the colors corresponding to the different performance parameter distribution intervals are different.
6. The method of claim 1, wherein obtaining the coordinate information and the performance parameters of each die in the test wafer comprises:
in a test log of a wafer test before packaging (CP test) or a finished product test after packaging (FT test), acquiring batch numbers of a plurality of wafers, wafer numbers, and coordinate information and performance parameters of crystal grains in each wafer;
and determining one or more wafers as test wafers according to the batch numbers and the wafer numbers, and extracting coordinate information and performance parameters of each die in the test wafers.
7. The method of claim 1, wherein the die performance parameter comprises at least one of voltage, current, capacitance, and frequency.
8. A die performance parameter processing apparatus in a wafer, comprising:
the acquisition unit is used for acquiring coordinate information and performance parameters of each crystal grain in the test wafer;
the computing unit is used for determining a reference value and a step value based on the performance parameters of each crystal grain in the test wafer, setting a plurality of performance parameter distribution intervals based on the reference value and the step value, and setting marks corresponding to each performance parameter distribution interval;
and the image unit is used for generating a performance parameter distribution diagram of the test wafer according to the coordinate information of each crystal grain in the test wafer, wherein the corresponding area of each crystal grain in the performance parameter distribution diagram is provided with a mark corresponding to the performance parameter distribution interval of the crystal grain.
9. A die performance parameter processing apparatus in a wafer, comprising: a memory and a processor;
the memory is used for storing programs;
the processor is configured to execute the program to implement the steps of the method for processing a die performance parameter in a wafer according to any one of claims 1 to 7.
10. A storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for processing die performance parameters in a wafer according to any one of claims 1 to 7.
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