CN115332079A - Preparation method and application of two-dimensional floating gate phototransistor - Google Patents
Preparation method and application of two-dimensional floating gate phototransistor Download PDFInfo
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Abstract
The invention discloses a preparation method and application of a two-dimensional floating gate phototransistor, which can simultaneously realize the functions of a light sensor, a storage element and a calculation unit in a single device by utilizing the physical properties of the phototransistor. The structure of the transistor comprises a substrate, an oxide layer, a charge trapping layer, a tunneling layer, a two-dimensional semiconductor channel layer, a source electrode and a drain electrode from bottom to top. The charge trapping layer is made of a single-layer graphene material, the two-dimensional semiconductor channel is made of a two-dimensional transition metal sulfide material, and the source electrode and the drain electrode are respectively positioned on two sides of the two-dimensional semiconductor channel. The invention integrates the functions of optical signal sensing, data storage and logical operation into a single transistor by stacking a single-layer graphene charge trapping layer/tunneling layer/two-dimensional transition metal sulfide channel layer to form a floating gate phototransistor, can realize the reconfigurable logical calculation and the photoelectric synapse simulation of AND, OR, NAND and NOR, and provides a promising hardware platform for the calculation in a sensor of visual information.
Description
Technical Field
The invention relates to the technical field of microelectronic devices, in particular to a two-dimensional material floating gate phototransistor which can be used for reconfigurable logic calculation and calculation in a visual information sensor.
Background
The high performance machine vision system can be used to detect changes in the environment and movement of objects, collect effective visual information, and interpret and respond to the visual information by performing arithmetic processing on the visual information data. Machine vision systems have become an integral part of emerging internet of things (IoT) technologies and a range of more revolutionary intelligent applications such as autopilot, robotics, etc. Today's machine vision systems, however, are primarily based on a sensor-computation separation architecture, where visual information is captured as analog signals by sensors, converted to digital signals in analog-to-digital converters (ADCs), and finally stored/processed step by step in storage and processing units. Although there has been a great progress in performance of machine vision systems, the low energy use efficiency and data interaction delay due to the complex structure of the conventional machine vision system, which requires the use of physically separated sensors, analog-to-digital converters and memory/processing units, cannot meet the wide low power consumption requirements in the application of the internet of things. Current improved methods, such as applying complex machine learning algorithms or using advanced image sensors, cannot fully overcome the system power consumption and delay challenges associated with conventional sensor-computation separation architectures. Therefore, future machine vision technologies inevitably require a thorough distinction from conventional architectures in terms of visual information acquisition and processing.
The computing technology in the sensor can integrate image sensing, data storage and computing functions in the same physical unit, has extremely high energy and time efficiency, hopefully subverts the traditional sensing-computing separation architecture, and is a powerful competitor of the next generation machine vision technology. Currently, memory computing technologies such as nonvolatile memory devices have been studied to integrate computing functions in memory cells, so as to avoid data interaction delay and energy consumption caused by von neumann architecture memory separation. However, in machine vision systems, there is still a bottleneck of data interaction between the sensors and the memory/processing unit, and further design of device functions and application methods is required. Structures such as floating gate phototransistors and floating gate memristor transistors based on two-dimensional semiconductor heterojunction can realize storage and calculation integration on the function, and meanwhile, the environmental information sensing function is further realized on the basis of material design, and the sensing and calculation integration technology with high energy efficiency and low delay is realized.
Disclosure of Invention
The invention aims to solve the problem of data interaction bottleneck of a sensor and a memory/processing unit in the background technology, and provides a preparation method and application of a two-dimensional floating gate photoelectric transistor.
The technical scheme of the invention is described as follows:
1. the technical principle is as follows:
the invention designs a two-dimensional floating gate phototransistor which is a single-layer graphene floating gate Van der Waals heterojunction structure with the resistance state function of a nonvolatile light-operated device. The single-layer graphene is used as a charge trapping layer, the transition metal sulfide is used as a two-dimensional semiconductor channel layer, and when light or electric stimulation with high intensity is applied, charge carriers pass through the tunneling layer to capture and release charges between the single-layer graphene floating gate and the two-dimensional transition metal sulfide channel layer, so that the non-volatile regulation and control of channel conductance are realized. After the charge trapping layer is set to be in a high/low resistance state by a higher-intensity pulse, the channel conductance state can be jointly determined by light input and gate voltage input, so that reconfigurable logic calculation of AND, OR, NAND and NOR is realized, and the device can be used as a photoelectric binary logic prototype device integrating sensing and calculation. Taking the NAND logic implementation of an N-channel two-dimensional floating gate phototransistor as an example, when the device applies a large negative gate voltage, the charge trapping layer releases electron storage holes and the device is preprogrammed to a low resistance state. The light pulse and the gate voltage pulse are defined as two logical inputs. When no pulse is added and only light or electric pulse is added, the channel keeps a low resistance state due to the nonvolatile storage characteristic of the device; when the optical pulse and the electric pulse are added simultaneously, the hole in the graphene is neutralized by the electron tunneled from the N-type semiconductor channel to the graphene, so that the floating gate effect is weakened, the voltage-assisted erasing phenomenon of the storage state is generated, and the nonvolatile switching from the low resistance state to the high resistance state, namely the NAND logic gate, is realized. Due to the switching current ratio of the device being greater than 10, except for non-volatile binary conductance state switching 6 And the intermediate conductance state has non-volatility, the invention can also realize the gradual change type conductance regulation and control of the simulated nerve synapse and realize the multi-stage, non-volatile and gradual change type conductance state switching, thereby simulating the behavior of the nerve synapse and providing the possibility of nerve form calculation for a visual sensing calculation system.
2. The device structure is as follows:
according to the principle, the two-dimensional floating gate phototransistor capable of being used for constructing the optical information nonvolatile logic gate is characterized in that a substrate, an oxidation layer, a charge trapping layer, a tunneling layer, a two-dimensional semiconductor channel layer, a source electrode and a drain electrode are vertically distributed on the substrate from bottom to top in sequence: the charge trapping layer is made of a single-layer graphene material, and the two-dimensional semiconductor channel layer is made of a two-dimensional transition metal sulfide material.
The method for manufacturing the device comprises the following steps:
the method comprises the following steps: mechanically stripping graphene to cover with thermal oxide SiO by using tape micro-mechanical stripping method 2 Identifying a single-layer graphene sheet on a substrate of an oxide layer through an optical microscope and Raman spectroscopy to form a charge trapping layer;
step two: mechanically stripping a two-dimensional hexagonal boron nitride sheet onto Polydimethylsiloxane (PDMS) by using a tape micro-mechanical stripping method, identifying the qualified hexagonal boron nitride sheet on the PDMS through an optical microscope, and transferring the loaded hexagonal boron nitride sheet onto a charge trapping layer by using the PDMS to form a tunneling layer;
step three: mechanically stripping a two-dimensional transition metal sulfide sheet onto PDMS by using a tape micro-mechanical stripping method, identifying a qualified two-dimensional transition metal sulfide sheet on PDMS through an optical microscope, and transferring the two-dimensional transition metal sulfide sheet borne by PDMS onto a tunneling layer to form a two-dimensional semiconductor channel layer;
step four: preparing a metal gold electrode with a strip shape by utilizing photoetching, thermal evaporation and metal stripping processes, and transferring the metal gold electrode onto a two-dimensional semiconductor channel layer by utilizing a PDMS (polydimethylsiloxane) adhesive film to form a source electrode and a drain electrode;
step five: the charge trapping layer is pre-programmed by applying voltage pulses with different polarities to a back gate substrate, and then four different reconfigurable nonvolatile photoelectric logics of AND, OR, NAND and NOR are realized under different photoelectric pulse inputs.
The invention has the following advantages:
1. according to the single-layer graphene floating gate heterojunction floating gate phototransistor, due to the fact that the single-layer graphene material is used in the charge trapping layer, positive and negative photoconduction switching can be achieved in the same device, compared with an existing device which only can achieve positive photoelectric response, the single-layer graphene floating gate heterojunction floating gate phototransistor has higher operation freedom degree, and the single-layer graphene floating gate phototransistor is a basis for achieving AND, OR, NAND and NOR reconfigurable photoelectric logic.
2. Meanwhile, the initial state of a charge quantity pre-programming device stored in the charge trapping layer can be regulated and controlled through the back gate voltage, then gate electric pulse and light pulse are used as logic inputs at two ends, and, or, NAND and NOR photoelectric logic calculation is reconfigurable in one transistor, the number of transistors required by a photoelectric digital logic gate is reduced, the circuit integration level is improved, and the circuit area is reduced.
3. In addition, the on-off current ratio of the device is more than 10 6 And the intermediate conductance state has non-volatility, and the gradual conductance regulation and the non-volatile multi-level storage of the simulated nerve synapse can be realized in the same device.
Drawings
FIG. 1 is a schematic cross-sectional view of a two-dimensional floating gate phototransistor used for constructing an optical information nonvolatile logic gate according to the present invention;
FIG. 2 is a flow chart illustrating a method for fabricating a two-dimensional floating gate phototransistor used for constructing a non-volatile logic gate of optical information and an application thereof according to the present invention.
Detailed Description
In order to make the objects and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the two-dimensional floating gate phototransistor used for constructing the optical information nonvolatile logic gate of the present invention includes: the transistor comprises a back gate substrate 1, an oxide layer 2, a charge trapping layer 3, a tunneling layer 4, a two-dimensional semiconductor channel layer 5, a source electrode 6 and a drain electrode 7. The back gate substrate 1 is heavily doped p-type Si and also serves as a gate of a device; the oxide layer 2 is thermal oxidized 300nm SiO 2 (ii) a The charge trapping layer 3 is made of a single-layer graphene material; the tunneling layer 4 is made of two-dimensional hexagonal boron nitride material; the two-dimensional semiconductor channel layer 5 is made of molybdenum disulfide belonging to transition metal sulfide, and certainly, tungsten disulfide, rhenium disulfide or tungsten diselenide belonging to transition metal sulfide can also be used; the source electrode 6 and the drain electrode 7 are made of metal gold materials.
The back gate substrate 1, the oxide layer 2, the charge trapping layer 3, the tunneling layer 4 and the two-dimensional semiconductor channel layer 5 are vertically distributed from bottom to top. The source electrode 6 and the drain electrode 7 are respectively located on both sides of the two-dimensional semiconductor channel layer 5.
The invention provides a preparation method of a two-dimensional floating gate phototransistor which can be used for constructing an optical information nonvolatile logic gate, and the following embodiments are provided.
The method for manufacturing the two-dimensional graphene/hexagonal boron nitride/molybdenum disulfide Van der Waals heterojunction floating gate memory and the implementation method of the reconfigurable photoelectric logic calculation of AND, OR, NAND and NOR are used. Referring to fig. 2, the implementation steps of this example are as follows:
the method comprises the following steps: fabrication of a charge trapping layer
Oxygen plasmaTreating the coating with a thermally oxidized SiO 2 The back gate substrate 1 of the oxide layer 2 is coated with thermal oxide SiO for 3min by using a micro-mechanical stripping process 2 The substrate 1 of the oxide layer 2 is mechanically stripped of graphene with tape and single-layer graphene sheets are identified by optical microscopy and raman spectroscopy to form a charge-trapping layer, as shown in fig. 2 (b).
Step two: making a tunneling layer
Mechanically stripping a two-dimensional hexagonal boron nitride sheet onto PDMS by using a tape micro-mechanical stripping method, identifying a qualified hexagonal boron nitride sheet (with the thickness of 8-15 nm) on the PDMS through an optical microscope, and aligning and transferring the loaded hexagonal boron nitride sheet onto the charge trapping layer by using the PDMS through a two-dimensional material transfer system to form a tunneling layer, as shown in fig. 2 (c).
Step three: fabricating two-dimensional semiconductor channel layers
And mechanically stripping the two-dimensional molybdenum disulfide sheet onto PDMS by using a tape micro-mechanical stripping method, identifying the qualified molybdenum disulfide sheet on the PDMS through an optical microscope, and aligning and transferring the loaded molybdenum disulfide sheet onto the tunneling layer through a two-dimensional material transfer system by using the PDMS to form a two-dimensional semiconductor channel layer, as shown in fig. 2 (d).
Step four: manufacturing source electrode and drain electrode
Under the masking action of photoresist, metal alloy materials are thermally evaporated, then metal stripping is carried out, a metal gold electrode in a specific shape is formed on a Si slide, and then the metal gold electrode on the slide is aligned and transferred to a specific position through a two-dimensional material transfer system through PDMS to form a source electrode and a drain electrode, as shown in figure 2 (e).
Step five: device annealing
And carrying out vacuum annealing on the device for 1-2 h at 200 ℃, and reducing the contact resistance between the source electrode and the drain electrode and the two-dimensional semiconductor channel.
The implementation method of the reconfigurable logic in the embodiment is as follows:
according to the embodiment of the present invention, it should be noted that the gate voltage is input terminal 1, the visible light pulse is input terminal 2, and the large gate voltage (± 40V) is used as the pre-programmed reset signal, and the device channel is defined as "0" when in the high resistance state, defined as "1" when in the low resistance state, defined as "1" when the corresponding input signal is applied, and defined as "0" when the corresponding input signal is not applied.
TABLE 1 Pre-Programming
In the embodiment, when gate voltage of 40V is applied and a channel of the device is pre-programmed to be in a high-resistance state, gate voltage input adopts-6V and 1ms pulses, and light pulse input adopts 0.5mW and 1ms pulses, so that photoelectric AND logic can be realized;
when gate voltage 40V is applied and a channel of the device is preprogrammed into a high-resistance state, gate voltage input adopts-10V and 1ms pulses, and optical pulse input adopts 2mW and 1ms pulses, so that photoelectric OR logic can be realized;
when gate voltage is applied to minus 40V and a channel of the device is pre-programmed to be in a low resistance state, gate voltage input adopts pulses of 4V and 1ms, and light pulse input adopts pulses of 0.5mW and 1ms, so that photoelectric NAND logic can be realized;
when gate voltage is applied to be 40V and a channel of the device is pre-programmed to be in a low resistance state, 7V and 1ms pulses are adopted for gate voltage input, and 2mW and 1ms pulses are adopted for light pulse input, so that photoelectric 'NOR' logic can be realized;
TABLE 2 (a) "and" Gate conductance State
TABLE 2 (b) "OR" Gate conductance State
TABLE 2 (c) "NAND" gate conductance states
TABLE 2 (d) "NOR" gate conductance states
The above description is only one preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (6)
1. A method for preparing a two-dimensional floating gate phototransistor includes: the transistor comprises a back gate substrate (1), an oxide layer (2), a charge trapping layer (3), a tunneling layer (4), a two-dimensional semiconductor channel layer (5), a source electrode (6) and a drain electrode (7); oxide layer (2), charge trap layer (3), tunnel layer (4), two-dimensional semiconductor channel layer (5) are in proper order by supreme vertical distribution down on back gate substrate (1), and source electrode (6), drain electrode (7) are located the both ends of two-dimensional semiconductor channel layer (5) respectively, its characterized in that: the charge trapping layer (3) is made of a single-layer graphene material, the tunneling layer (4) is made of a two-dimensional hexagonal boron nitride material, the two-dimensional semiconductor channel layer (5) is made of a two-dimensional transition metal sulfide material, after the voltage of the back gate substrate (1) is applied for preprogramming, voltage pulses applied to the back gate substrate (1) and visible light pulses applied to the two-dimensional semiconductor channel layer (5) are used as logic inputs at two ends, and, OR, NAND and NOR reconfigurable nonvolatile photoelectric logic can be achieved in a single transistor.
2. The method of claim 1, wherein the two-dimensional transition metal sulfide material is molybdenum disulfide, tungsten disulfide, rhenium disulfide, or tungsten diselenide.
3. The method of manufacturing a two-dimensional floating gate phototransistor according to claim 1, comprising the steps of:
the method comprises the following steps: mechanically stripping graphene to cover with thermal oxide SiO by using tape micro-mechanical stripping method 2 Identifying a single-layer graphene sheet on a back gate substrate (1) of an oxide layer (2) through an optical microscope and Raman spectroscopy to form a charge trapping layer (3);
step two: mechanically stripping a two-dimensional hexagonal boron nitride sheet onto Polydimethylsiloxane (PDMS) by using a tape micro-mechanical stripping method, identifying the qualified hexagonal boron nitride sheet on the PDMS through an optical microscope, and transferring the loaded hexagonal boron nitride sheet onto a charge trapping layer (3) by using the PDMS to form a tunneling layer (4);
step three: mechanically stripping a two-dimensional transition metal sulfide sheet onto PDMS by using a tape micro-mechanical stripping method, identifying the qualified two-dimensional transition metal sulfide sheet on the PDMS through an optical microscope, and transferring the loaded two-dimensional transition metal sulfide sheet onto a tunneling layer (4) by using the PDMS to form a two-dimensional semiconductor channel layer (5);
step four: preparing a strip-shaped metal gold electrode by utilizing photoetching, thermal evaporation and metal stripping processes, and transferring the strip-shaped metal gold electrode onto a two-dimensional semiconductor channel layer (5) by utilizing PDMS (polydimethylsiloxane) to form a source electrode (6) and a drain electrode (7);
step five: the charge trapping layer (3) is pre-programmed by applying voltage pulses with different polarities to the back gate substrate (1), so that four different reconfigurable nonvolatile photoelectric logics of AND, OR, NAND and NOR are realized under different floating gate characteristics of the charge trapping layer (3).
4. The method for fabricating a two-dimensional floating gate phototransistor as recited in claim 3, wherein said first tape micro-mechanical peeling method is to peel off graphene sheets from bulk graphene material to thermal SiO oxide by using adhesive tape 2 A single-layer graphene charge-trapping layer (3) is formed on the oxide layer (2).
5. The method for preparing a two-dimensional floating gate phototransistor as recited in claim 1, wherein the tape micro-mechanical peeling method in the second step and the third step is to peel a two-dimensional material sheet from the bulk hexagonal boron nitride or the bulk transition metal sulfide material onto the PDMS by using a tape, and then transfer the two-dimensional material sheet carried by the PDMS to a specific position in an aligned manner by using a two-dimensional material micro-transfer system.
6. The method for preparing a two-dimensional floating gate phototransistor as claimed in claim 1, wherein the photolithography, thermal evaporation, metal stripping and transfer process of step four is to thermally evaporate a metal material under the masking effect of the photoresist, then to strip the metal, to form a metal gold electrode with a specific shape on the Si slide, and then to align and transfer the metal gold electrode on the slide to a specific position through a two-dimensional material transfer system by using PDMS to form the source electrode (6) and the drain electrode (7).
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140263945A1 (en) * | 2013-03-14 | 2014-09-18 | Nutech Ventures | Floating-gate transistor photodetector |
| CN109004016A (en) * | 2018-06-04 | 2018-12-14 | 国家纳米科学中心 | Asymmetric Van der Waals heterojunction device, preparation method and the usage |
| CN109887921A (en) * | 2019-01-16 | 2019-06-14 | 复旦大学 | It is a kind of that grid memory and preparation method thereof is enclosed based on two-dimensional semiconductor material |
| CN110323223A (en) * | 2019-05-16 | 2019-10-11 | 国家纳米科学中心 | Push up floating gate Van der Waals heterojunction device and preparation method thereof, optical memory |
| CN110808280A (en) * | 2019-11-12 | 2020-02-18 | 华中科技大学 | Floating gate type field effect transistor memory and manufacturing method thereof |
| CN112601037A (en) * | 2020-12-14 | 2021-04-02 | 电子科技大学 | Floating gate device-based image sensing and storage integrated pixel unit and pixel array |
| CN113299558A (en) * | 2021-05-24 | 2021-08-24 | 华东师范大学 | Floating gate structure transistor with hafnium disulfide as channel and preparation method thereof |
| CN113903856A (en) * | 2021-08-09 | 2022-01-07 | 国科大杭州高等研究院 | Novel memristor based on neural network visual perception, and preparation method and application thereof |
-
2022
- 2022-08-11 CN CN202210959972.8A patent/CN115332079A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140263945A1 (en) * | 2013-03-14 | 2014-09-18 | Nutech Ventures | Floating-gate transistor photodetector |
| CN109004016A (en) * | 2018-06-04 | 2018-12-14 | 国家纳米科学中心 | Asymmetric Van der Waals heterojunction device, preparation method and the usage |
| CN109887921A (en) * | 2019-01-16 | 2019-06-14 | 复旦大学 | It is a kind of that grid memory and preparation method thereof is enclosed based on two-dimensional semiconductor material |
| CN110323223A (en) * | 2019-05-16 | 2019-10-11 | 国家纳米科学中心 | Push up floating gate Van der Waals heterojunction device and preparation method thereof, optical memory |
| CN110808280A (en) * | 2019-11-12 | 2020-02-18 | 华中科技大学 | Floating gate type field effect transistor memory and manufacturing method thereof |
| CN112601037A (en) * | 2020-12-14 | 2021-04-02 | 电子科技大学 | Floating gate device-based image sensing and storage integrated pixel unit and pixel array |
| CN113299558A (en) * | 2021-05-24 | 2021-08-24 | 华东师范大学 | Floating gate structure transistor with hafnium disulfide as channel and preparation method thereof |
| CN113903856A (en) * | 2021-08-09 | 2022-01-07 | 国科大杭州高等研究院 | Novel memristor based on neural network visual perception, and preparation method and application thereof |
Non-Patent Citations (4)
| Title |
|---|
| MINH DAO TRAN, ET AL.: "Two-Terminal Multibit Optical Memory via van der Waals Heterostructure", 《ADV. MATER.》, pages 1 - 8 * |
| MINH DAO TRAN, ET AL.: "Two-Terminal Multibit Optical Memory via van der Waals Heterostructure", ADV. MATER., 27 December 2018 (2018-12-27), pages 1 - 8 * |
| YILIN SUN, ET AL.: "Programmable van-der-Waals heterostructure-enabled optoelectronic synaptic floating-gate transistors with ultra-low energy consumption", 《INFOMAT.》, pages 1 - 12 * |
| 陈玉倩: "基于 PtS2/h-BN/Graphene 的浮栅型光电存储器性能研究", CNKI, 15 March 2020 (2020-03-15), pages 1 - 52 * |
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