CN109887921A - It is a kind of that grid memory and preparation method thereof is enclosed based on two-dimensional semiconductor material - Google Patents
It is a kind of that grid memory and preparation method thereof is enclosed based on two-dimensional semiconductor material Download PDFInfo
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- CN109887921A CN109887921A CN201910041823.1A CN201910041823A CN109887921A CN 109887921 A CN109887921 A CN 109887921A CN 201910041823 A CN201910041823 A CN 201910041823A CN 109887921 A CN109887921 A CN 109887921A
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Abstract
It is specially a kind of that grid memory and preparation method thereof is enclosed based on two-dimensional semiconductor material the invention belongs to memory technology field.The present invention obtains that window is bigger, retention time longer nonvolatile memory by enhancing the grid-control ability of device using single grid structure of enclosing structure substitution legacy memory.Preparation process of the present invention includes: first successively to obtain successively metal gates, dielectric layer, electric charge capture layer, tunnel layer and channel material using the methods of electron beam evaporation, atomic layer deposition, mechanical stripping and chemical vapor deposition on substrate, then obtains enclosing structure in reverse order using above-mentioned same procedure.The present invention can prepare the novel memory devices with larger memory window and longer retention time, greatly enhance grid voltage to the control ability of device, can be widely used in future memory field.
Description
Technical field
The invention belongs to memory technology fields, and in particular to it is a kind of based on two-dimensional semiconductor material enclose grid memory and
Preparation method.
Background technique
Semiconductor material memory is a big key areas in modern science and technology.Traditional semiconductor memory is using single
One grid (top gate structure or back grid structure) carrys out control device, when the thickness of channel material is larger, applies electricity in control grid
After pressure, it is possible that channel does not have completely depleted phenomenon, therefore grid needs to be strengthened the control ability of channel.
On the other hand, with the development of semiconductor technology, Moore's Law is already close to the limit, the feature ruler of semiconductor devices
To interconnection technique, micro-processing technology etc., higher requirements are also raised for very little diminution, while some corresponding problems, example also occurs
Such as short-channel effect, quantum effect can largely reduce the performance of silicon-based devices.Therefore, it is necessary to find a kind of to take
For the new material of conventional semiconductors silicon.In recent years, the two-dimensional materials such as graphene are receive more and more attention.Solely by it
Special structure and excellent performance, these two-dimensional materials are widely applied in memory, are expected to that silicon is replaced to become novel
The strong candidate of electronic device.
In the present invention, traditional single grid is substituted with enclosing structure as channel material using two-dimensional material film,
Grid is greatly enhanced to the control ability of channel, obtains that memory window is bigger, retention time longer memory.
Summary of the invention
Grid memory is enclosed based on two-dimensional semiconductor material the purpose of the present invention is to provide a kind of device performance is excellent
And preparation method thereof.
The present invention is by metal gates, insulating oxide, electric charge capture layer, tunnel layer, the channel of traditional vertical stacks stacked
The structure of material is changed to enclosed structure, realizes better grid control.
Preparation method provided by the invention that enclose grid memory based on two-dimensional semiconductor material, specific steps are as follows:
(1) metal gates are prepared on preprepared substrate
Specific method includes: to be exposed photoresist at required electrode pattern on sample using photoetching process；Then in sample
Upper deposit metal forms electrode.
Preferably, the photoetching process uses ultraviolet photolithographic or e-beam lithography.
Preferably, the method for the deposit metal can be physical vapour deposition (PVD) or electron beam evaporation.
Preferably, the metal is common Au, Cr, Pt etc..
(2) oxidation insulating layer is grown on metal gates
The oxidation insulating layer can be aluminium oxide or silica etc..
The growing method of the oxidation insulating layer is Atomic layer deposition method.
(3) two-dimensional material electric charge capture layer is grown on the insulating layer
Preferably, the two-dimensional charge trapping layer materials are graphene.
Preferably, the two-dimensional charge trapping layer materials can be prepared by two methods: one is by block-shaped material
The method of mechanical stripping directly acquires on material；Another kind be by chemical vapor deposition growth large area and the controllable number of plies it is thin
Film.
(4) two-dimensional material tunnel layer is grown on electric charge capture layer
Preferably, the two-dimentional tunnelling layer material is BN.
Preferably, the two-dimentional tunnelling layer material can be by mechanically pulling off or the method for chemical vapor deposition obtains.
(5) two-dimentional channel material is grown on the tunneling layer
Preferably, the two-dimentional channel material is MoS2。
Preferably, the length of the two-dimentional channel material is greater than the length of enclosing structure.
Preferably, the two-dimentional channel material can be by mechanically pulling off or the method for chemical vapor deposition obtains.
(6) BN, graphene, oxidation insulating layer, metal electrode are successively grown in channel material, form enclosing structure
Preferably, the BN and graphene are by mechanically pulling off method or chemical vapor deposition method obtains.
Preferably, the oxidation insulating layer, metal electrode pass through atomic layer deposition respectively and electron beam evaporation obtains.
(7) metal electrode of certain figure is prepared on above-mentioned sample as source electrode and drain electrode
Preferably, the preparation method of the metal electrode is identical as the preparation method of above-mentioned metal electrode.
Effect of the present invention
The present invention uses enclosing structure to enhance grid to the control ability of channel, after grid applies control voltage, it is ensured that channel
In fully depleted state, memory window is increased.Simultaneously as there is the charge of greater number to enter in capture layer, grid are removed
It needs after pressure and returns in channel for more time, therefore the holding time of data is longer compared with legacy memory.
The present invention realizes grid voltage to the strong control action of channel, greatly improves device performance, in future
Two-dimensional material memory area has very big development potentiality.
Detailed description of the invention
Fig. 1 is the schematic diagram after grown metal gates.
Fig. 2 is the schematic diagram after grown oxidation insulating layer.
Fig. 3 is the schematic diagram after grown electric charge capture layer.
Fig. 4 is the schematic diagram after grown tunnel layer.
Fig. 5 is the schematic diagram after being prepared for channel material.
Fig. 6 is the schematic diagram covered after tunnel layer in channel material.
Fig. 7 is the schematic diagram covered after electric charge capture layer on the tunneling layer.
Fig. 8 is the schematic diagram covered after insulating oxide on electric charge capture layer.
Fig. 9 is the schematic diagram after being prepared for enclosing structure.
Figure 10 is the schematic diagram that deposited after metal source and drain electrode.
Figure 11 is to prepare the flow chart for enclosing grid memory based on two-dimensional semiconductor material.
Specific embodiment
It is below detailed description of the present invention embodiment, examples of the embodiments are shown in the accompanying drawings, wherein from beginning extremely
Same or similar label indicates same or similar material or method with the same or similar functions eventually.Below with reference to
The embodiment of attached drawing description is exemplary, and for explaining only the invention, and is not construed as limiting the claims.For letter
Change disclosure of the invention, hereinafter the material of specific examples and method are described.Certainly, they are merely examples, and
It is not intended to limit the present invention.In addition, the present invention provides various specific techniques and material example, but this field
Those of ordinary skill can be appreciated that the applicable property of other techniques and/or the use of other materials.
Hereinafter, being directed to the system according to the present invention that enclose grid memory based on two-dimensional semiconductor material according to appended attached drawing
Standby mode, which is illustrated, to be illustrated.
Fig. 1 shows the structure after grown metal gates, including substrate 1001, positioned at the metal gates of substrate
1002。
Fig. 2, shows the structure after grown oxidation insulating layer on metal gates, including substrate 1001, is located at substrate
On metal gates 1002 and oxidation insulating layer 1003.
Fig. 3, shows the structure after grown electric charge capture layer on oxidation insulating layer, including substrate 1001, is located at lining
Metal gates 1002 on bottom, the oxidation insulating layer 1003 on grid and the charge on oxidation insulating layer
Capture layer 1004.
Fig. 4, shows the structure after grown tunnel layer on electric charge capture layer, including substrate 1001, be located at substrate it
On metal gates 1002, the oxidation insulating layer 1003 on grid, the electric charge capture layer on oxidation insulating layer
1004 and the tunnel layer 1005 on capture layer.
Fig. 5, shows the structure after grown two-dimentional channel material on the tunneling layer, including substrate 1001, is located at substrate
On metal gates 1002, the oxidation insulating layer 1003 on grid, the electric charge capture on oxidation insulating layer
Layer 1004, the tunnel layer 1005 on capture layer and the two-dimentional channel material 1006 on tunnel layer.
Fig. 6 to Fig. 9 shows and successively grown tunnel layer, electric charge capture layer, oxide isolated in two-dimentional channel material
Layer, the structure after metal gates, including substrate 1001, metal gates 1002, oxidation insulating layer 1003, electric charge capture layer 1004,
Tunnel layer 1005 and two-dimentional channel material 1006.
Figure 10, the structure after showing deposit source electrode and drain electrode, including substrate 1001, metal gates 1002, two-dimentional channel
Material 1006 and source electrode and drain electrode 1007.
Below according to each step of enclosing grid memory of the manufacture based on two-dimensional semiconductor material, in conjunction with Fig. 1 to 10, for tool
An example of body is illustrated.
Firstly, in step s 11, silicon substrate film is put into acetone soln, impregnates two minutes, then removed with isopropanol
Remaining acetone is simultaneously dried up with nitrogen gun.Then again on clean substrate through lithographic definition electrode pattern, and one layer is deposited
Metal gates.In this example, by electron beam lithography, exposure, development obtain the photoetching containing metal pattern on sample
Glue.One layer of metal is finally deposited, metal gates 1002 are formed.Metal electrode can be Au, Cr, Ag, Pt etc., can be wanted according to device
Seek selection electrode.The method of deposit metal electrodes, including use physical vapour deposition (PVD), electron beam evaporation or magnetron sputtering etc.
Deposited metal film.Preferably, one layer of golden film is deposited by electron beam evaporation.After removing photoresist using acetone, it is left
Metallic pattern be required electrode.
Then, in step s 12, oxidation insulating layer 1003 is grown by the method for atomic layer deposition.In this example, it sinks
The aluminium oxide of 30 nanometer thickness of product is as insulating layer.But the present invention is not limited thereto, the thickness of oxidation insulating layer can be as needed
It is adjusted.Preferably, the oxidation insulating layer of 30 to 40 nano thickness.
Then, in step s 13, one layer of certain thickness graphene is shifted on insulating layer 1003 (be also possible to other
Two-dimensional material) 1004 be used as electric charge capture layer.
Next, shifting one layer of certain thickness BN1005 on capture layer 1004 as tunnel layer in step S14.
Next, shifting one layer of certain thickness MoS on tunnel layer 1005 in step S152(it is also possible to other
Two-dimensional material) the two-dimentional channel material of 1006 conducts.Channel material length is greater than the length of final prepared enclosing structure.
Two-dimensional material graphene, BN, MoS are grown using the method for mechanical stripping in this example2.But the present invention is unlimited
Due to this, these two-dimensional materials can also be obtained using the methods of chemical vapor deposition.
Later, in step s 16, according to the growing method of above-mentioned respective material be sequentially prepared tunnel layer, electric charge capture layer,
Oxidation insulating layer and metal gates form enclosing structure.
Finally, by lithographic definition electrode pattern, and depositing one layer of metal as source electrode and drain electrode in step S17
1007.In this example, electrode preparation method is identical with the above-mentioned method for preparing metal gates.
It can prepare according to the present invention and grid memory is enclosed based on two-dimensional semiconductor material, to realize high performance novel deposit
Reservoir.
More than, it has been carried out in detail for the grid memory preparation method of enclosing of the invention based on two-dimensional semiconductor material
It is bright, but the present invention is not limited to example above, in the range for not departing from main idea of the present invention, can also carry out various improvement, become
Shape.
Claims (9)
1. a kind of preparation method for enclosing grid memory based on two-dimensional semiconductor material, which is characterized in that specific steps are as follows:
(1) metal gates are prepared on substrate；
(2) oxidation insulating layer is grown on metal gates；
(3) two-dimensional material electric charge capture layer is grown on the insulating layer；
(4) two-dimensional material tunnel layer is grown on electric charge capture layer；
(5) two-dimentional channel material is grown on the tunneling layer；
(6) BN, graphene, oxidation insulating layer, metal electrode are successively grown in channel material, form enclosing structure；
(7) metal electrode of certain figure is prepared on above-mentioned sample as source electrode and drain electrode.
2. preparation method according to claim 1, which is characterized in that in step (1), the side for preparing metal gates
Method: photoresist is exposed into required electrode pattern on sample using photoetching process；Then metal is deposited on sample to be formed
Electrode.
3. preparation method according to claim 2, which is characterized in that in step (1), the photoetching process is ultraviolet photolithographic
Or e-beam lithography；The method of the deposit metal is physical vapour deposition (PVD) or electron beam evaporation；The metal be Au,
Cr or Pt.
4. preparation method according to claim 3, which is characterized in that in step (2), the oxidation insulating layer is aluminium oxide
Or silica；The growing method of the oxidation insulating layer is Atomic layer deposition method.
5. preparation method described in one of -4 according to claim 1, which is characterized in that in step (3), the two-dimensional charge capture
Layer material is graphene；The two-dimensional charge trapping layer materials are prepared by two methods: one is by bulk material
The method of mechanical stripping directly acquires；Another kind is the film by chemical vapor deposition growth large area and the controllable number of plies.
6. preparation method according to claim 5, which is characterized in that in step (4), the two dimension tunnelling layer material is
BN；The two dimension tunnelling layer material is by mechanically pulling off or the method for chemical vapor deposition obtains.
7. preparation method according to claim 6, which is characterized in that in step (5), the two dimension channel material is MoS2；
The length of the two dimension channel material is greater than the length of enclosing structure.
8. preparation method according to claim 6 or 7, which is characterized in that in step (6), the BN and graphene pass through
Mechanical stripping method or chemical vapor deposition method obtain；The oxidation insulating layer, metal electrode pass through atomic layer deposition respectively
Long-pending and electron beam evaporation obtains.
9. what the preparation method as described in one of claim 1-7 obtained encloses grid memory based on two-dimensional semiconductor material.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115332079A (en) * | 2022-08-11 | 2022-11-11 | 西安电子科技大学 | Preparation method and application of two-dimensional floating gate phototransistor |
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| CN106601815A (en) * | 2016-11-28 | 2017-04-26 | 深圳大学 | Ring-gate structure field effect transistor and preparation method thereof |
| CN107665894A (en) * | 2017-09-12 | 2018-02-06 | 复旦大学 | Half floating-gate memory based on two-dimensional semiconductor material and preparation method thereof |
| CN107845687A (en) * | 2017-10-27 | 2018-03-27 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, electronic equipment |
| CN108666314A (en) * | 2018-04-09 | 2018-10-16 | 复旦大学 | Quasi- nonvolatile memory and preparation method thereof based on the controllable PN junction of two-dimensional material |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601815A (en) * | 2016-11-28 | 2017-04-26 | 深圳大学 | Ring-gate structure field effect transistor and preparation method thereof |
| CN107665894A (en) * | 2017-09-12 | 2018-02-06 | 复旦大学 | Half floating-gate memory based on two-dimensional semiconductor material and preparation method thereof |
| CN107845687A (en) * | 2017-10-27 | 2018-03-27 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, electronic equipment |
| CN108666314A (en) * | 2018-04-09 | 2018-10-16 | 复旦大学 | Quasi- nonvolatile memory and preparation method thereof based on the controllable PN junction of two-dimensional material |
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| CN115332079A (en) * | 2022-08-11 | 2022-11-11 | 西安电子科技大学 | Preparation method and application of two-dimensional floating gate phototransistor |
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